IT1172111B - Sistema di elaborazione dati
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Sistema di elaborazione dati
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Publication number
IT1172111B
IT1172111BIT49788/81AIT4978881AIT1172111BIT 1172111 BIT1172111 BIT 1172111BIT 49788/81 AIT49788/81 AIT 49788/81AIT 4978881 AIT4978881 AIT 4978881AIT 1172111 BIT1172111 BIT 1172111B
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Application filed by Dshkhunian Valery, Ivanov Eduard Evgenievich, Kovalenko Sergei S, Mashevich Pavel R, Alexei Alexeevich Ryzhov, Telenkov Vyacheslav V, Chicherin Yurij EfiledCriticalDshkhunian Valery
Priority to IT49788/81ApriorityCriticalpatent/IT1172111B/it
Publication of IT8149788A0publicationCriticalpatent/IT8149788A0/it
Application grantedgrantedCritical
Publication of IT1172111BpublicationCriticalpatent/IT1172111B/it
Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions