JPS5789163A - Common memory access system - Google Patents
Common memory access systemInfo
- Publication number
- JPS5789163A JPS5789163A JP55164214A JP16421480A JPS5789163A JP S5789163 A JPS5789163 A JP S5789163A JP 55164214 A JP55164214 A JP 55164214A JP 16421480 A JP16421480 A JP 16421480A JP S5789163 A JPS5789163 A JP S5789163A
- Authority
- JP
- Japan
- Prior art keywords
- memories
- common memory
- rank
- common
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Abstract
PURPOSE:To simplify the program processing in case of changing a system configuration, by giving a logical rank to plural common memories, and designating the logical rank when each processor accesses the common memory. CONSTITUTION:Plural common memories 1a, 1b are made double, plural processors 2a-2d are connected to the memories 1a, 1b by a common memory bus 3 and a rank designating line 4, and the same processing is shared in its load by each processor 2a-2d. To these memories 1a, 1b, logical ranks A, B are given, and the ranks A, B of the memories 1a, 1b are designated through the rank designating line 4 from each processor 2a-2d. Subsequently, the common memory operation is set so that the read and write operations can be executed, without giving statuses 1-4 of status No., and the program processing in case of changing a system configuration is simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55164214A JPH0614328B2 (en) | 1980-11-21 | 1980-11-21 | Common memory access method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55164214A JPH0614328B2 (en) | 1980-11-21 | 1980-11-21 | Common memory access method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5789163A true JPS5789163A (en) | 1982-06-03 |
JPH0614328B2 JPH0614328B2 (en) | 1994-02-23 |
Family
ID=15788829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55164214A Expired - Lifetime JPH0614328B2 (en) | 1980-11-21 | 1980-11-21 | Common memory access method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0614328B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0372578A2 (en) * | 1988-12-09 | 1990-06-13 | Tandem Computers Incorporated | Memory management in high-performance fault-tolerant computer system |
-
1980
- 1980-11-21 JP JP55164214A patent/JPH0614328B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0372578A2 (en) * | 1988-12-09 | 1990-06-13 | Tandem Computers Incorporated | Memory management in high-performance fault-tolerant computer system |
Also Published As
Publication number | Publication date |
---|---|
JPH0614328B2 (en) | 1994-02-23 |
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