IT1150096B - Metodo per fabbricare un transistor con un profilo ideale delle impurita della base - Google Patents

Metodo per fabbricare un transistor con un profilo ideale delle impurita della base

Info

Publication number
IT1150096B
IT1150096B IT26721/80A IT2672180A IT1150096B IT 1150096 B IT1150096 B IT 1150096B IT 26721/80 A IT26721/80 A IT 26721/80A IT 2672180 A IT2672180 A IT 2672180A IT 1150096 B IT1150096 B IT 1150096B
Authority
IT
Italy
Prior art keywords
transistor
manufacturing
ideal profile
base impurities
impurities
Prior art date
Application number
IT26721/80A
Other languages
English (en)
Other versions
IT8026721A0 (it
Inventor
Billy Lee Crowder
Randall Duane Isaac
Hung Ning Tak
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8026721A0 publication Critical patent/IT8026721A0/it
Application granted granted Critical
Publication of IT1150096B publication Critical patent/IT1150096B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
IT26721/80A 1979-12-28 1980-12-18 Metodo per fabbricare un transistor con un profilo ideale delle impurita della base IT1150096B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1979/001137 WO1981001911A1 (en) 1979-12-28 1979-12-28 Method for achieving ideal impurity base profile in a transistor

Publications (2)

Publication Number Publication Date
IT8026721A0 IT8026721A0 (it) 1980-12-18
IT1150096B true IT1150096B (it) 1986-12-10

Family

ID=22147840

Family Applications (1)

Application Number Title Priority Date Filing Date
IT26721/80A IT1150096B (it) 1979-12-28 1980-12-18 Metodo per fabbricare un transistor con un profilo ideale delle impurita della base

Country Status (6)

Country Link
EP (1) EP0042380B1 (it)
JP (1) JPS6410951B2 (it)
CA (1) CA1160363A (it)
DE (1) DE2967588D1 (it)
IT (1) IT1150096B (it)
WO (1) WO1981001911A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536950A (en) * 1983-02-10 1985-08-27 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor device
US4912053A (en) * 1988-02-01 1990-03-27 Harris Corporation Ion implanted JFET with self-aligned source and drain
JPH02153534A (ja) * 1988-12-06 1990-06-13 Toshiba Corp 半導体装置の製造方法
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
US3389023A (en) * 1966-01-14 1968-06-18 Ibm Methods of making a narrow emitter transistor by masking and diffusion
US3432920A (en) * 1966-12-01 1969-03-18 Rca Corp Semiconductor devices and methods of making them
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
FR1569872A (it) * 1968-04-10 1969-06-06
US3717507A (en) * 1969-06-19 1973-02-20 Shibaura Electric Co Ltd Method of manufacturing semiconductor devices utilizing ion-implantation and arsenic diffusion
US3886569A (en) * 1970-01-22 1975-05-27 Ibm Simultaneous double diffusion into a semiconductor substrate
NL7116688A (it) * 1970-12-09 1972-06-13
US3753807A (en) * 1972-02-24 1973-08-21 Bell Canada Northern Electric Manufacture of bipolar semiconductor devices
US3856578A (en) * 1972-03-13 1974-12-24 Bell Telephone Labor Inc Bipolar transistors and method of manufacture
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
US3880676A (en) * 1973-10-29 1975-04-29 Rca Corp Method of making a semiconductor device
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
EP0042380A4 (en) 1983-04-18
JPS6410951B2 (it) 1989-02-22
DE2967588D1 (en) 1986-04-24
EP0042380A1 (en) 1981-12-30
WO1981001911A1 (en) 1981-07-09
EP0042380B1 (en) 1986-03-19
CA1160363A (en) 1984-01-10
JPS56501585A (it) 1981-10-29
IT8026721A0 (it) 1980-12-18

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