IN2012DN02104A - - Google Patents

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Publication number
IN2012DN02104A
IN2012DN02104A IN2104DEN2012A IN2012DN02104A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A IN 2104DEN2012 A IN2104DEN2012 A IN 2104DEN2012A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A
Authority
IN
India
Prior art keywords
user
processor core
level interrupt
application thread
thread executing
Prior art date
Application number
Other languages
English (en)
Inventor
Jaewoong Chung
Karin Strauss
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02104A publication Critical patent/IN2012DN02104A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/16—Arrangements for providing special services to substations
    • H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
    • H04L12/1881—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast with schedule organisation, e.g. priority, sequence management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
IN2104DEN2012 2009-08-14 2010-08-05 IN2012DN02104A (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23398309P 2009-08-14 2009-08-14
US12/633,034 US8285904B2 (en) 2009-08-14 2009-12-08 Flexible notification mechanism for user-level interrupts
US12/633,032 US8356130B2 (en) 2009-08-14 2009-12-08 Mechanism for recording undeliverable user-level interrupts
US12/633,007 US8255603B2 (en) 2009-08-14 2009-12-08 User-level interrupt mechanism for multi-core architectures
PCT/US2010/044528 WO2011019578A1 (en) 2009-08-14 2010-08-05 User-level interrupt mechanism for multi-core architectures

Publications (1)

Publication Number Publication Date
IN2012DN02104A true IN2012DN02104A (pt) 2015-08-21

Family

ID=43589266

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2104DEN2012 IN2012DN02104A (pt) 2009-08-14 2010-08-05

Country Status (7)

Country Link
US (3) US8356130B2 (pt)
EP (1) EP2465032B1 (pt)
JP (1) JP5646628B2 (pt)
KR (1) KR101651246B1 (pt)
CN (1) CN102483705B (pt)
IN (1) IN2012DN02104A (pt)
WO (1) WO2011019578A1 (pt)

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CN102520916B (zh) * 2011-11-28 2015-02-11 深圳中微电科技有限公司 在mvp处理器中消除纹理延迟和寄存器管理的方法
US9552313B2 (en) * 2011-12-28 2017-01-24 Intel Corporation Delivering real time interrupts with an advanced programmable interrupt controller
KR101331957B1 (ko) * 2012-01-11 2013-11-21 엘아이지넥스원 주식회사 범용 운영체제의 실시간성 쓰레드 처리를 위한 커널 구성 방법
US9785133B2 (en) * 2012-02-10 2017-10-10 Fisher-Rosemount Systems, Inc. Methods for collaboratively assisting a control room operator
US8849731B2 (en) * 2012-02-23 2014-09-30 Microsoft Corporation Content pre-fetching for computing devices
US9043522B2 (en) 2012-10-17 2015-05-26 Arm Limited Handling interrupts in a multi-processor system
US9208113B2 (en) 2013-01-15 2015-12-08 Apple Inc. Deferred inter-processor interrupts
US9495311B1 (en) * 2013-12-17 2016-11-15 Google Inc. Red zone avoidance for user mode interrupts
US9594704B1 (en) 2013-12-17 2017-03-14 Google Inc. User mode interrupts
WO2015096120A1 (en) * 2013-12-27 2015-07-02 Intel Corporation Techniques for implementing a secure mailbox in resource-constrained embedded systems
US9563588B1 (en) 2014-01-29 2017-02-07 Google Inc. OS bypass inter-processor interrupt delivery mechanism
US9542254B2 (en) 2014-07-30 2017-01-10 International Business Machines Corporation Application-level signal handling and application-level memory protection
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
EP3855318B1 (en) * 2014-09-26 2024-02-14 INTEL Corporation Apparatus and method for configuring sets of interrupts
US9910699B2 (en) 2014-10-28 2018-03-06 Intel Corporation Virtual processor direct interrupt delivery mechanism
US9928094B2 (en) * 2014-11-25 2018-03-27 Microsoft Technology Licensing, Llc Hardware accelerated virtual context switching
US9921984B2 (en) * 2014-12-23 2018-03-20 Intel Corporation Delivering interrupts to user-level applications
US10002103B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10002102B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10922252B2 (en) * 2015-06-22 2021-02-16 Qualcomm Incorporated Extended message signaled interrupts (MSI) message data
CN105094976A (zh) * 2015-10-09 2015-11-25 天津国芯科技有限公司 一种中断控制方法和中断控制器
CN105808338A (zh) * 2016-03-17 2016-07-27 李晓波 一种在处理中实现中断响应核可配置的方法及装置
CN107800546B (zh) * 2016-08-31 2021-03-30 华为技术有限公司 一种广播消息的管理方法及装置
US10496572B1 (en) 2017-03-06 2019-12-03 Apple Inc. Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled
US10467162B2 (en) * 2017-03-31 2019-11-05 Hewlett Packard Enterprise Development Lp Interrupt based on a last interrupt request indicator and a work acknowledgement
US10838760B2 (en) * 2017-11-29 2020-11-17 Nxp Usa, Inc. Systems and methods for interrupt distribution
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TWI703501B (zh) * 2018-08-23 2020-09-01 慧榮科技股份有限公司 具有分散式信箱架構的多處理器系統及其溝通方法
US11321144B2 (en) 2019-06-29 2022-05-03 Intel Corporation Method and apparatus for efficiently managing offload work between processing units
US11372711B2 (en) 2019-06-29 2022-06-28 Intel Corporation Apparatus and method for fault handling of an offload transaction
US11182208B2 (en) 2019-06-29 2021-11-23 Intel Corporation Core-to-core start “offload” instruction(s)
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Also Published As

Publication number Publication date
EP2465032B1 (en) 2020-12-16
JP5646628B2 (ja) 2014-12-24
US8255603B2 (en) 2012-08-28
US20110040913A1 (en) 2011-02-17
US8285904B2 (en) 2012-10-09
WO2011019578A1 (en) 2011-02-17
CN102483705A (zh) 2012-05-30
JP2013502004A (ja) 2013-01-17
US20110040914A1 (en) 2011-02-17
US8356130B2 (en) 2013-01-15
CN102483705B (zh) 2014-12-17
KR20120062768A (ko) 2012-06-14
US20110040915A1 (en) 2011-02-17
EP2465032A1 (en) 2012-06-20
KR101651246B1 (ko) 2016-09-05

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