IN2012DN02104A - - Google Patents

Download PDF

Info

Publication number
IN2012DN02104A
IN2012DN02104A IN2104DEN2012A IN2012DN02104A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A IN 2104DEN2012 A IN2104DEN2012 A IN 2104DEN2012A IN 2012DN02104 A IN2012DN02104 A IN 2012DN02104A
Authority
IN
India
Prior art keywords
user
processor core
level interrupt
application thread
thread executing
Prior art date
Application number
Inventor
Jaewoong Chung
Karin Strauss
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02104A publication Critical patent/IN2012DN02104A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/16—Arrangements for providing special services to substations
    • H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
    • H04L12/1881—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast with schedule organisation, e.g. priority, sequence management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.
IN2104DEN2012 2009-08-14 2010-08-05 IN2012DN02104A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23398309P 2009-08-14 2009-08-14
US12/633,034 US8285904B2 (en) 2009-08-14 2009-12-08 Flexible notification mechanism for user-level interrupts
US12/633,032 US8356130B2 (en) 2009-08-14 2009-12-08 Mechanism for recording undeliverable user-level interrupts
US12/633,007 US8255603B2 (en) 2009-08-14 2009-12-08 User-level interrupt mechanism for multi-core architectures
PCT/US2010/044528 WO2011019578A1 (en) 2009-08-14 2010-08-05 User-level interrupt mechanism for multi-core architectures

Publications (1)

Publication Number Publication Date
IN2012DN02104A true IN2012DN02104A (en) 2015-08-21

Family

ID=43589266

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2104DEN2012 IN2012DN02104A (en) 2009-08-14 2010-08-05

Country Status (7)

Country Link
US (3) US8285904B2 (en)
EP (1) EP2465032B1 (en)
JP (1) JP5646628B2 (en)
KR (1) KR101651246B1 (en)
CN (1) CN102483705B (en)
IN (1) IN2012DN02104A (en)
WO (1) WO2011019578A1 (en)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102077181B (en) * 2008-04-28 2014-07-02 惠普开发有限公司 Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems
US8285904B2 (en) * 2009-08-14 2012-10-09 Advanced Micro Devices, Inc. Flexible notification mechanism for user-level interrupts
US8566492B2 (en) * 2009-12-31 2013-10-22 Intel Corporation Posting interrupts to virtual processors
US9652365B2 (en) * 2010-08-24 2017-05-16 Red Hat, Inc. Fault configuration using a registered list of controllers
KR101717494B1 (en) * 2010-10-08 2017-03-28 삼성전자주식회사 Apparatus and Method for processing interrupt
WO2012082556A2 (en) 2010-12-15 2012-06-21 Advanced Micro Devices, Inc. Computer system interrupt handling
US8370283B2 (en) * 2010-12-15 2013-02-05 Scienergy, Inc. Predicting energy consumption
WO2013057769A1 (en) * 2011-10-20 2013-04-25 富士通株式会社 Information processing device, control method for information processing device and control program
CN102520916B (en) * 2011-11-28 2015-02-11 深圳中微电科技有限公司 Method for eliminating texture retardation and register management in MVP (multi thread virtual pipeline) processor
US9552313B2 (en) * 2011-12-28 2017-01-24 Intel Corporation Delivering real time interrupts with an advanced programmable interrupt controller
KR101331957B1 (en) * 2012-01-11 2013-11-21 엘아이지넥스원 주식회사 Method of configuring kernel for real-time thread proccsing of general purpose operating system
US9785133B2 (en) * 2012-02-10 2017-10-10 Fisher-Rosemount Systems, Inc. Methods for collaboratively assisting a control room operator
US8849731B2 (en) * 2012-02-23 2014-09-30 Microsoft Corporation Content pre-fetching for computing devices
US9043522B2 (en) * 2012-10-17 2015-05-26 Arm Limited Handling interrupts in a multi-processor system
US9208113B2 (en) 2013-01-15 2015-12-08 Apple Inc. Deferred inter-processor interrupts
US9594704B1 (en) 2013-12-17 2017-03-14 Google Inc. User mode interrupts
US9495311B1 (en) * 2013-12-17 2016-11-15 Google Inc. Red zone avoidance for user mode interrupts
WO2015096120A1 (en) * 2013-12-27 2015-07-02 Intel Corporation Techniques for implementing a secure mailbox in resource-constrained embedded systems
US9563588B1 (en) 2014-01-29 2017-02-07 Google Inc. OS bypass inter-processor interrupt delivery mechanism
US9542254B2 (en) 2014-07-30 2017-01-10 International Business Machines Corporation Application-level signal handling and application-level memory protection
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
CN106663072B (en) * 2014-09-26 2020-11-17 英特尔公司 Apparatus and method for configuring a set of interrupts
US9910699B2 (en) 2014-10-28 2018-03-06 Intel Corporation Virtual processor direct interrupt delivery mechanism
US9928094B2 (en) * 2014-11-25 2018-03-27 Microsoft Technology Licensing, Llc Hardware accelerated virtual context switching
US9921984B2 (en) * 2014-12-23 2018-03-20 Intel Corporation Delivering interrupts to user-level applications
US10002103B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10002102B2 (en) * 2015-03-13 2018-06-19 Microchip Technology Incorporated Low-pin microcontroller device with multiple independent microcontrollers
US10922252B2 (en) * 2015-06-22 2021-02-16 Qualcomm Incorporated Extended message signaled interrupts (MSI) message data
CN105094976A (en) * 2015-10-09 2015-11-25 天津国芯科技有限公司 Interrupt control method and interrupt controller
CN105808338A (en) * 2016-03-17 2016-07-27 李晓波 Method and device for realizing configurability of interrupt response kernel during processing
CN107800546B (en) 2016-08-31 2021-03-30 华为技术有限公司 Method and device for managing broadcast messages
US10496572B1 (en) 2017-03-06 2019-12-03 Apple Inc. Intracluster and intercluster interprocessor interrupts including a retract interrupt that causes a previous interrupt to be canceled
US10467162B2 (en) * 2017-03-31 2019-11-05 Hewlett Packard Enterprise Development Lp Interrupt based on a last interrupt request indicator and a work acknowledgement
US10838760B2 (en) * 2017-11-29 2020-11-17 Nxp Usa, Inc. Systems and methods for interrupt distribution
US11687366B2 (en) 2018-07-24 2023-06-27 Mitsubishi Electric Corporation Interrupt handling method, computer system, and non-transitory storage medium that resumes waiting threads in response to interrupt signals from I/O devices
TWI680375B (en) 2018-08-23 2019-12-21 慧榮科技股份有限公司 Multi-processor system having distributed mailbox architecture and processor error checking method thereof
US11182208B2 (en) 2019-06-29 2021-11-23 Intel Corporation Core-to-core start “offload” instruction(s)
US11372711B2 (en) 2019-06-29 2022-06-28 Intel Corporation Apparatus and method for fault handling of an offload transaction
US11321144B2 (en) 2019-06-29 2022-05-03 Intel Corporation Method and apparatus for efficiently managing offload work between processing units
US11366769B1 (en) * 2021-02-25 2022-06-21 Microsoft Technology Licensing, Llc Enabling peripheral device messaging via application portals in processor-based devices
US12430162B2 (en) 2021-09-30 2025-09-30 Intel Corporation User-level interprocessor interrupts
CN114329439A (en) * 2021-11-18 2022-04-12 平头哥(上海)半导体技术有限公司 System on chip, interrupt isolation method and computer equipment
US12174765B2 (en) * 2022-03-29 2024-12-24 Mellanox Technologies, Ltd. Interrupt emulation on network devices
CN116578530A (en) * 2023-04-28 2023-08-11 平头哥(上海)半导体技术有限公司 System on chip, interrupt isolation method and computer equipment
CN119182817B (en) * 2024-09-04 2025-10-17 浙江吉利控股集团有限公司 SSE stream output interrupt control method, device, server and medium

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05189252A (en) * 1992-01-13 1993-07-30 Meidensha Corp Event processing method for software
US5909582A (en) 1996-04-26 1999-06-01 Nec Corporation Microcomputer having user mode interrupt function and supervisor mode interrupt function
US6061709A (en) * 1998-07-31 2000-05-09 Integrated Systems Design Center, Inc. Integrated hardware and software task control executive
US6370606B1 (en) * 1998-11-05 2002-04-09 Compaq Computer Corporation System and method for simulating hardware interrupts in a multiprocessor computer system
US6148361A (en) * 1998-12-17 2000-11-14 International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
JP4057769B2 (en) 2000-08-31 2008-03-05 松下電器産業株式会社 Interrupt management device and interrupt management method
US7529235B2 (en) * 2000-12-06 2009-05-05 Franklin Zhigang Zhang Internet based time distributed message network system and personal mobile access device
US7392282B2 (en) * 2001-03-14 2008-06-24 International Business Machines Corporation Method for ensuring client access to messages from a server
JP2005190207A (en) * 2003-12-25 2005-07-14 Matsushita Electric Ind Co Ltd Interrupt control device and control method
GB0404696D0 (en) * 2004-03-02 2004-04-07 Level 5 Networks Ltd Dual driver interface
US7080179B1 (en) * 2004-03-26 2006-07-18 Foundry Networks, Inc. Multi-level interrupts
US9189230B2 (en) 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US7689747B2 (en) * 2005-03-28 2010-03-30 Microsoft Corporation Systems and methods for an augmented interrupt controller and synthetic interrupt sources
US7581051B2 (en) * 2005-05-16 2009-08-25 Microsoft Corporation Method for delivering interrupts to user mode drivers
US20070073928A1 (en) * 2005-09-26 2007-03-29 John Bruno High-speed input/output signaling mechanism using a polling CPU and cache coherency signaling
US7493436B2 (en) * 2006-10-26 2009-02-17 International Business Machines Corporation Interrupt handling using simultaneous multi-threading
US8689215B2 (en) * 2006-12-19 2014-04-01 Intel Corporation Structured exception handling for application-managed thread units
US7627706B2 (en) * 2007-09-06 2009-12-01 Intel Corporation Creation of logical APIC ID with cluster ID and intra-cluster ID
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US8285904B2 (en) * 2009-08-14 2012-10-09 Advanced Micro Devices, Inc. Flexible notification mechanism for user-level interrupts

Also Published As

Publication number Publication date
CN102483705A (en) 2012-05-30
US20110040915A1 (en) 2011-02-17
KR20120062768A (en) 2012-06-14
US20110040914A1 (en) 2011-02-17
US8255603B2 (en) 2012-08-28
CN102483705B (en) 2014-12-17
US8356130B2 (en) 2013-01-15
WO2011019578A1 (en) 2011-02-17
EP2465032A1 (en) 2012-06-20
US8285904B2 (en) 2012-10-09
EP2465032B1 (en) 2020-12-16
JP5646628B2 (en) 2014-12-24
JP2013502004A (en) 2013-01-17
US20110040913A1 (en) 2011-02-17
KR101651246B1 (en) 2016-09-05

Similar Documents

Publication Publication Date Title
IN2012DN02104A (en)
PH12013501345A1 (en) Tamper resistant solid oral dosage forms
WO2012033839A3 (en) Oxygen concentrator heat management system and method
GB2520852A (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
WO2010101788A3 (en) Access control using identifiers in links
BR112014013644A2 (en) cloud service agent realization method; cloud service agent server; and cloud service agent realization system
IN2012CN07526A (en)
MY181023A (en) Conversational message service operating method for providing acknowledgement
MX2013014175A (en) Methods and apparatus for multi-source restore.
WO2010068356A3 (en) System and method for communicating over a network with a medical device
IN2015DN02657A (en)
WO2013089782A3 (en) Co-location electrical architecture
EP2383946A4 (en) Method, server and system for providing resource for an access user
GB2520858A (en) Instruction set for message scheduling of SHA256 algorithm
WO2010043706A3 (en) Method for the deterministic execution and synchronisation of an information processing system comprising a plurality of processing cores executing system tasks
SG11201402442UA (en) A method of generation and transmission of secure tokens based on tokens generated by trng and split into shares and the system thereof
WO2011005612A3 (en) Information aggregation service
EP2773073A4 (en) Entry generation method, message receiving method, and corresponding device and system
AR081035A1 (en) RECEIVING APPLIANCE, AD CONTROL METHOD, AND PROGRAM
AR090202A1 (en) METHODS AND APPLIANCES TO REDUCE MEMORY REQUIREMENTS FOR SOFTWARE APPLICATIONS OF PROCESS CONTROL SYSTEMS
PH12014500964A1 (en) Security mechanism for external code
IN2013DE03292A (en)
IN2012DN03242A (en)
IN2013CH04831A (en)
CL2012003461A1 (en) Procedure for feeding an asymmetric three-phase current into a three-phase alternating voltage network comprising the generation of a direct system of the current to be fed, of an inverted system of the current to be fed and of the superposition of both systems; associated wind device and installation.