IN2013CH04831A - - Google Patents
Info
- Publication number
- IN2013CH04831A IN2013CH04831A IN4831CH2013A IN2013CH04831A IN 2013CH04831 A IN2013CH04831 A IN 2013CH04831A IN 4831CH2013 A IN4831CH2013 A IN 4831CH2013A IN 2013CH04831 A IN2013CH04831 A IN 2013CH04831A
- Authority
- IN
- India
- Prior art keywords
- core
- procedure
- executing
- methods
- execute
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5083—Techniques for rebalancing the load in a distributed system
- G06F9/5088—Techniques for rebalancing the load in a distributed system involving task migration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Stored Programmes (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Technologies are generally described for methods and systems effective to execute a program in a multi-core processor. In an example, methods to execute a program in a multi-core processor may include executing a first procedure on a first core of a multi-core processor. The methods may further include while executing the first procedure, sending a first and second instruction, from the first core to a second and third core, respectively. The instructions may command the cores to execute second and third procedures. The methods may further include executing the first procedure on the first core while executing the second procedure on the second core and executing the third procedure on the third core.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN4831CH2013 IN2013CH04831A (en) | 2013-10-28 | 2013-10-28 | |
PCT/US2013/077031 WO2015065500A1 (en) | 2013-10-28 | 2013-12-20 | Distributed procedure execution in multi-core processors |
US14/371,322 US9483318B2 (en) | 2013-10-28 | 2013-12-20 | Distributed procedure execution in multi-core processors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN4831CH2013 IN2013CH04831A (en) | 2013-10-28 | 2013-10-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2013CH04831A true IN2013CH04831A (en) | 2015-08-07 |
Family
ID=53004890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN4831CH2013 IN2013CH04831A (en) | 2013-10-28 | 2013-10-28 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9483318B2 (en) |
IN (1) | IN2013CH04831A (en) |
WO (1) | WO2015065500A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3673368A1 (en) | 2017-08-24 | 2020-07-01 | Lutron Technology Company LLC | Stack safety for independently defined operations |
US11182208B2 (en) | 2019-06-29 | 2021-11-23 | Intel Corporation | Core-to-core start “offload” instruction(s) |
US10983796B2 (en) | 2019-06-29 | 2021-04-20 | Intel Corporation | Core-to-core end “offload” instruction(s) |
US11372711B2 (en) | 2019-06-29 | 2022-06-28 | Intel Corporation | Apparatus and method for fault handling of an offload transaction |
US11030000B2 (en) | 2019-06-29 | 2021-06-08 | Intel Corporation | Core advertisement of availability |
US11321144B2 (en) | 2019-06-29 | 2022-05-03 | Intel Corporation | Method and apparatus for efficiently managing offload work between processing units |
US11016766B2 (en) | 2019-06-29 | 2021-05-25 | Intel Corporation | Apparatus and method for compiler hints for inter-core offload |
US10929129B2 (en) * | 2019-06-29 | 2021-02-23 | Intel Corporation | Apparatus and method for modifying addresses, data, or program code associated with offloaded instructions |
US20210311897A1 (en) | 2020-04-06 | 2021-10-07 | Samsung Electronics Co., Ltd. | Memory with cache-coherent interconnect |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5655096A (en) | 1990-10-12 | 1997-08-05 | Branigin; Michael H. | Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution |
US6665793B1 (en) * | 1999-12-28 | 2003-12-16 | Institute For The Development Of Emerging Architectures, L.L.C. | Method and apparatus for managing access to out-of-frame Registers |
US6826681B2 (en) * | 2001-06-18 | 2004-11-30 | Mips Technologies, Inc. | Instruction specified register value saving in allocated caller stack or not yet allocated callee stack |
US6804632B2 (en) * | 2001-12-06 | 2004-10-12 | Intel Corporation | Distribution of processing activity across processing hardware based on power consumption considerations |
EP1387277B1 (en) * | 2002-07-31 | 2009-07-15 | Texas Instruments Incorporated | Write back policy for memory |
US7055060B2 (en) | 2002-12-19 | 2006-05-30 | Intel Corporation | On-die mechanism for high-reliability processor |
US7769962B2 (en) * | 2005-12-12 | 2010-08-03 | Jeda Technologies, Inc. | System and method for thread creation and memory management in an object-oriented programming environment |
US7827541B2 (en) | 2006-03-16 | 2010-11-02 | International Business Machines Corporation | Method and apparatus for profiling execution of code using multiple processors |
US20070245120A1 (en) * | 2006-04-14 | 2007-10-18 | Chang Jung L | Multiple microcontroller system, instruction, and instruction execution method for the same |
US7512745B2 (en) * | 2006-04-28 | 2009-03-31 | International Business Machines Corporation | Method for garbage collection in heterogeneous multiprocessor systems |
US7543184B2 (en) * | 2006-05-23 | 2009-06-02 | The Mathworks, Inc. | System and method for distributing system tests in parallel computing environments |
US7779230B2 (en) | 2006-10-18 | 2010-08-17 | Wisconsin Alumni Research Foundation | Data flow execution of methods in sequential programs |
US8291381B2 (en) | 2007-09-27 | 2012-10-16 | Microsoft Corporation | Call stack parsing in multiple runtime environments |
DE102008005124A1 (en) | 2008-01-18 | 2009-07-23 | Kuka Roboter Gmbh | Computer system, control device for a machine, in particular for an industrial robot, and industrial robots |
US9189282B2 (en) | 2009-04-21 | 2015-11-17 | Empire Technology Development Llc | Thread-to-core mapping based on thread deadline, thread demand, and hardware characteristics data collected by a performance counter |
US9086973B2 (en) * | 2009-06-09 | 2015-07-21 | Hyperion Core, Inc. | System and method for a cache in a multi-core processor |
US9015689B2 (en) * | 2013-03-14 | 2015-04-21 | Board of Regents on Behalf of Arizona State University | Stack data management for software managed multi-core processors |
-
2013
- 2013-10-28 IN IN4831CH2013 patent/IN2013CH04831A/en unknown
- 2013-12-20 WO PCT/US2013/077031 patent/WO2015065500A1/en active Application Filing
- 2013-12-20 US US14/371,322 patent/US9483318B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US9483318B2 (en) | 2016-11-01 |
US20150220369A1 (en) | 2015-08-06 |
WO2015065500A1 (en) | 2015-05-07 |
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