JP4057769B2 - Interrupt management device and interrupt management method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention performs interrupt management in a computer processing real-time operation system (real-time OS), a multitask operation system (multitask OS) and a signal processing processor (hereinafter referred to as a DSP), and includes W-CDMA. The present invention relates to an interrupt management device and an interrupt management method suitable for use in an image terminal device such as a portable videophone device using a (Wide band-Code Division Multiple Access) system.
[0002]
[Prior art]
Conventionally, in a microprocessor system, an interrupt request from an external device or an external device or a software interrupt request from an application program being executed (hereinafter referred to as an interrupt) is executed while the microprocessor (hereinafter referred to as a CPU) is executing program processing. When an asynchronous interrupt request generated due to various factors (generally called a request) occurs, the program processing being executed is interrupted to process the interrupt request.
[0003]
On the other hand, the DSP has a main processor (hereinafter referred to as MP) for the CPU, and when an interrupt request is generated while the MP is executing a program process, the program process being executed is executed. And interrupt request is processed. In the following description, the minimum unit of a program is referred to as a task.
[0004]
Since the contents of processing for an interrupt request differ for each interrupt factor, an interrupt processing routine (hereinafter referred to as an interrupt processing task) is created for each interrupt factor in advance (created by the user), and there is an interrupt request. When an interrupt occurs, an interrupt control means (hereinafter referred to as an interrupt controller) that informs the occurrence of an interrupt informs the CPU or MP, whereby the CPU or MP identifies the cause of the interrupt and calls the corresponding interrupt processing task for processing. Is used.
[0005]
When the CPU or MP interrupts the task processing being executed due to the generation of an interrupt request, the address of the task to be resumed or the contents of the internal register of the CPU or MP used so far (hereinafter referred to as the processing resource being processed) After saving, the interrupt processing task is executed. Then, when the interrupt processing task ends, these registers are returned to the original state, and the task processing being executed is resumed.
[0006]
In the interrupt processing task, it is complicated to create the interrupt processing task because the processing of saving / restoring processing resources during processing is complicated. Therefore, in a microprocessor system having a CPU, these processes are performed in real time OS and multitasking. Usually, this is performed by calling an interrupt management mechanism of an OS (hereinafter, collectively referred to as OS: operating system) (hereinafter referred to as a system call).
[0007]
In a DSP having an MP, it is usually constructed as a monitor program as software of one separate task separated from the interrupt processing task (usually called microcode or firmware in the DSP). Hereinafter, system calls and monitor programs are collectively referred to as interrupt handlers.
[0008]
Furthermore, as an interrupt process, in the case of a single interrupt (an interrupt that prohibits acceptance of other interrupts during interrupt processing), when an interrupt occurs, the processing resource being processed by the interrupt handler and the stack area of that task Save to the task control means, and simultaneously mask the interrupt mask to disable other interrupts and perform interrupt processing. When the interrupt processing is completed and the execution of the interrupted task is resumed, the task stack information, the task control means, and the interrupt mask are restored.
[0009]
Also, in an interrupt handler with multiple interrupts (interrupts that can accept other interrupts even during interrupt processing), all interrupts are disabled when disabling interrupt masking for single interrupts. Interrupt processing is performed without prohibition and without setting an interrupt mask for the higher interrupt level. This means that in an interrupt handler having multiple interrupts, it is necessary to determine which interrupt is prohibited when an interrupt occurs for each interrupt type.
[0010]
Also, if you want to perform processing at an interrupt level that is different from the interrupt level of the interrupt processing task in the interrupt processing task, a method is used in which an interrupt is generated and processed as an interrupt processing task with a different interrupt level using software interrupts. ing.
[0011]
[Problems to be solved by the invention]
However, the conventional interrupt management method has the following problems. (1) When other interrupts can be accepted in the interrupt task, or when a certain interrupt is prohibited thereafter, it is necessary to change the processing of the interrupt handler. However, since the interrupt handler and the interrupt processing task are closely related, it is difficult to independently change the interrupt processing contents by the interrupt handler or the interrupt processing task.
[0012]
(2) In the interrupt management method using the OS, interrupt handlers in the OS collectively perform interrupt disable / permit processing for all interrupt causes, and the user interrupts the interrupt handler in the OS. It is necessary to create an interrupt processing task in consideration of the management status.
[0013]
(3) It is difficult to construct an interrupt process that does not depend on the interrupt management state of the interrupt handler in the OS.
[0014]
(4) In the interrupt processing task, when processing at an interrupt level different from the interrupt level of the interrupt processing task is desired, using a software interrupt to generate and process an interrupt as an interrupt processing task having a different interrupt level, Since a new interrupt request is generated by a software interrupt, a processing resource saving / restoring process is required, and processing efficiency deteriorates.
[0015]
(5) Japanese Patent Application Laid-Open No. 5-224951 discloses a double interrupt that designates a software interrupt and shifts the process to the OS before the process is transferred to the interrupt handler when the CPU is started by the interrupt request. An interrupt handler activation unit that activates an interrupt handler by analyzing an interrupt factor and saving registers in the OS when processing is transferred via the double interrupt designation unit; A management method is disclosed that includes an interrupt handler end processing unit that restores registers in the OS and resumes interrupted processing when the interrupt handler is notified of the end of interrupt processing.
[0016]
However, in the case of the technique described in this publication, the save / restore processing of registers in the OS and the processing in the interrupt handler are separated by providing a double interrupt designating means, and the efficiency of interrupt handler creation is improved. It is designed to improve,
No means are disclosed for separating the interrupt handler and the interrupt processing task, and there is still a problem that the interrupt processing contents cannot be changed independently by the interrupt handler or the interrupt processing task.
[0017]
Furthermore, since a double interrupt designating unit is used that designates a software interrupt and shifts the process to the OS before the process shifts to the interrupt handler, it is necessary to save and restore processing resources during processing. That is, the problem that processing efficiency deteriorates cannot be solved at all.
[0018]
The present invention has been made in view of such a point, and when it is necessary to change the processing of an interrupt handler, such as when other interrupts can be accepted within an interrupt task, or when a certain interrupt is prohibited thereafter. In addition, interrupt processing contents can be easily changed by interrupt handlers and interrupt processing tasks.
[0019]
Further, in the interrupt management method using the OS, even when interrupt handlers in the OS collectively perform interrupt disable / permit processing for all interrupt causes, the user can interrupt interrupt handlers in the OS. Interrupt processing task can be created without being aware of the interrupt management status of
[0020]
In addition, it is possible to construct interrupt processing that does not depend on the interrupt management status of the interrupt handler in the OS, and in the interrupt processing task, when processing at an interrupt level different from the interrupt level of the interrupt processing task, An object of the present invention is to provide an interrupt management device and an interrupt management method that can be realized without specifying a software interrupt that requires resource saving / restoring processing.
[0021]
[Means for Solving the Problems]
The interrupt management device of the present invention notifies the interrupt handler with an interrupt mask. Control The interrupt control means that performs the above and the interrupt handler are provided independently and prepared for each interrupt factor. And a set of interrupt masks An interrupt acceptance management means for holding an interrupt acceptance status, an interrupt mask release control means for controlling release of an interrupt mask for an interrupt factor in an interrupt processing task, and an interrupt task switch management means for managing task switching information from the interrupt processing task; The interrupt handler includes an evacuation processing means for evacuating information on a task being executed when an interrupt occurs, and an interrupt that determines an interrupt processing task to be processed according to the cause of the interrupt. Depending on the processing of the factor determination processing means, the interrupt acceptance management means and the interrupt mask release control means Remove the interrupt mask from the interrupt ready state. Multiple interrupt control means for performing interrupt mask update control, interrupt task control processing means for performing processing transition between the interrupt processing task and the interrupt handler determined by the interrupt factor determination processing means, and the interrupt task switch management The task switching information managed by the means is used to control the task switching instruction from the interrupt processing task. If there is a task switching instruction, the control is transferred to the interrupt processing task, and if there is no task switching instruction, the interrupt task control processing means is controlled. And an interrupt task switch control means for transferring the task, and a task return processing means for returning the information of the task being executed when the interrupt saved by the save processing means is generated and restarting the suspended task processing. take.
[0022]
According to this configuration, when control is transferred from the interrupt control means to the interrupt handler when an interrupt occurs, the interrupt handler save processing means saves various information of the task being executed when the interrupt occurs. When various information of the task is saved, the interrupt factor determination processing means uses the interrupt acceptance management means to determine which interrupt factor is processed for the interrupt factor notified from the interrupt control means. Determine the interrupt handling task to call.
[0023]
When an interrupt processing task is determined, the multiple interrupt control means retrieves the interrupt mask for that interrupt processing task from the interrupt acceptance management means (holding the interrupt acceptance ready state prepared for each interrupt cause), and interrupt control Set to the interrupt mask of the means. At this time, since the interrupt mask has already been set by the interrupt mask of the interrupt control means when an interrupt occurs, no change is made to the interrupt mask for the interrupt factor for which the interrupt is disabled. In contrast to the interrupt mask state set in the interrupt control means when an interrupt occurs, the mask for the interrupt factor determined by the interrupt factor determination processing means is disabled, and the interrupt mask state is saved. Further, the state of the interrupt acceptance management means when an interrupt occurs is saved.
[0024]
Next, the interrupt task control processing means calls the interrupt processing task determined by the interrupt factor determination processing means. In the interrupt processing task, processing corresponding to the interrupt is performed. When a new interrupt factor is generated during this processing and the interrupt is permitted, information on the corresponding interrupt factor of the interrupt mask release control means Is set to the interrupt release state. Further, when the interrupt is permitted immediately, the corresponding interrupt mask of the interrupt mask of the interrupt controller is simultaneously set to the mask release state.
[0025]
When the processing of the interrupt processing task ends, the processing shifts to the interrupt task switch control means. At this time, if the interrupt processing task performs processing at an interrupt level different from the current interrupt level, the task switching information managed by the interrupt task switch management means corresponding to the interrupt level to be processed is set. Then, the processing shifts to the interrupt task switch control means.
[0026]
The interrupt task switch control means uses the task switching information managed by the interrupt task switch management means to determine which interrupt processing task is the interrupt processing task corresponding to the task switch instruction, and to call the interrupt processing task To decide. Then, the task switching information managed by the interrupt task switch management means is updated to call the determined interrupt processing task. If there is no task switching information managed by the interrupt task switch management means, control is transferred to the interrupt task control processing means.
[0027]
The interrupt task control processing means uses the multiple interrupt control means for both the interrupt acceptance management means saved before calling the interrupt processing task and the interrupt mask release control means set by the interrupt processing task. For the interrupt factor that is in the co-interrupt enabled state, the interrupt mask that is saved by the multiple interrupt control means and in which the corresponding bit in the interrupt mask state is set to enable interrupt is set in the interrupt mask of the interrupt controller. Further, for the interrupt factor changed to the interrupt enabled state at this time, the corresponding interrupt factor information of the interrupt mask release control means is reset. The task return processing means restores various information of the task that was being executed when the interrupt saved by the save processing means occurs, and resumes the processing of the suspended task.
[0028]
As described above, the interrupt acceptance management means and the interrupt mask release control means are prepared independently of the interrupt handler, and the multiple interrupt control means defines only the control method using the interrupt acceptance management means. When interrupt handler processing needs to be changed, such as when other interrupts can be accepted within an interrupt task, or when certain interrupts are prohibited thereafter, interrupt acceptance management means and interrupt mask release The control means can be changed, and an interrupt processing task can be created without being aware of the interrupt management status of the interrupt handler. In addition, it is possible to construct an interrupt process independent of the interrupt management state of the interrupt handler.
[0029]
Also, if you want to perform processing at an interrupt level different from the interrupt level of the interrupt processing task within the interrupt processing task, set the task switching information managed by the interrupt task switch management means corresponding to the interrupt level to be processed Thus, it is possible to construct an interrupt process that can change the interrupt level without designating a software interrupt that requires a process for saving / restoring the processing resource being processed.
[0030]
Also, the interrupt management device of the present invention provides an interrupt notification to an interrupt handler with an interrupt mask. Control The interrupt control means that performs the above and the interrupt handler are provided independently and prepared for each interrupt factor. And a set of interrupt masks An interrupt acceptance management means for holding an interrupt acceptance status, an interrupt mask release control means for controlling release of an interrupt mask for an interrupt factor in an interrupt processing task, and an interrupt task switch management means for managing task switching information from the interrupt processing task; The interrupt handler includes an evacuation processing means for evacuating information on a task being executed when an interrupt occurs, and an interrupt that determines an interrupt processing task to be processed according to the cause of the interrupt. Depending on the processing of the factor determination processing means, the interrupt acceptance management means and the interrupt mask release control means Remove the interrupt mask from the interrupt ready state. Multiple interrupt control means for performing interrupt mask update control, interrupt task control processing means for performing processing transition between the interrupt processing task and the interrupt handler determined by the interrupt factor determination processing means, and the interrupt task switch management The task switching information managed by the means is used to control the task switching instruction from the interrupt processing task. If there is a task switching instruction, the control is transferred to the interrupt processing task, and if there is no task switching instruction, the interrupt factor determination processing means is controlled. And an interrupt task switch control means for transferring the task, and a task return processing means for returning the information of the task being executed when the interrupt saved by the save processing means is generated and restarting the suspended task processing. take.
[0031]
According to this configuration, the interrupt factor determination processing unit responds to the mask state determined by the interrupt factor determination processing unit, that is, the interrupt factor with respect to the interrupt mask state set in the interrupt control unit when an interrupt occurs. The interrupt factor determination process is performed again for the same interrupt level each time control is transferred from the interrupt processing task to the interrupt handler using the interrupt mask state in which the mask is set to the interrupt disabled state.
[0032]
Therefore, in addition to the operation of the interrupt management device configured as described above, every time control is transferred from the interrupt processing task to the interrupt handler, the interrupt factor determination is performed again for the interrupt of the same interrupt level without performing the return processing of the processing resource being processed. It is possible to construct an interrupt process that can be processed.
[0033]
The interrupt management device of the present invention comprises factor determination calculation processing means for performing calculation processing when controlling the task switching instruction in the interrupt task switch control means in the interrupt management device, while the interrupt handler A configuration including factor determination calculation control means for controlling a calculation method when the determination calculation processing means performs calculation is employed.
[0034]
According to this configuration, as the task switching information from the interrupt processing task managed by the interrupt task switch management means, the same information as the interrupt factor that controls the notification is managed by the interrupt control means, and the interrupt factor determination processing means When determining the interrupt processing task to be processed according to the factor, the factor determination calculation processing means is performed using the result after the calculation according to the calculation method instructed by the factor determination calculation control means.
[0035]
Therefore, in addition to the operation of the interrupt management device configured as described above, when the control is transferred from the interrupt processing task to the interrupt handler, the generation of the interrupt factor managed by the interrupt control means is instructed by the task switch management means from the interrupt processing task. Therefore, it is possible to construct an interrupt process that does not require a save / restore process for the processing resource being processed.
[0036]
The interrupt management device according to the present invention includes an initialization task management means for storing a task call address for performing task initialization processing and an execution task for holding information on a task being executed in the interrupt management device. A control means, an initialization task instruction means for storing information of a task to interrupt processing, a task control means for determining a processing task to be processed and storing a call address for each processing task, and the initialization task management The interrupt handler uses the information from the interrupt task switch control means to determine whether to interrupt the task, and the task must be interrupted. If there is a suspended task determination means for storing information on the suspended task in the initialization task instruction means, Task suspension processing means for calling the dispatch processing means without restoring the task information once for the information of the task being executed at the time of the occurrence of the interrupt, and various information of the task being executed at the time of the interruption occurrence When returning a task that has been interrupted according to the processing of the task recovery processing means that performs recovery, the execution task control means, and the interrupted task determination means, it is determined whether or not initialization of the task is necessary, and initialization is performed. The system includes a task management control unit that calls the task suspension processing unit when returning to a task that requires processing, and that calls the task return processing unit when initialization processing is unnecessary.
[0037]
According to this configuration, the execution task control means stores information on the task being executed in the processing task and the interrupt processing task. In the interrupt handler, the information on the task being executed stored in the execution task control means is saved by the multiple interrupt control means when the interrupt occurs, and the interrupt processing task information determined by the interrupt factor determination processing means is saved. It is newly stored in the execution task control means.
[0038]
When the task is required to be initialized in the interrupt processing task, the task information to be initialized is stored in the interrupt task switch management means. When the processing of the interrupt processing task ends, the processing shifts to the interrupt task switch control means. At this time, if the interrupt task determination means determines whether the task initialization is necessary and the task initialization is instructed The information of the task to be initialized is stored in the initialization task instruction means. When the control is transferred to the interrupt task control processing means, the task management control means stores the execution task control means information saved before calling the interrupt processing task and the initialization task instruction means. Compare the information of the tasks to be initialized.
[0039]
When the same task is instructed, the task suspension processing means that simply calls the dispatch processing means of the task manager is called, not the task recovery processing means that restores various information in the task that was being executed when the interrupt occurred. As a result, the processing of the suspended task is resumed. If initialization processing is not required, task return processing means for saving various information in the task that was being executed when the interrupt occurred is called, and processing of the suspended task is resumed. Then, when switching the processing task to be called by the dispatch processing means of the task manager, it is compared with the processing task instructed by the initialization task instruction means, and the calling processing task requires initialization processing. Calls the task that performs the initialization process using the call address stored in the initialization task management means.
[0040]
Therefore, in addition to the operation of the interrupt management device configured as described above, the suspended task determination means for determining whether or not the initialization process of the suspended task is necessary when returning to the suspended task using the execution task control means and the interrupt task switch management means And task management control means for calling a task for performing initialization processing using a call address stored in the initialization task management means when returning to a task that requires initialization initialization processing. In the interrupt processing task, when a situation occurs in which the task processing is controlled to start from the initial state, the task that was being executed when the interrupt was saved by the save processing means (returned in the initialization process) Without returning various information of tasks that do not need to be performed), the task manager dispatch processing means again Task it is possible to start processing from the initialization process only when instructed.
[0041]
In the interrupt management device according to the present invention, in the interrupt management device, the interrupt task determination unit determines whether the task is interrupted using the information of the factor determination calculation processing unit.
[0042]
According to this configuration, the interrupt control unit controls the notification as the task suspension information from the interrupt processing task instructed by the interrupt task switch management unit is the task initialization determination performed by the interrupt task determination unit. The same information as the interrupt factor is also managed, and the factor determination calculation processing means performs the calculation using the result after the calculation according to the calculation method instructed by the factor determination calculation control means.
[0043]
Therefore, in addition to the operation of the interrupt management device having the above-described configuration, it is possible to construct an interrupt process capable of determining a suspended task in consideration of the generation of an interrupt factor managed by the interrupt control means.
[0044]
The base station apparatus of the present invention employs a configuration including the interrupt management apparatus.
[0045]
The mobile station apparatus of the present invention employs a configuration including the interrupt management apparatus.
[0046]
By providing the interrupt management device in each device, the processing efficiency in communication can be improved.
[0047]
The interrupt management method of the present invention controls interrupt notification to an interrupt handler with an interrupt mask, saves information on a task being executed when an interrupt is generated by this control, and interrupts to be processed according to the interrupt factor processing The task is determined and prepared for each interrupt source independently of the interrupt handler. And a set of interrupt masks Depending on interrupt mask release control information and interrupt acceptance enable state information to hold interrupt acceptance enable state and control interrupt permission in interrupt processing task Remove the interrupt mask from the interrupt ready state. Performs interrupt mask update control, transitions between the determined interrupt processing task and interrupt handler, manages task switching information from the interrupt processing task, and uses the task switching information to Controls task switching instructions. If there is a task switching instruction, control is transferred to the interrupt processing task. If there is no task switching instruction, the task information that was being executed when the saved interrupt occurred is restored and suspended. Resume processing I did .
[0048]
According to this method, the interrupt acceptance management information and interrupt mask release control information are prepared independently of the interrupt handler, and the interrupt mask update control defines only the control method using the interrupt acceptance management information. If it is necessary to change the interrupt handler processing, such as when other interrupts can be accepted within the interrupt task or when certain interrupts are prohibited thereafter, the interrupt acceptance management information Interrupt mask release control information can be changed, and interrupt processing tasks can be created without being aware of the interrupt management status of the interrupt handler. In addition, it is possible to construct an interrupt process independent of the interrupt management state of the interrupt handler.
[0049]
In addition, if you want to process at an interrupt level that is different from the interrupt level of the interrupt processing task in the interrupt processing task, you can set task switching information corresponding to the interrupt level to be processed, and save and restore the processing resources being processed The interrupt level can be changed without specifying a software interrupt that requires processing.
[0050]
The interrupt management method of the present invention controls task switching instructions from the interrupt processing task using task switching information in the above interrupt management method, and transfers control to the interrupt processing task when there is a task switching instruction. When there is no task switching instruction, the task is called to determine the interrupt processing task to be processed according to the interrupt factor.
[0051]
According to this method, in addition to the operation of the interrupt management method of the above method, every time control is transferred from the interrupt processing task to the interrupt handler, the processing resource return processing is performed for the interrupt of the same interrupt level. Therefore, it is possible to construct an interrupt process that can perform the interrupt factor determination process again.
[0052]
The interrupt management method of the present invention controls the calculation method when the factor determination calculation process performs calculation in the above interrupt management method, when calculating the interrupt processing task to be processed in the interrupt factor determination process. .
[0053]
According to this method, in addition to the operation of the above interrupt management method, when the control is transferred from the interrupt processing task to the interrupt handler, an interrupt factor managed by the interrupt control means is generated by an instruction from the interrupt processing task. Therefore, it is possible to construct an interrupt process that does not need to save / restore processing resources during processing.
[0054]
Also, the interrupt management method of the present invention is the above-described interrupt management method. In the interrupt management method, initialization task management information for storing a call address of a task for performing task initialization processing and a task being executed independently of the interrupt handler. Information is stored, the task switching information is used to determine whether to suspend the task, and if the task needs to be suspended, the information on the task to be suspended is stored in the initialization task instruction information, and the process to be processed A task manager having a dispatch process for determining a task and storing a task control information storing a call address for each processing task and switching a processing task to be called according to the initialization task management information, and a task being executed when an interrupt occurs The task suspension processing task that calls the dispatch processing without performing the return of the information in When returning to the suspended task according to the information of the task in progress and the initialization task instruction information, it is determined whether or not the initialization process of the suspended task is necessary, and the task is suspended when returning to the task that requires initialization processing. Call the processing task, and call the task return processing task if initialization processing is not required.
[0055]
According to this method, in addition to the operation of the interrupt management method described above, the interrupt task determination process for determining whether or not the interrupt task initialization process is necessary when returning to the interrupt task using the execution task control information and the task switching information When a task returns to a task that requires initialization processing, the task that performs initialization processing is called using the call address stored in the initialization task management information. When a situation occurs in which the processing is controlled so as to start from the initial state, it is no longer necessary to return in the initialization processing, without restoring various information in the task that was being executed when the saved interrupt occurred In addition, the initialization process is an initialization process only when the task is dispatched again by the task manager dispatch process. It is possible to start the process.
[0056]
The recording medium of the present invention is any one of the above Interrupt management method Same interrupt management method For running on a computer Take the structure in which the program is recorded.
[0057]
According to this configuration, the recording medium is Discount The interrupt management control can be realized by reading the program that executes the management management method.
[0058]
Operating system of the present invention Recording medium The above interrupt management method To realize Has processing function Take composition .
[0059]
According to this configuration, the interrupt management control can be realized by reading the program that executes the interrupt management control method.
[0060]
The signal processing processor according to the present invention comprises the above interrupt management method. To realize A processing function is provided.
[0061]
According to this configuration, the interrupt management control can be realized by reading the program that executes the interrupt management control method.
[0062]
DETAILED DESCRIPTION OF THE INVENTION
The gist of the present invention is to notify an interrupt handler of an interrupt generated for an interrupt factor by controlling an interrupt mask.
[0063]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0064]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 1 of the present invention. In this figure, the interrupt management device 100 includes an interrupt handler 101, an interrupt controller 102, an interrupt acceptance management unit 103, an interrupt mask release control unit 104, and an interrupt task switch management unit 105. .
[0065]
The interrupt handler 101 includes a save processing unit 106, an interrupt factor determination processing unit 107, an interrupt task control processing unit 108, a task return processing unit 109, a multiple interrupt control unit 110, and an interrupt task switch control unit 111. ing. The interrupt controller 102 includes an interrupt mask unit 112.
[0066]
In this figure, reference numerals 121-1 to 121-N are first to Nth interrupt factors. Reference numeral 123 denotes a processing task, which has first to Nth tasks 124-1 to 124-N. Reference numeral 127 denotes an interrupt processing task, which includes first to Nth interrupt processing tasks 128-1 to 128-N.
[0067]
The interrupt controller 102 controls interrupt notification to the interrupt handler 101 using the interrupt mask unit 112. In the interrupt handler 101, the save processing unit 106 saves various information of the task that was being executed when the interrupt occurred. The interrupt factor determination processing unit 107 determines an interrupt processing task to be processed based on the interrupt factor. The interrupt task control processing unit 108 performs processing transition between the determined interrupt processing task and the interrupt handler. The multiple interrupt control unit 110 performs interrupt mask update control using the interrupt acceptance management unit 103 and the interrupt mask release control unit 104. The interrupt task switch control unit 111 controls the task switching instruction from the interrupt processing task 127 using the task switching information managed by the interrupt task switch management unit 105. If there is a task switching instruction, the interrupt task switch control unit 111 returns to the interrupt processing task 127 again. Control is transferred, and if there is no task switching instruction, control is transferred to the interrupt task control processing unit 108.
[0068]
Of the interrupt receivable management unit 103, the interrupt mask release control unit 104, and the interrupt task switch management unit 105 provided independently of the interrupt handler 101, the interrupt receivable management unit 103 includes an interrupt reception prepared for each interrupt factor. The interrupt mask release control unit 104 controls the permission of the interrupt in the interrupt processing task. The interrupt task switch management unit 105 manages task switching information from the interrupt processing task 127.
[0069]
Next, the operation of the interrupt management apparatus 100 configured as described above will be described.
FIG. 2 is a diagram for explaining the operation of the interrupt controller 102. Here, in order to simplify the description, there are eight types of interrupt factors (IRQn: n = 0, 1 to 7) as interrupt factors, all are maskable interrupts, and each interrupt factor is generated. An interrupt request register (referred to as IR: Interrupt Request) and an interrupt mask register (referred to as IM: Interrupt Mask) for controlling interrupt prohibition (0) / permission (1) for each interrupt factor as the interrupt mask unit 112 And an interrupt request reset register (IRR: Interrupt Request Reset) that exists for each interrupt factor and is used to reset the interrupt request register IR.
[0070]
When the software sets (1) data in the IRR, the corresponding bit of the IR is reset (0). Each of the IR, IM, and IRR registers is implemented using the LSB8 bit of a 16-bit register, and an interrupt enable flag (0) / allow (1) interrupt enable flag (for all maskable interrupt factors) is controlled simultaneously. In this example, IE (Interrupt Enable) is provided.
[0071]
2 (a), (b), (c), and (d) show IR, IM, IRR, and IE, and bits for each interrupt factor IRQn (n = 0, 1,..., 7) IRn, IMn, IRRn (n = 0, 1,..., 7).
In addition, an example is shown in which “0” is set to a bit that does not correspond to an interrupt factor.
[0072]
FIG. 3 is a diagram showing a processing flow in the interrupt controller 102 when an interrupt factor occurs. As shown in this figure, when an interrupt factor is generated and detected (step 10), the corresponding bit of the interrupt request register is set (1) (step 12). After setting the corresponding bit in the interrupt request register, it is determined whether or not the interrupt permission flag is permitted (step 14). If not permitted, the process shifts to a standby state (step 16). Determines whether the corresponding bit of the interrupt mask register is enabled (1) (step 18). In this determination, if the corresponding bit of the interrupt mask register is not permitted, the process shifts to a standby state. If permitted, the interrupt permission flag is disabled (0) (step 20), and then the interrupt handler processes. A transition is made (step 22).
Furthermore, the interrupt factor determination process is also performed when the interrupt permission flag or the interrupt mask register is changed from the prohibited (0) state to the permitted (1) state (steps 24 and 26).
[0073]
Hereinafter, in order to simplify the description of the processing in the interrupt handler 101, when the processing transitions to the interrupt handler 101, four types of interrupt factors IRQ6, IRQ4, IRQ1, and IRQ0 are set (1) as interrupt factors. In this case, IM7, IM6, IM3, IM1, and IM0 are set to interrupt permission (1) as the setting state of the interrupt mask register IM, and all the interrupts are set as interrupt acceptance management means at that time. A case where the permitted interrupt mask is retained in the interrupt acceptance management unit 103 (this retained register is referred to as IMFGreg) will be described.
[0074]
Also, task switching information from the interrupt processing task managed by the interrupt task switch management unit 105 is realized by using the MSB 8 bit of the 16-bit register (the register holding this information is called TKSreg, task switching An example will be described in which “0” is set for bits not corresponding to information). The TKSreg is instructed (1) to the bit position corresponding to the task corresponding to the task switching instruction, and the release (0) is set when there is no instruction. The case where all the TKSreg states at this time are released will be described.
[0075]
Further, it is assumed that the interrupt mask release control unit 104 at this time has no interrupt factor to be masked, that is, all the bits of the interrupt mask release control unit 104 are set to clear (0).
[0076]
In addition, four interrupt levels are set as the interrupt level of the interrupt factor.
Level 0 interrupt factor: IRQ2, IRQ3
Level 1 interrupt factor: IRQ0, IRQ1
Level 2 interrupt factors: IRQ7, IRQ6, IRQ4
Level 3 interrupt factor: IRQ5
And level 0> level 1> level 2> level 3.
[0077]
The interrupt acceptance management unit 103 holds an interrupt mask register setting state (referred to as IMFG) in which only an interrupt factor having a higher level than the interrupt factor level is permitted (1) for each interrupt. The
[0078]
FIG. 4 shows the setting state of the interrupt mask register to be set for the interrupt level, and IMFGn corresponds to IRQn (n = 0, 1,..., 7), respectively. For example, in IMFG6 for interrupt factor IRQ6, the corresponding bits of IRQ0, IRQ1, IRQ2, and IRQ3, which are higher in level than IRQ6, are set to enable (1). Further, since IMFG1 corresponding to the interrupt factor IRQ2 does not have an interrupt factor having a higher level than IRQ2, all bits are set to disabled (0).
[0079]
First, when the process transitions to the interrupt handler 101, various information of the processing task being executed at that time (this processing task is referred to as the interrupt task 125) is saved by the save processing unit 106.
[0080]
Next, with respect to the interrupt factor notified from the interrupt controller 102 by the interrupt factor determination processing unit 107, it is determined which interrupt factor is to be processed using the interrupt acceptance management unit 103, and the interrupt processing task to be called is determined. decide.
[0081]
FIG. 5 is an explanatory diagram of the interrupt factor determination processing procedure.
Since four types of interrupt factors IRQ6, IRQ4, IRQ1, and IRQ0 are set (1) as interrupt factors, each corresponding bit of IR6, IR4, IR1, and IR0 is 1 in the interrupt request register IR (S1 ).
As the setting state of the interrupt mask register IM, IM7, IM6, IM3, IM1, and IM0 are set to interrupt permission (1), so the interrupt mask register IM is set to each bit 1 of IM7, IM6, IM3, IM1, and IM0. (S2).
[0082]
Next, an AND operation for each corresponding bit of S1 and S2 is performed (S3).
In the state of S3, evaluation is performed in order from the MSB side, and an interrupt factor corresponding to a bit having a value of 1 is selected. In this case, since the bit at the position with respect to IRQ6 is first 1, IRQ6 is selected as an interrupt factor.
[0083]
Next, with respect to the setting state IMFG in the interrupt mask register held in the interrupt acceptance management unit 103, the setting state IMFG6 in the interrupt mask register corresponding to the selected interrupt factor IRQ6 (that is, IMFG6 in FIG. 5). (S4).
[0084]
Next, an AND operation for each corresponding bit of S3 and S4 is performed (S5).
Next, the same evaluation as that performed for the state of S3 is performed, and IRQ1 is selected as an interrupt factor. Next, processing similar to S4 is performed to obtain IMFG1 (that is, the value of IMFG1 in FIG. 5) from the interrupt acceptance management unit 103 (S6).
[0085]
Next, if the same processing as S5 is performed, all the bits become 0 (S7). Therefore, if the same evaluation as that performed for the state of S3 is performed, there is no corresponding interrupt factor. At this time, the interrupt factor evaluated immediately before, that is, IRQ1 is selected as the interrupt factor, the interrupt processing task for IRQ1 is determined as the interrupt processing task to be called, and the processing transitions to the interrupt task control processing unit 108.
[0086]
Since IRQ1 is selected as the interrupt factor at this time, the bit corresponding to IRQ1 of the interrupt request reset register IRR, that is, by setting (1) IRR1, the interrupt factor of IRQ1 set in the interrupt request register IR is reset. (0) is performed.
Here, the interrupt processing task for IRQ1 is referred to as an R-th interrupt processing task 129, which will be described below.
[0087]
FIG. 6 is an explanatory diagram of a processing procedure in the multiple interrupt control unit 110.
The multiple interrupt control unit 110 extracts the interrupt mask IMFG1 for the determined R-th interrupt processing task 129 from the interrupt acceptance management unit 103 that holds the interrupt acceptance state prepared for each interrupt factor, and Set in the interrupt mask unit 112.
[0088]
At this time, when an interrupt occurs, an interrupt mask is already set in the interrupt mask unit 112 of the interrupt controller 102, and no change is made to the interrupt mask for the interrupt factor for which the interrupt is disabled. That is, by performing an AND operation for each corresponding bit of IMFG1 in S6 and IM in S2, an interrupt mask state to be set in the interrupt mask 34 is determined, and this mask state is set in the interrupt mask 34 (S8).
[0089]
Further, with respect to the interrupt mask state set in the interrupt controller 102 when an interrupt occurs, the interrupt mask state in which the mask for the interrupt factor IRQ1 determined by the interrupt factor determination processing unit 107 is disabled is saved. That is, the state (S10) obtained by performing an EOR operation on the S2 IM with only the corresponding bit of the interrupt factor IRQ1 set to 1 (S9) is saved (the saved register is called IM_SHLTreg). ).
[0090]
Further, the state of the interrupt acceptance management means when an interrupt occurs is saved. That is, the contents (S11) of IMFGreg in a state where all interrupts are permitted are saved (a register to be saved is called IM_SHLTreg).
[0091]
Next, the interrupt task control processing unit 108 calls the R-th interrupt processing task 129 that is the corresponding interrupt processing task determined by the interrupt factor determination processing processing unit 12. In the R-th interrupt processing task 129, processing corresponding to the interrupt is performed. When interrupt is permitted for a new interrupt factor during this processing, the interrupt mask release control unit 104 sets the corresponding interrupt factor. Set the information to interrupt release state. When the interrupt is permitted immediately, the corresponding interrupt mask of the interrupt mask unit 112 of the interrupt controller 102 is simultaneously set to the mask release state.
[0092]
That is, in the process of the R-th interrupt processing task 129, considering that the interrupt factor IRQ2 can be newly accepted, all the bits of the interrupt mask release control unit 104 are set to clear (0). Therefore, when the interrupt factor IRQ2 can be accepted, the corresponding bit of the interrupt mask release control unit 104 is set (1).
[0093]
FIG. 7A shows the state of the interrupt mask release control unit 104 at this time (S12).
[0094]
Further, since IRQ2 is an interrupt factor at a higher level than the interrupt factor IRQ1 to be processed by the R-th interrupt processing task 129, the interrupt is permitted immediately, and the interrupt mask unit 112 of the interrupt controller 102 at the present time The interrupt mask of the corresponding bit of IRQ2 is canceled (1) with respect to the set state S8. FIG. 7B shows the state of the interrupt mask unit 112 at this time (S13).
[0095]
A case will be described in which the interrupt level is changed and the interrupt processing task 127 is processed in the processing of the interrupt processing task R129.
In this case, an instruction (1) is set in the corresponding bit of the task switching information TKSreg managed by the interrupt task switch management unit 105 corresponding to the interrupt processing task 127 whose interrupt level is to be changed, and the interrupt task switch control unit 111 is set. Transfer control.
[0096]
When any bit of TKSreg is 1, the interrupt task switch control unit 111 evaluates TKSreg in order from the MSB and selects the interrupt processing task 127 corresponding to the task switching instruction that is first set to 1 (here, The following description will proceed assuming that the Nth interrupt processing task 130 has been selected, and the bit of the corresponding TKSreg is set to release (0).
[0097]
Also, the interrupt acceptance management unit 103 holds an IMFG for each interrupt task switch instruction.
Then, using the information of IMFG, IM_SHLTreg, and IM corresponding to the selected interrupt processing task
((IM_SHLTreg and IMFG) eor IM) eor IM_SHLTreg
The bit information calculated by the above operation is newly set in IM1.
When the processing of the interrupt processing task N130 is completed, the processing shifts to the interrupt task switch control unit 111 again.
[0098]
Then, the above process is repeated until all bits of TKSreg managed by the interrupt task switch management unit 105 become 0. When all bits of TKSreg become 0, control is transferred to the interrupt task control unit 108.
[0099]
At this time, the state of the interrupt acceptance management unit 103 saved in IMFG_SHLTreg before calling the R-th interrupt processing task 129 by the multiple interrupt control unit 110 and the R-th interrupt processing task 129 are set. The interrupt mask state saved to IM_SIM_SHLTreg by the multiple interrupt control unit 110 for the interrupt factor in which both interrupts are enabled, that is, IRQ2 with respect to the state (S12) of the interrupt mask release control unit 104 that has been made The corresponding bit of (S10) set to enable interrupt is set in the interrupt mask unit 112 of the interrupt controller 102. FIG. 7C shows the state of the mask 34 at this time (S14).
[0100]
Furthermore, the interrupt factor information corresponding to the interrupt mask cancellation control unit 104 is reset for the interrupt factor IRQ2 changed to the interrupt enabled state at this time. FIG. 7D shows the state of the interrupt mask release control unit 104 at this time (S15). Then, the task return processing unit 109 restores various information of the task that was being executed when the interrupt saved by the save processing unit 106 occurred, and resumes the processing of the suspended task 125.
[0101]
As described above, according to the interrupt management device 100 of the first embodiment, the interrupt receivable management unit 103 and the interrupt mask release control unit 104 are prepared independently of the interrupt handler 101, and the multiple interrupt control unit 110 Since only the control method using the receivable management means 51 is defined, the processing of the interrupt handler 101 such as when other interrupts can be accepted within the interrupt task or when certain interrupts are prohibited thereafter. When it is necessary to change the interrupt handler management unit 103 and the interrupt mask release control unit 104, the interrupt handler task 127 can be created without being aware of the interrupt management state of the interrupt handler 101. Construction of interrupt processing that does not depend on the interrupt management state of the interrupt handler 101 Possible to become.
[0102]
Also, in the interrupt processing task 127, when it is desired to perform processing at an interrupt level different from the interrupt level of the interrupt processing task, the task switching information managed by the interrupt task switch management unit 105 corresponding to the interrupt level to be processed is displayed. It is possible to construct an interrupt process that can change the interrupt level without specifying a software interrupt that needs to save / restore the processing resource during processing.
[0103]
In the first embodiment, the interrupt task switching instruction is described as the case where the interrupt level is changed. However, the task switching is not performed when the same processing is performed in the interrupt processing task 127 instead of changing the interrupt level. It can be realized similarly.
[0104]
(Embodiment 2)
FIG. 8 is a block diagram showing the configuration of the interrupt management apparatus according to Embodiment 2 of the present invention. In the second embodiment shown in this figure, parts corresponding to those in the first embodiment shown in FIG.
[0105]
The interrupt management device 700 according to the second embodiment shown in this figure includes an interrupt task switch control unit 701 in the interrupt handler 101 in addition to the components of the interrupt management device 100 according to the first embodiment. The interrupt task switch control unit 701 uses the task switching information managed by the interrupt task switch management unit 105 to control a task switching instruction from the interrupt processing task 127. Control is transferred again, and if there is no task switching instruction, processing similar to that of the interrupt task switch control unit 111 of the first embodiment is performed except that control is transferred to the interrupt factor determination processing unit 107.
[0106]
The interrupt factor determination processing unit 107 acquires IR information at the time of the interrupt immediately before being saved in the save processing unit 106, and was set in the interrupt controller 102 when an interrupt generated by the multiple interrupt control unit 110 occurred. The interrupt processing task 127 to the interrupt handler 101 use the interrupt mask state (S8) in which the mask for the interrupt factor determined by the interrupt factor determination processing unit 107 is set to the interrupt disabled state with respect to the interrupt mask state (S2). Each time control is transferred to, the same interrupt factor determination processing as in FIG. 5 is performed again for the same interrupt level.
[0107]
As described above, according to the interrupt management device 700 of the second embodiment, every time control is transferred from the interrupt processing task 127 to the interrupt handler 101, the processing resource restoration process is performed for an interrupt of the same interrupt level. It is possible to construct an interrupt process that can perform the interrupt factor determination process again without performing it.
[0108]
(Embodiment 3)
FIG. 9 is a block diagram showing the configuration of the interrupt management apparatus according to Embodiment 3 of the present invention. In the third embodiment shown in this figure, parts corresponding to those in the second embodiment shown in FIG.
[0109]
In addition to the components of the interrupt management device 700 of the second embodiment, the interrupt management device 800 of the third embodiment shown in this figure includes a factor determination calculation processing unit 801 and a factor determination calculation control unit 802 in the interrupt handler 101. And.
[0110]
Here, as an example, an OR operation is designated as the calculation method of the factor determination calculation control unit 802 that controls the calculation method when the factor determination calculation processing unit 801 performs calculation, and the interrupt factor determination processing unit 107 should process the calculation. A case where the factor determination calculation processing unit 801 performs OR calculation processing when determining an interrupt processing task will be described.
[0111]
Further, a case is considered in which, in the task switching information TKSreg from the interrupt processing task managed by the interrupt task switch management unit 105, the same information as the interrupt factor that controls the notification is managed using LSB8bit.
[0112]
In this case, it can be set as information for instructing an interrupt at the same position as that in FIG.
The factor determination calculation processing unit 801 performs an OR operation on the bit position corresponding to the instructed interrupt factor with the IR information saved by the save processing unit 106 immediately before, and stores the result in the save processing unit 106. Control is returned to the task switch control unit 111.
[0113]
As described above, according to the interrupt management device 800 of the third embodiment, when control is transferred from the interrupt processing task 127 to the interrupt handler 101, the generation of the interrupt factor managed by the interrupt controller 102 is generated from the task from the interrupt processing task 127. This can be performed by an instruction from the switch management unit 105, and it is possible to construct an interrupt process that does not require a save / restore process of the processing resource being processed.
[0114]
(Embodiment 4)
FIG. 10 is a block diagram showing the configuration of the interrupt management apparatus according to Embodiment 4 of the present invention. In the fourth embodiment shown in this figure, portions corresponding to those in the first embodiment shown in FIG.
[0115]
In addition to the components of the interrupt management apparatus 100 of the first embodiment, the interrupt management apparatus 900 of the fourth embodiment shown in this figure includes an execution task control unit 901, an initialization task instruction unit 902, and an initialization task management. 903, a task management control unit 904, a task suspension processing unit 905, a suspended task determination unit 906, and a task manager 909 provided with a dispatch processing unit 908 having a task control unit 907. The task management control unit 904, the task suspension processing unit 905, and the suspended task determination unit 906 are provided in the interrupt handler 101.
[0116]
The initialization task management unit 903 stores a call address of a task that performs task initialization processing independently of the interrupt handler 101. The execution task control unit 901 holds information on a task being executed. The initialization task instruction unit 902 instructs (holds) setting of a task that requires initialization processing. A dispatch processing unit 908 of the task manager 909 determines a processing task to be processed, stores a task control unit 901 that stores a calling address for each processing task, and stores a calling address of a task that performs task initialization processing. The initialization task management unit 903 is used to perform processing task switching processing to be called.
[0117]
When the task management control unit 904 uses the execution task control unit 901 and the initialization task instruction unit 902 to return to the suspended task, the task management control unit 904 determines whether or not the suspended task initialization process is necessary. When returning, the task that performs the initialization process stored in the initialization task management unit 903 is called. The task interruption processing unit 905 calls the dispatch processing unit 908 without restoring various information in the task that was being executed when the interrupt saved by the save processing unit 106 occurred. The suspended task determination unit 906 determines a task to be suspended from the suspended task information managed by the interrupt task switch management unit 105, and sets the information in the initialization task instruction unit 902.
[0118]
The operation of the interrupt management apparatus 900 of the fourth embodiment configured as described above will be described. However, in order to simplify the description of the processing in the interrupt handler 101, description will be made using the description in the first embodiment.
[0119]
(A) of FIG. 11 shows the state of the information of the task being executed stored in the execution task control unit 901. Each task of the processing task 4 and the interrupt processing task 2 is associated with each bit. This shows the case of management. On the other hand, FIG. 11B shows a case where a task that requires initialization processing is set in the initialization task instruction unit 902 corresponding to each bit in the same manner as the execution task control unit 901.
[0120]
The execution task control unit 901 stores information on a task being executed (called TSKINF) among the processing task and the interrupt processing task. First, when the process transitions to the interrupt handler 101, 1 is set to the corresponding bit of the processing task (interrupt task 125) being executed at that time (T1).
[0121]
Next, the multiple interrupt control unit 110 saves the information of the task being executed that was stored in the execution task control unit 901 when the interrupt occurred, that is, the state of T1 (the save register is referred to as TSKINF_SHLTreg), and interrupt factor determination processing Information (T2) of the R-th interrupt processing task 129 determined by the unit 107 is newly stored in the execution task control unit 901.
[0122]
When the R-th interrupt processing task 129 needs to be initialized, the task information to be initialized is stored in the interrupt task switch management unit 105. When the processing of the R-th interrupt processing task 129 is completed, when the control is transferred again to the interrupt task switch control unit 111, the interrupt task determination unit 906 performs initialization tasks stored in the interrupt task switch management unit 105 From this information, the task that needs to be initialized is interpreted, and the initialization task instruction unit 902 stores the information of the task to be initialized.
[0123]
Consider a case where the suspended task 125 is set as a task that requires initialization. In this case, 1 is set to the corresponding bit of the suspended task 125 in the initialization task instruction unit 902 (T3). Thereafter, the processing shifts to the interrupt task control processing unit 108. At this time, the information (T2) of the execution task control unit 901 saved by the multiple interrupt control unit 110 in TSKINF_SHLTreg before calling the interrupt processing task. The task management control unit 904 performs comparison using the information (T3) of the task to be initialized stored in the initialization task instruction unit 902.
[0124]
The task management control unit 904 calls the task suspension processing unit 905 when the compared tasks indicate the same task, and calls the task return processing unit 109 when the processing is unnecessary. For example, since the information of the execution task control unit 901 saved in TSKINF_SHLTreg is information on the task that was being executed when the interrupt occurred, only the corresponding 1 bit is always set to 1, so the task management control unit If the AND operation of T2 and T3 is performed at 904 and becomes a non-zero value, it can be determined that the compared task indicates the same task, and in this case, the task is the same.
[0125]
As described above, when returning to the suspended task, it is determined whether or not the initialization process of the suspended task is necessary, and when returning to the task that needs the initialization process, the interruption processing unit 106 is executing when an interrupt is saved. The task suspension processing unit 905 is called instead of the task return processing unit 109 that saves various information of the task.
[0126]
When the initialization process is not required, the task return processing unit 109 that restores various information in the task that was being executed when the interrupt saved by the save processing unit 106 is called is called, and the suspended task processing is resumed. The
[0127]
The comparison with the processing task instructed by the initialization task instruction unit 902 when switching the processing task to be called by the dispatch processing unit 908 of the task manager 909 is the same as the comparison processing in the task management control unit 904. If the process task to be called is a task that requires an initialization process, the task that performs the initialization process is called using the call address stored in the initialization task management unit 903.
[0128]
As described above, according to the interrupt management apparatus 900 of the fourth embodiment, the initialization task management unit 903 that stores the call address of the task that performs the task initialization process, and the execution task that holds the information of the task being executed The interrupt task determination unit 906 interprets the information of the task that requires the initialization processing set in the control unit 901 and the interrupt task switch management unit 105, sets the information in the initialization task instruction unit 902, and executes the task control unit 901. When the task is returned to the suspended task using the initialization task instruction unit 902, it is determined whether or not the initialization process of the suspended task is necessary. The task management control unit 904 calls a task that performs initialization processing using the call address stored in 903.
[0129]
For this reason, when the interrupt processing task 127 is controlled to start the task processing from the initial state, the interrupt processing task 127 does not need to initialize the task stack area, the task control means, and the like.
[0130]
Therefore, the interrupt processing task 127 does not need to be aware of the processing contents of the task to be initialized, and the processing procedure for performing initialization in the interrupt processing task 127 is independent of the interrupt processing task 127 and the task that requires initialization. It is possible to construct a mechanism that can be controlled easily.
[0131]
In addition, when initialization of a task occurs, various information on the task that was being executed is restored when an interrupt saved by the save processing unit 106 that no longer needs to be restored in the initialization process. Without performing this process, the initialization process can be started from the initialization process only when the dispatch processing unit 908 of the task manager 909 instructs the task again.
[0132]
(Embodiment 5)
FIG. 12 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 5 of the present invention. In the fifth embodiment shown in this figure, portions corresponding to those in the fourth embodiment shown in FIG. 10 are denoted by the same reference numerals, and the interrupt task switch control unit 111 is replaced with the interrupt task switch control unit 701 shown in FIG. It becomes the composition which became.
[0133]
Therefore, the interrupt management apparatus 1000 of the fourth embodiment shown in this figure exhibits the effects described in the second and fourth embodiments, and detailed description thereof is omitted.
[0134]
(Embodiment 6)
FIG. 13 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 6 of the present invention. In the sixth embodiment shown in this figure, portions corresponding to those in the third embodiment shown in FIG.
[0135]
In addition to the components of the interrupt device 800 of the third embodiment, the interrupt management device 1100 of the sixth embodiment shown in this figure includes an execution task control unit 901 that is a component of the fourth embodiment, and an initial A task manager provided with a dispatch processing unit 908 having a generalized task instruction unit 902, an initialization task management unit 903, a task management control unit 904, a task suspension processing unit 905, and a task control unit 907 in the interrupt handler 101 909, and includes an interrupted task determination unit 1101 that determines an interrupted task using the calculation result of the factor determination calculation processing unit 801.
[0136]
Then, with respect to the third embodiment, the factor determination calculation processing unit 801 performs an OR operation with the IR information saved immediately before by the save processing unit 106 at the bit position corresponding to the instructed interrupt factor, and save processing When the process is stored in the unit 106 and the control is returned to the task switch control unit 111, the interrupt task determination unit 1101 performs the same process as the interrupt task determination unit 906 in the fourth embodiment.
[0137]
Therefore, the interrupt management device 1100 of the sixth embodiment exhibits the effects described in the third and fourth embodiments, and a detailed description thereof is omitted.
[0138]
It should be noted that the present invention can be applied to all interrupt management devices that can read the data of the recording medium by programming the functions of the interrupt management device according to each of the embodiments described above and writing the recording medium. Is possible. Examples of the recording medium include a semiconductor recording medium, a magnetic recording medium, an optical recording medium, and an optical / magnetic recording medium.
[0139]
It is also possible to incorporate the functions of the interrupt management device according to each of the above embodiments as an interrupt management mechanism in a signal processing processor (DSP), and an application that uses interrupt processing independently of interrupt processing in the DSP. It is effective when realizing
[0140]
Further, the function of the interrupt management device according to each of the above embodiments can be incorporated into interrupt processing in an OS such as a computer processing real-time operation system and a multitask operation system, and is realized on a personal computer. The construction of an application system is effective when an application using interrupt processing is realized independently of interrupt processing within the OS. In addition, in the case of having multiple interrupts, the interrupt level can be constructed in a form independent of the interrupt mechanism in the OS, and this is particularly effective.
[0141]
Further, by providing the interrupt management device according to each of the above embodiments in a terminal device or base station device in mobile communication, it is possible to improve processing efficiency in communication.
[0142]
【The invention's effect】
As described above, according to the present invention, in an interrupt processing task, when it is desired to perform processing at an interrupt level different from the interrupt level of the interrupt processing task, software that requires saving / restoring processing of the processing resource being processed The interrupt level can be changed without specifying an interrupt.
[0143]
Further, every time control is transferred from the interrupt processing task to the interrupt handler, the interrupt factor determination process can be performed again for the interrupt of the same interrupt level without performing the return process of the processing resource being processed.
[0144]
In addition, when control is transferred from the interrupt processing task to the interrupt handler, the interrupt processing managed by the interrupt controller can be generated from the interrupt processing task, and interrupt processing that does not require saving / restoring processing resources during processing Is possible.
[0145]
In addition, when it is necessary to change interrupt handler processing, such as when other interrupts can be accepted within an interrupt task, or when certain interrupts are prohibited, interrupts by interrupt handlers or interrupt processing tasks The processing contents can be easily changed.
[0146]
Further, in the interrupt management method using the OS, even when interrupt handlers in the OS collectively perform interrupt disable / permit processing for all interrupt causes, the user can interrupt interrupt handlers in the OS. It is possible to create an interrupt processing task without being conscious of the interrupt management state.
[0147]
In addition, when the interrupt processing that does not depend on the interrupt management state of the interrupt handler in the OS and the interrupt processing task is controlled to start the task processing from the initial state, the task stack area, It is not necessary for the interrupt processing task to initialize task control means and the like.
[0148]
Therefore, it is not necessary for the interrupt processing task to be aware of the processing contents of the task to be initialized, and within the interrupt processing task, the processing procedure for initialization can be controlled independently of the interrupt processing task and the task that requires initialization. Can be constructed.
[0149]
In addition, when task initialization occurs, it is no longer necessary to restore various information on the task that was being executed when the interrupt was saved by the save processing unit that no longer needs to be restored in the initialization process. .
[0150]
Furthermore, the initialization process can be started from the initialization process only when the task is dispatched again by the task manager dispatch processing unit, and task management including initialization in the task manager is addressed. Since only the management and control methods are defined, it is possible to perform switching control of processing tasks independent of the call address of each processing task.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a diagram for explaining the operation of the interrupt controller of the interrupt management device according to the first embodiment;
FIG. 3 is a flowchart for explaining the operation of the interrupt controller of the interrupt management device according to the first embodiment;
FIG. 4 is a diagram showing a setting state of an interrupt mask register for each interrupt factor held in the interrupt acceptance management unit of the interrupt management device according to the first embodiment;
FIG. 5 is a diagram for explaining an interrupt factor determination processing procedure of the interrupt management device according to the first embodiment;
FIG. 6 is a diagram for explaining a processing procedure in a multiple interrupt control unit of the interrupt management device according to the first embodiment;
FIG. 7 is a diagram for explaining a processing procedure in an interrupt processing task of the interrupt management device according to the first embodiment;
FIG. 8 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 2 of the present invention.
FIG. 9 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 3 of the present invention.
FIG. 10 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 4 of the present invention.
FIG. 11 is a diagram showing a state of information on a task being executed that is stored in the execution task control unit of the interrupt management device according to the fourth embodiment;
FIG. 12 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 5 of the present invention.
FIG. 13 is a block diagram showing a configuration of an interrupt management apparatus according to Embodiment 6 of the present invention.
[Explanation of symbols]
100, 700, 800, 900, 1000, 1100 Interrupt management device
101 Interrupt handler
102 Interrupt controller
103 Interrupt acceptance manager
104 Interrupt mask release controller
105 Interrupt task switch manager
106 Evacuation processing unit
107 Interrupt factor determination processing section
108 Interrupt task control processing unit
109 Task return processing section
110 Multiple interrupt controller
111 Interrupt task switch controller
112 Interrupt mask section
121-1 First interrupt factor
121-N Nth interrupt factor
123 Processing Task
124-1 First Task
124-2 Suspended task
124-N Nth task
127 Interrupt processing task
128-1 First interrupt processing task
128-R Rth interrupt processing task
128-N Nth interrupt processing task
701 Interrupt task switch controller
801 Factor determination calculation processing unit
802 Factor determination calculation control unit
901 Execution task control unit
902 Initialization task instruction section
903 Initialization task management section
904 Task management control unit
905 Task interruption processing part
906 Interrupted task determination unit
907 Task control unit
908 Dispatch processing part
909 Task Manager

Claims (14)

An interrupt control means for controlling the interrupt notification to the interrupt handler in the interrupt mask, the interrupt handler provided independently from, holds the interrupt acceptance state consisting of a set of prepared for each interrupt factor Rutotomoni Interrupt Mask interrupt An interrupt management device comprising: an acceptable management means; an interrupt mask release control means for controlling release of an interrupt mask for an interrupt factor in an interrupt processing task; and an interrupt task switch management means for managing task switching information from the interrupt processing task. There,
The interrupt handler includes a save processing unit that saves information on a task that is being executed when an interrupt occurs, an interrupt factor determination processing unit that determines an interrupt processing task to be processed according to an interrupt factor, and the interrupt acceptance management And an interrupt processing task determined by the interrupt factor determination processing means, and a multiple interrupt control means for taking out an interrupt mask from the interrupt ready state and performing an update control of the interrupt mask according to the processing of the interrupt mask release control means. An interrupt task control processing unit that performs a process transition between the interrupt handler and the task switching information managed by the interrupt task switch management unit, and controls a task switching instruction from the interrupt processing task. If there is, transfer control to the interrupt processing task. If there is no task switching instruction, interrupt task switch control means for transferring control to the interrupt task control processing means, and processing of a task that has been interrupted by returning information on the task being executed when the interrupt saved by the save processing means occurs An interrupt management device comprising: task return processing means for resuming processing. An interrupt control means for controlling the interrupt notification to the interrupt handler in the interrupt mask, the interrupt handler provided independently from, holds the interrupt acceptance state consisting of a set of prepared for each interrupt factor Rutotomoni Interrupt Mask interrupt An interrupt management device comprising: an acceptable management means; an interrupt mask release control means for controlling release of an interrupt mask for an interrupt factor in an interrupt processing task; and an interrupt task switch management means for managing task switching information from the interrupt processing task. There,
The interrupt handler includes a save processing unit that saves information on a task that is being executed when an interrupt occurs, an interrupt factor determination processing unit that determines an interrupt processing task to be processed according to an interrupt factor, and the interrupt acceptance management And an interrupt processing task determined by the interrupt factor determination processing means, and a multiple interrupt control means for taking out an interrupt mask from the interrupt ready state and performing an update control of the interrupt mask according to the processing of the interrupt mask release control means. An interrupt task control processing unit that performs a process transition between the interrupt handler and the task switching information managed by the interrupt task switch management unit, and controls a task switching instruction from the interrupt processing task. If there is, transfer control to the interrupt processing task. If there is no task switching instruction, interrupt task switch control means for transferring control to the interrupt factor determination processing means, and processing of a task that has been interrupted by returning information on the task being executed when the interrupt saved by the save processing means occurs An interrupt management device comprising: task return processing means for resuming processing.   The interrupt handler includes factor determination calculation processing means for performing calculation processing when controlling a task switching instruction in the interrupt task switch control means, while the interrupt handler is a factor for controlling a calculation method when the factor determination calculation processing means performs calculation 3. The interrupt management apparatus according to claim 2, further comprising a determination calculation control unit.   Initialization task management means for storing the task call address for performing task initialization processing, execution task control means for storing information on the task being executed, and initialization for storing information on the task for which processing is interrupted Task instruction means, task control means for determining a processing task to be processed and storing a call address for each processing task, and dispatch processing means for switching a processing task to be called according to the processing of the initialization task management means On the other hand, the interrupt handler performs task interruption determination using information from the interrupt task switch control means, and stores information on the task to be interrupted in the initialization task instruction means if task interruption is necessary. The suspended task determination means to perform and the task information that was being executed when the interrupt occurred Task suspension processing means for calling the dispatch processing means without returning information, task return processing means for restoring various information of the task that was being executed when the interrupt occurred, the execution task control means, and the suspended task When returning a task that has been suspended according to the processing of the determination means, it is determined whether or not the initialization processing of the task is necessary, and when returning to a task that requires initialization processing, the task suspension processing means is called, 4. The interrupt management device according to claim 1, further comprising task management control means for calling up the task return processing means when initialization processing is unnecessary.   5. The interrupt management apparatus according to claim 4, wherein the interrupt task determination unit performs task interrupt determination using information of the factor determination calculation processing unit.   A base station apparatus comprising the interrupt management apparatus according to any one of claims 1 to 5.   A mobile station apparatus comprising the interrupt management apparatus according to any one of claims 1 to 5. Controls interrupt notification to the interrupt handler with the interrupt mask, saves information on the task being executed when an interrupt is generated by this control, determines the interrupt processing task to be processed according to the interrupt factor, and is independent of the interrupt handler , is prepared for each interrupt factor holding the interrupt acceptance state consisting of a set of Rutotomoni interrupt mask in accordance with the interrupt unmasking control information and interrupt information of the reception state to control the interrupt enabling the interrupt processing task interrupt Take out the mask from the interrupt ready state , perform interrupt mask update control, transition the processing between the determined interrupt processing task and interrupt handler, manage task switching information from the interrupt processing task, and Interrupt handling using switching information Controls the task switching instruction from the task. If there is a task switching instruction, the control is transferred to the interrupt processing task. If there is no task switching instruction, the task information being executed is restored and interrupted when the saved interrupt occurs. An interrupt management method characterized by resuming processing of a task that has been interrupted.   Task switching information is used to control the task switching instruction from the interrupt processing task. If there is a task switching instruction, control is transferred to the interrupt processing task, and if there is no task switching instruction, depending on the cause of the interrupt, 9. The interrupt management method according to claim 8, wherein a task for determining an interrupt processing task to be processed is called.   10. The arithmetic processing when the interrupt processing task to be processed in the interrupt factor determination processing is determined, and the calculation method when the factor determination calculation processing performs the calculation is controlled. Interrupt management method.   Independent of the interrupt handler, it stores initialization task management information that stores the task call address for task initialization processing, and information on the task that is being executed. If the task is to be interrupted, the task information to be interrupted is stored in the initialization task instruction information, the processing task to be processed is determined, and the call address for each processing task is stored A task manager having a dispatch process for switching a processing task to be called according to control information and the initialization task management information, and a task interruption process for calling the dispatch process without returning the information in the task being executed when an interrupt occurs. Depending on the task and the information of the task being executed and the initialization task instruction information, When returning, it is judged whether or not the initialization process of the interrupted task is necessary, and when returning to the task that needs the initialization process, the task interruption process task is called, and when the initialization process is unnecessary, the task return process task is 11. The interrupt management method according to claim 8, wherein the interrupt management method is called. 12. A recording medium on which a program for causing a computer to execute the interrupt management method according to claim 8 is recorded. Recording medium recording the operating system, characterized by comprising a processing function for causing actual revealed interrupt management method according to any one of claims 11 to claim 8. A signal processing processor comprising a processing function for realizing the interrupt management method according to claim 8.

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