JP2001229038A - Multi-operating computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-operating computer system for easily assigning a necessary operating system to a device even when multiple devices share the same interruption number in operating multiple operating systems by a single processor. SOLUTION: Which device of multiple devices 106-108 generates interruption due to a common interruption number is decided, and an operating system allocated from multiple operating systems 111 and 112 to the device which generates interruption is activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention switches a plurality of operating systems to operate one processor,
The present invention relates to a multi-operating computer system in which a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt line.

[0002]

2. Description of the Related Art In general, a computer system runs one operating system, which manages computer resources such as a processor, a memory, and a secondary storage device of a computer, and sets a resource schedule so that the computer can operate efficiently. Is going. The operating system includes an operating system suitable for online processing, an operating system for real-time processing, an operating system excellent in a graphical user interface, and the like, each of which has characteristics.

There is known a multi-operating computer system in which one computer is operated by a plurality of operating systems. For a multi-operating computer system, see, for example,
-149385.

In a multi-operating computer system, for an interrupt generated from a peripheral device such as a mouse or a keyboard, an operating system receiving an interrupt request is determined for each interrupt number, and the interrupt number of the generated interrupt is determined. Is used to switch the operating system.

On the other hand, in an existing computer system, peripheral devices are added. In this case, the interrupt signal lines of the computer system are limited and cannot be easily increased. For this reason, PCI (Peripheral Co.
A plurality of peripheral devices, such as a group of peripheral devices connected to an mponent interconnect (Mponent Interconnect) bus, often use one interrupt signal line in common. Further, interrupts from a plurality of peripheral devices may be collected by one interrupt management device, and one interrupt signal line may be commonly used.

[0006]

In the prior art, since the operating system that receives an interrupt request is determined for each interrupt number, the same interrupt number (common interrupt number) is used.
The same operating system must control all of the plurality of peripheral devices that perform interrupts. For this reason, there is a problem that a required operating system cannot be assigned to a device.

An object of the present invention is to easily assign an operating system required to a plurality of operating systems even when the plurality of devices share the same interrupt number when the plurality of operating systems are operated by a single processor. And a multi-operating computer system.

[0008]

A feature of the present invention is to determine which device has generated an interrupt by a common interrupt number among a plurality of devices, and to determine which device has generated an interrupt from a plurality of operating systems. The operating system assigned to is started.

According to the present invention, it is determined which device has generated the interrupt by the common interrupt number, and the operating system assigned to the device in which the interrupt has occurred from a plurality of operating systems is started. Operating system can be easily assigned.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the overall configuration of an embodiment of the present invention.

In FIG. 1, a computer system includes a processor 100, a memory 101, an interrupt control device 102, an interrupt signal line 104, and a display (image output device) 10.
5, sensor 106, keyboard 107, mouse 108,
It comprises a clock interrupt generator 109, an interrupt bus 110, an interrupt management device 130, and the like.

A processor 100, a memory 101, an interrupt controller 102, a display 105, a sensor 106,
The keyboard 107, the mouse 108, and the clock interrupt generator 109 are connected by the processor bus 103.
The display 105, the clock interrupt generator 10
9. The interrupt management device 130 is connected to the interrupt control device 102 via the interrupt signal line 104 and notifies completion of the input / output operation.

The sensor 106, keyboard 107, and mouse 108 are connected to an interrupt management device 130. Therefore, interrupts from the sensor 106, the keyboard 107, and the mouse 108 are notified to the interrupt controller 102 with the same interrupt number (common interrupt number). Display 10
5, sensor 106, keyboard 107, mouse 108,
When the clock interrupt generator 109 generates an interrupt, it is input to the interrupt controller 102 via the interrupt signal line 104. The interrupt control device 102 converts this signal into a numerical value as an interrupt number and supplies the signal to the processor 100 via the interrupt bus 110.

The display 105 generates an interrupt when screen output is completed, the sensor 106 generates an interrupt when measured data exceeds a certain value, and the keyboard 107 and the mouse 108 generate an input such as pressing a button. An interrupt is generated when a call is made. Clock interrupt generator 10
9 generates an interrupt every fixed period. The interrupt from the clock interrupt generator 109 is used for clocking of the operating system and the like.

The processor 100 is a microprocessor for operating a plurality of operating systems. The memory 101 includes a first operating system 111, a second operating system 112, and a task unit 113 operating on each operating system.
To 118, rescheduler units 119 and 120 for scheduling tasks of each operating system,
Input / output driver units 121 and 122 for each operating system, interrupt handler units 123 and 124 for each operating system, inter-OS control unit 125
Hold. The inter-OS control unit 125 includes an OS context switching unit 126, a common interrupt handler unit 127, and an interrupt generation device specifying unit 128. These processing units are read and executed by the processor 100.
Further, the processor 100 has a mask function for inhibiting an interrupt input by the interrupt bus 110.

Operating systems 111 and 112
Executes the tasks 113 to 118 using the memory and the processor resources allocated to each user. Task 11
Tasks 3 to 115 are tasks executed by the first OS 111, and tasks 116 to 118 are tasks executed by the second OS 112.

Operating systems 101 and 102
The interrupt handler units 123 and 124 are called from the common interrupt handler unit 127 and execute an interrupt process corresponding to the interrupt number. Input / output driver units 121 and 122
Performs an interface for controlling the peripheral device from each of the tasks 113 to 118, and inputs / outputs data by reading / writing the peripheral device.
To 109 are controlled. The input / output driver units 121 and 122 also include an interrupt process for a peripheral device to be controlled.

The rescheduler units 119 and 120 store the execution environment (contents of each register in the processor 100) of the task executed immediately before, respectively.
0 is stored in the task management table in the internal memory area, a task to be newly executed is determined, and the execution environment of the task is taken out from the task management table and set in each register inside the processor 100 to select the task. Perform tasks.

The interrupt management device 130 collects the interrupts from the sensor 106, the keyboard 107, and the mouse 108 into one interrupt number, and notifies the interrupt control device 102. The interrupt management device 130 has a device identification register 131 for specifying an interrupt generation device.

FIG. 2 shows an example of the configuration of the device identification register 131. Each bit of the device identification register 131 is
The presence or absence of an interrupt from each peripheral device connected to the interrupt management device 130 is shown. For example, a bit “0” indicates the presence or absence of an interrupt from the sensor 106, and when the bit “0” is “1”, it indicates that an interrupt from the sensor 106 has occurred. Conversely, when the bit “0” is “0”, it indicates that no interrupt from the sensor 106 has occurred. Like bit “0”, bit “1” and bit “2” indicate the presence or absence of an interrupt from keyboard 107 and mouse 108, respectively.

Each bit of the device identification register 131 is set when the interrupt from each peripheral device connected to the interrupt management unit 130 is notified.
It is set to “1” by 0. After that, the input / output driver units 121 and 122 of the OS set “0” at the end of the interrupt processing.
Set.

FIG. 3 shows the relationship between the respective processing units centering on the common interrupt handler unit 127. A solid arrow in the drawing indicates that the processing unit indicated by the arrow is called.
A dotted arrow indicates that the item indicated by the arrow is referred to.

When an interrupt is generated from a peripheral external device or the like, the interrupt is notified from the interrupt control device 102 to the processor 100 via the interrupt bus 110. In general,
In a computer system controlled by a single operating system, all interrupts are temporarily processed by an interrupt handler unit, and then distributed to each input / output driver unit. However, in the computer system that operates a plurality of operating systems as described in the present embodiment, before this, the common interrupt handler unit 127 receives all the interrupts and sends them to the corresponding interrupt handler unit of the operating system. It becomes a form to be sorted.

The outline of the interrupt processing will be described below with reference to FIG. From the figure, the order of processing is shown.

First, when an interrupt is generated from a peripheral device, the interrupt controller 110
Call 27 (). Common interrupt handler section 127
Refers to the shared IRQ flag table (IRQ means interrupt number) 303, and calls the interrupt generation device specifying unit 128 if the generated interrupt shares the interrupt number ().

The interrupt generating device specifying unit 128 specifies the interrupt generating device with reference to the device identification register 131 of the interrupt management device 130 and notifies the common interrupt handler unit 127. The common interrupt handler unit 127 refers to the interrupt allocation table 302, determines the OS that processes the current interrupt, and calls the OS context switching unit 126 ().

The OS context switching unit 126 switches the OS context when the OS that processes the current interrupt is not the currently executing OS. The common interrupt handler unit 127 refers to the interrupt handler table 301 and calls the interrupt handler unit (123 or 124) of the OS that processes the current interrupt ().

The interrupt handler table 301 stores the start addresses of the interrupt handler sections of the respective OSs 111 and 112. The interrupt handler unit (123 or 124) calls the input / output driver unit (121 or 122) of the interrupt processing target device to execute () interrupt processing, and if the task switching is required as a result of the interrupt processing, the rescheduler Part (119 or 120)
Call ().

FIG. 4 shows the interrupt allocation table 302. The interrupt assignment table 302 includes a device number and an interrupt assignment destination OS. In the item of the interrupt destination OS, an OS that processes an interrupt from the device of the device number is stored. “0” is stored when the interrupt destination OS is the first OS, and “1” is stored when the interrupt allocation destination is the second OS.

Conventionally, the interrupt assignment destination OS is determined by the interrupt number, but in the present invention, the interrupt assignment destination OS is determined by the device number. Therefore, for a device that does not share an interrupt number with another device, the interrupt number is used as the device number. The device number of the device that shares the interrupt number with another device is determined by the interrupt generation device specifying unit 128 from the device number table 304.

As shown in FIG. 6 (described later), if the device numbers of the sensor 106, the keyboard 107, and the mouse 108 are 20, 21, and 22, respectively, the OS to which the interrupt is allocated for these device numbers is stored. You.

FIG. 5 shows an example of the shared IRQ flag table 303. The shared IRQ flag table 303 includes interrupt numbers and a shared IRQ flag for each interrupt number. The shared IRQ flag indicates whether each interrupt number is shared by a plurality of peripheral devices, and stores “1” when shared, and stores “0” when not shared.

For example, in FIG. 1, the sensor 106, the keyboard 107, and the mouse 108 share an interrupt number,
Assuming that the interrupt number from these device groups is 2, the shared IRQ flag becomes 1 in the section where the interrupt number is 2 in the shared IRQ flag table 303.

FIG. 6 shows an example of the device number table 304. The device number table 304 includes a device type and a device number corresponding to the device. If the device numbers of the sensor 106, the keyboard 107, and the mouse 108 are defined as 20, 21, and 22, respectively, the device number 20 of the peripheral device is added to the device number section of the device number table 304.
21 and 22 are stored.

The OS context switching unit 126 includes data of an executing OS storage unit 305. The OS context switching unit 126 saves the current OS context (the contents of each register in the processor 100) in a memory area in the OS context switching unit 126 in order to switch the OS under execution. The context of the switching destination OS stored in the memory area is written back to the register inside the processor 100. Also,
If you don't know which OS is currently running,
Since it is not possible to determine which OS context should be saved at the time of OS switching, the running OS storage unit 305 stores which OS is currently being executed. For example, if the currently executing OS is the first OS 111, “0” is set to the second OS,
If it is 112, “1” is stored in the running OS storage unit 305.

FIG. 7 shows a processing flow of the common interrupt handler section 127.

The common interrupt handler section 127 executes with interrupts disabled. First, in process 700, the common interrupt handler unit 127 acquires the interrupt number of the interrupt that has occurred this time from the interrupt control device 102. Process 70
In step 1, the OS to which the interrupt is to be allocated is determined. In the process 701, a value of 0 is obtained if the interrupt allocation destination OS is the first OS 111, and a value of 1 is obtained if the interrupt allocation destination OS is the second OS 112. By the process 701, even in the case of an interrupt from a peripheral device sharing an interrupt number, which is a feature of the present invention, the interrupt destination OS corresponding to the peripheral device from which the interrupt occurred can be determined. The details of the process 701 will be described later with reference to FIG.

The process shifts from the process 701 to the process 702 to retrieve the contents of the running OS storage unit 305 and determine whether the currently running OS is the first OS 111 or the second OS 112. The currently running OS is the first OS 11
A value of "0" is obtained for 1 and a value of "1" is obtained for the second OS 112.

In step 703, it is checked whether or not the interrupt destination OS obtained in step 701 is equal to the currently executed OS obtained in step 702. In particular,
If the value obtained in step 701 is equal to the value obtained in step 702, it is determined that the interrupt allocation destination OS is the same as the OS currently being executed. Conversely, when the value obtained in the process 701 is different from the value obtained in the process 702, it is determined that the interrupt assignment destination OS is different from the OS currently being executed.

If the OS to which the interrupt is to be assigned is different from the OS currently being executed, the OS must be switched once. In this case, in the process 704, the OS switching process is performed by calling the OS context switching unit 126. The OS context switching unit 126 switches the OS under execution to the OS to which the interrupt is allocated, and the OS storage unit 305 under execution.
Is stored in the OS.

Next, in process 705, the common interrupt handler unit 127 determines that the interrupt allocation destination OS is the first OS 11
Check whether it is 1 or 2nd OS 112,
If the target is the first OS 111, the interrupt handler unit 123 of the first OS is activated in step 706 with reference to the interrupt handler table 301. Second OS 112
If an interrupt has occurred, the interrupt handler unit 124 of the second OS is activated in step 707 with reference to the interrupt handler table 301.

The interrupt handler units 123 and 124 call the input / output driver units 121 and 122 to perform interrupt processing for the interrupt generation device. In general, the interrupt handler units 123 and 124 need to perform task switching in interrupt processing when the rescheduler unit 119
Call 120 and execute the corresponding task. on the other hand,
If task switching does not occur, the interrupt handler unit 12
3 and 124 return control to the common interrupt handler unit 127 (to be described later with reference to FIG. 10), and the common interrupt handler unit 127
Resumes operation from step 708.

In step 708, it is checked whether or not the operating system has been switched when an interrupt occurs. When the operating system is switched by the process 704, in the process 709, the OS context switching unit 126 is called to execute the OS switching process.
The OS to be executed is switched to the OS that was being executed when the interrupt occurred.

FIG. 8 shows an interrupt allocation destination OS determination process 701.
3 shows a detailed processing flow. The process 701 uses the interrupt number passed from the interrupt control device 102. First, in process 800, the shared IRQ flag corresponding to the designated interrupt number is acquired with reference to the shared IRQ flag table 303. If the shared IRQ flag is “0” in the processing 801, the interrupt number is equal to the device number. In the processing 802, the interrupt allocation destination OS is acquired by referring to the interrupt allocation table 302 using the interrupt number as the device number. If the value of the interrupt assignment destination OS is “0”, an interrupt is assigned to the first OS 111, and if the value is “1”, an interrupt is assigned to the second OS 112.

In the process 801, if the shared IRQ flag acquired in the process 800 is “1”, the process 128
Specifies the interrupt generation device. In the processing 803, the interrupt allocation destination OS corresponding to the device number of the interrupt generation device is acquired with reference to the interrupt allocation table 302, and the interrupt allocation destination OS determination processing 701 is terminated. The interrupt generation device specifying process 128 will be described with reference to FIG.

FIG. 9 shows an interrupt generation device specifying process 128.
3 shows a processing flow. First, in process 900, an interrupt generation device is specified with reference to the device identification register 131 provided in the interrupt management device 130.
Thereafter, in process 901, the device number table 3
With reference to 04, the device number of the interrupt generation device is acquired from the interrupt generation device type specified in the process 900. For example, when an interrupt from the sensor 106 occurs, the device type of the device number table 304 refers to the item of the sensor, and the device number 20 is obtained.

FIG. 10 shows the interrupt handler section 12 of the first OS 111 called from the common interrupt handler section 127.
3 shows a processing flow of No. 3; In the process 1000, the value of each register inside the processor 100 is saved in the memory area inside the interrupt handler unit 123. Processing 1
At 001, an interrupt number is obtained from the interrupt control device 102.

Next, in process 1002, an interrupt process corresponding to the obtained interrupt number is executed. If it is necessary to switch tasks in the interrupt processing, the value of the task switching flag inside the rescheduler 119 is set to "1". For example, if a sensor interrupt occurs in a state where there is a task that is stopped waiting for an interrupt from the sensor 106, the task is changed from a stopped state to an executable state. The process sets the value of the task switching flag section to "1".
In the process 1003, it is checked whether or not the operating system is performing rescheduling when an interrupt occurs (that is, whether or not the process of the rescheduler unit 119 is being executed). Re-scheduling means that the task to be executed next is being selected and the task is not actually executed. Therefore, if it is determined that rescheduling is being performed, the save register of the interrupt stack is discarded in process 1008, and the process 100
In step 9, the rescheduler unit 119 is started from the beginning.

When the interrupt handler 123 determines that rescheduling is not being performed, the operating system is executing some task at that time. For this reason, it is determined in the process 1004 whether task switching is necessary. Specifically, if the value of the task switching flag section inside the rescheduler section 119 is “1”, it is determined that task switching is necessary. If the value of the task switching flag is other than "1", it is determined that task switching is not required. If task switching is not required, the processing of the interrupt handler unit 123 is terminated as it is. At that time, in a process 1005, the value of the register of the processor 100 saved in the memory area inside the interrupt handler unit 123 in the process 1000 is written back to each register of the processor 100.

Next, in process 1006, control is returned to the common interrupt handler section 127. If it is determined that task switching is necessary, the process
00, the value of the register of the processor 100 saved in the memory area inside the interrupt handler unit 123 is copied to the task management table in the memory area inside the rescheduler unit 119. The value of the register of the processor 100 saved in the area is discarded. Thereafter, processing 1
In 009, the rescheduler unit 119 is called. When any task of the first OS 111 is to be operated as a result of the rescheduling, the task is executed as it is.

The interrupt handler section 12 of the second OS 112
4 is executed by the interrupt handler unit 12 of the first OS 111.
3 is the same as the process. However, in the present embodiment, since the first OS 111 is executed prior to the second OS 112, any task of the second OS 112 may operate as a result of the rescheduling in the interrupt handler unit 124. When any of the tasks is operating in the first OS 111, the task of the second OS 112 does not operate. The OS context is switched to the first OS 111 by the inter-OS control 125, and the first OS
The task of S111 is executed.

As described above, according to the present invention, it is determined which device has generated an interrupt by a common interrupt number among a plurality of devices, and a plurality of operating systems activate an operating system assigned to the device in which the interrupt has occurred. The operating system required for the device can be easily assigned.

In the above-described embodiment, the device in which the interrupt occurred is specified by referring to the device identification register 130. However, all devices sharing the interrupt number are directly accessed to specify the device in which the interrupt occurred. Obviously, you can.

[0055]

According to the present invention, even when a plurality of operating systems are operated by a single processor and a plurality of devices share an interrupt number, an interrupt by a common interrupt number among a plurality of devices is determined. Since it is determined whether a device has occurred and the operating system assigned to the device where the interrupt has occurred from multiple operating systems is started,
The operating system required for the device can be easily assigned.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example configuration of a device identification register.

FIG. 3 is a configuration diagram illustrating details of an interrupt processing unit.

FIG. 4 is a diagram showing an example configuration of an interrupt allocation table.

FIG. 5 is a diagram showing an example configuration of a shared IRQ flag table.

FIG. 6 is a diagram illustrating an example configuration of a device number table.

FIG. 7 is a processing flowchart for explaining the operation of the present invention.

FIG. 8 is a processing flowchart for explaining the operation of the present invention.

FIG. 9 is a processing flowchart for explaining the operation of the present invention.

FIG. 10 is a processing flowchart for explaining the operation of the present invention.

[Explanation of symbols]

100: Processor, 101: Memory, 102: Interrupt control device, 103: Processor bus, 104: Interrupt signal line, 105: Display, 106: Sensor, 107
... Keyboard, 108, mouse, 109, clock interrupt generator, 110, interrupt bus, 111, first OS,
112 ... second OS, 113 ... task A, 114 ... task B, 115 ... task C, 116 ... task D, 117 ...
Task E, 118: Task F, 119: Rescheduler section of the first OS, 120: Rescheduler section of the second OS, 121: Input / output driver section of the first OS, 122 ...
I / O driver section of the second OS, 123: interrupt handler section of the first OS, 124: interrupt handler section of the second OS, 125: inter-OS control section, 126: OS context switching section, 127: common interrupt Handler unit, 128: interrupt generation device specifying unit, 130: interrupt management device, 1
31: Device identification register, 301: Interrupt handler table, 302: Interrupt allocation table, 303: Shared IRQ flag table, 304: Device number table, 305: Running OS storage unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Tadashi Uewaki 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Works of Hitachi, Ltd. (72) Inventor Hiroshi Ohno 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 F term in Hitachi Ltd. Omika Works (reference) 5B098 BA03 BA11 BB11 EE06 GA02 GC01 HH04 HH08

Claims (5)

[Claims] 1. A multi-operating computer system in which a plurality of operating systems are switched to operate one processor and a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt signal line. It is characterized by determining which device has caused an interrupt by a common interrupt number among a plurality of devices, and activating an operating system assigned to the device in which the interrupt has occurred from the plurality of operating systems. Multi-operating computer system. 2. A multi-operating computer system in which a plurality of operating systems are switched to operate one processor and a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt signal line. By managing interrupts of a plurality of devices, when an interrupt of the common interrupt number occurs, a device that has generated an interrupt by a common interrupt number among the plurality of devices is determined, and the device that has generated an interrupt from the plurality of operating systems is determined. A multi-operating computer system, wherein an assigned operating system is started. 3. A multi-operating computer system in which a plurality of operating systems are switched to operate one processor and a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt signal line. A device number is determined for each of the plurality of devices, and when an interrupt of the common interrupt number occurs, a device that has generated an interrupt by the common interrupt number among the plurality of devices is determined, and the plurality of devices are determined based on the device number of the device. A multi-operating computer system for activating an operating system assigned to the device in which an interrupt has occurred from the operating system. 4. A multi-operating computer system in which a plurality of operating systems are switched to operate one processor and a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt signal line. Interrupt management means for managing the occurrence of interrupts of a plurality of devices; interrupt control means for inputting an interrupt signal based on a common interrupt number from the interrupt management means via an interrupt line; Device identifying means for determining a device; and interrupt handler means for activating an operating system assigned to the device which has generated an interrupt from the plurality of operating systems based on the device identified by the device identifying means. Multi-operating Calculation system. 5. A multi-operating computer system in which a plurality of operating systems are switched to operate one processor and a plurality of devices generate an interrupt with a common interrupt number assigned to a common interrupt signal line. Interrupt management means for managing interrupt generation of a plurality of devices and a device which has generated the interrupt; interrupt control means for inputting an interrupt signal by a common interrupt number from the interrupt management means via an interrupt line; Of the device that has generated an interrupt, and a device specifying unit that specifies a device number of the device; and a device that has been allocated to the device that has generated an interrupt from the plurality of operating systems based on the device number specified by the device specifying unit. Start the operating system Multi operating rate proboscis computer system characterized by comprising a write handler means.