JPH11167494A - Arithmetic processor and register managing method for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate processings of saving and restoration of register data when procedure call or interruption is generated without providing plural register sets. SOLUTION: A retained flag is provided in each register in a register set 5 in a processor 1, and when procedure call or interruption is generated, all of the retained flags are cleared. When a retained flag corresponding to a time to write into the register is not set during a procedure or interruption processing, the value of the register is retained in a memory and a retained flag is set, and at the time of returning from the procedure or interruption processing, only data in the register set with the retained flag is restored to minimize saving processing of registered data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPU (Micro Processing Uni) for a computer system.
t: ultra-compact processing unit), CPU (Central)
Processing Unit: Central Processing Unit)
And more particularly to an arithmetic processing device (hereinafter simply referred to as a processor), and particularly to an arithmetic processing device that speeds up the process of saving and restoring register data when a procedure call or an interrupt occurs, and a register of the arithmetic processing device. Regarding management methods.

[0002]

2. Description of the Related Art Conventionally, when a program is executed by a processor and a procedure call or an interrupt occurs, when a register is used in a newly started process, the register is used in the process which has been executed until then. In order to save the data, the data held in the register is written to a save area on the memory. Such a writing process to the memory causes a reduction in processing performance.

[0003] As a method of solving the above problems,
A method of providing a plurality of register sets that can be used in a processor has been proposed. In this method, the register data is not saved by switching to a new register set each time a procedure call or an interrupt occurs.

[0004]

However, the above-described method using the register set has the following problems.

That is, since a register is required to operate at a high speed, it becomes a complicated and large-scale circuit. Providing a plurality of register sets greatly increases the amount of hardware of the processor. When a plurality of register sets are provided,
A circuit for switching the register set must be provided between the arithmetic circuit in the processor and the register set,
This hinders the speeding up of the circuit operation. In addition, since a sufficient number of register sets cannot be prepared due to the limitation of the amount of hardware, all register sets may be used up during the processing of a program. In this case, the processing cannot be continued unless the data of at least one register set is stored in the memory, and the processing performance is reduced at that time.

[0006] When the called procedure or the processing performed by an interrupt is simple, not all the registers are used, but in the register setting method, a plurality of all registers are prepared. It is a waste of hardware resources.

The present invention has been made in view of the above circumstances, and solves the above-mentioned disadvantages, and saves and restores register data when a procedure call or an interrupt occurs without providing a plurality of register sets. An object of the present invention is to provide an arithmetic processing device capable of speeding up processing and a register management method for the arithmetic processing device.

[0008]

According to the present invention, there is provided an arithmetic processing device for controlling various processes of a computer system by executing a program, the data being used when the arithmetic processing device executes a program. Register means comprising a plurality of registers for storing a saved flag which is set when the data is saved in a save area on the memory of the computer system corresponding to the data; control means for controlling the register means and the memory; The control means clears the stored flag when a procedure call or an interrupt process occurs when the arithmetic processing unit executes a program, and writes data to the register in the procedure call or the interrupt process. The saved flag corresponding to the register to be written is set If not, the saved flag is set and the data of the register to be written is saved in the save area on the memory. After the procedure call or the interrupt processing is completed, the saved flag of the saved flag is saved from the save area on the memory. Only for the set register, read the data of the register corresponding to this register, return to the register where the saved flag is set, clear the saved flag, and resume the procedure call or the process before the occurrence of the interrupt It is characterized by the following.

According to the above configuration, the stored flags are provided in the respective registers in the processor, and all the stored flags are cleared when a procedure call or an interrupt occurs. If the corresponding saved flag is not set at the time of execution, the value of the register is saved in the memory, the saved flag is set, and when returning from the procedure or the interrupt processing, the saved flag is set. By restoring the data only in the register in which the data is stored, the effect of minimizing the save processing of the register data is obtained.

In addition to the above configuration, if a write buffer for temporarily storing data for writing data from the processor to the memory is provided, when the register data is recovered, the write for storing the register data is performed in the write buffer. If there is any unprocessed data, the write data is written back to the register and the write process itself is canceled, thereby reducing the number of writes to the memory and speeding up the recovery of the register data.

Further, in addition to the above configuration, the present invention relates to a write buffer for buffering data to be written to a memory from a processor, wherein a write buffer for a memory command for storing register data is provided separately from a write buffer for normal memory writing. If the former write buffer has free space, the latter write buffer process is given priority over the former write buffer process, and if the former write buffer becomes full, the former write buffer process is prioritized. By adjusting the write processing so as to cause the normal memory write to be prevented from being interrupted by the memory write of the register data.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing a general structure of a computer according to an embodiment of the present invention. In addition to this, this computer is assumed to have a configuration necessary for an ordinary computer system, such as various I / O devices such as a keyboard and a display, and a storage device such as a hard disk.
Portions not particularly related to the description of the present embodiment are not shown, and details are omitted. The processor 1 controls each component of the computer system, and exchanges data with the memory 2 via the bus 3.

FIG. 2 shows an example of a general internal configuration of the processor 1. The execution unit 4, the register set 5, and the control unit 8 are connected by an internal bus 6. The execution unit 4 performs arithmetic processing on the data. The register set 5 includes a plurality of registers.
The control unit 8 controls the execution unit 4 and the register set 5 in order to realize an operation specified by an instruction constituting a program. Write buffer 7
When data is written from the processor 1 to the memory 2, buffering of the write data is performed so that the processor 1
Can start the next process.

FIG. 3 is a diagram showing an example of a register save area secured on the memory 2. If a procedure call or an interrupt occurs during the execution of the program, a new save area for saving register data is secured. The address of the save area in use is normally held in a register in the processor.

FIG. 4 is a diagram showing a configuration example of the register set of the present embodiment. The information of the stored flag 10 is stored corresponding to each of the registers 9 constituting the register set.

FIG. 5 is a diagram showing an example of a register save area according to this embodiment. In addition to the normal register data, the saved flag 10 at the time when the procedure call or the interruption occurs is saved as save data 11 in the save area. The control unit 8 operates as shown in FIGS. 6 and 7 with respect to the management of register data in the processing of procedures and interrupts.

FIG. 6 shows a flow of processing for managing register data of the control unit 8 when a procedure call or an interrupt occurs.

First, when a procedure call or an interrupt occurs (step A1), the saved flag 10 is saved as saved data 11 in the current save area on the memory 2 (step A2), and then the saved flag is saved. 10 is cleared (step A3), and a new save area is created (step A4). Next, execution of a procedure or interrupt processing program is started (step A5). The instruction of the program is decoded (step A6), and it is determined whether or not writing to the register occurs (step A6).
7). When writing has occurred in the register (Yes in step A7), it is determined whether or not the stored flag corresponding to the register has been set (step A8).

If the stored flag is set (Yes in step A8), data is written to the register without doing anything (step A11). If the stored flag is not set (No in step A8), the register data is stored in the write buffer for writing to the current save area (step A9), the stored flag is set (step A10), and the register is set. Is written (step A11).

If writing to the register does not occur (No in step A7), the instruction is executed as it is (step A12). Execute the instruction (step A1
2) Next, it is determined whether the instruction has been completed (step A13). When the instruction is completed (Y in step A13)
es) ends the procedure call or interrupt processing. If the instruction has not been completed (N in step A13)
o) The next instruction is decoded (step A6).

FIG. 7 shows a flow of processing when the procedure call or the interrupt processing ends and returns to the original processing.

When the procedure call and the interrupt processing are completed (step B1), the data is restored from the save area only for the register in which the stored flag is set (step B2). Next, the saved data 11 of the immediately preceding save area is restored to the saved flag 10 (step B).
3) The previous save area is set as the current save area (step B4). Thereafter, the processing before the occurrence of the procedure call or the interrupt processing is restarted (step B5).

As described above, by storing the information of the saved flag 10 corresponding to each register 9 constituting the register set, it is not necessary to save each register by a program, and the program can be easily created. become. Further, since only the minimum necessary registers are stored, the number of writing processes to the memory is reduced, and the processing performance of the program is improved.

FIG. 8 is a flow chart showing the flow of processing for the write buffer 7 of the control unit 8 with respect to the management of register data according to the present embodiment.

In the process of restoring the register data from the save area, first, it is determined whether or not the register data is in the write buffer 7 (step C1). When the register data is not in the write buffer 7 (N in step C1)
o), the register data is restored from the save area (step C5). If the register data is in the write buffer 7 (Yes in step C1), the write buffer 7
From the register data (step C2).

Next, it is determined whether or not the writing of the register data to the memory 2 has not been processed (step C3). If the register data writing process has been performed (No in step C3), the process ends. If the writing of the register data has not been processed (Yes in step C3), the processing of writing the register data into the memory 2 is canceled (step C4).

As described above, when the register data is restored from the save area, the ordinary processor performs the read processing of the memory after all the contents of the write buffer have been written out. When the register data remains in the write buffer 7, the data is restored from the write buffer to the register, thereby reducing read access to the memory and realizing high speed. Furthermore, when the register data write processing is not performed, the write processing itself is canceled to reduce memory access.

FIG. 9 is a diagram showing an example of the configuration of the write buffer 7. Each entry is composed of write data 14 to be written to the memory, a write address 13 which is a memory address of a write destination, and individual entries.
An unprocessed flag 12 indicates that the writing process to the memory 2 is not performed. In such a configuration, the process of restoring the register data from the write buffer in FIG. 8 involves comparing the address to be read from the save area with the write address 13, and if there is a match, the corresponding write data 14 is stored in the register. Forward.

FIG. 10 is a diagram showing another configuration example of the write buffer. In this example, in order to write the memory for saving the register, the write buffer 16 for saving the register is used.
Was provided separately. The general write buffer 15 is used for normal memory writing. When there is data to be written in both write buffers, the priority control unit 17 controls which write process is executed.

The priority control unit 17 controls the process 15 of the general write buffer when the register saving write buffer 16 has a free space, and when the register write buffer 16 runs out of space, the register saving process is performed. The processing of the write buffer 16 has priority. In a normal processor, memory write due to register saving occurs when a procedure call or interrupt processing is started, but this method has an effect of distributing memory write due to register saving and has an effect of program processing. Therefore, it is possible to reduce the performance degradation caused by preventing the memory writing.

FIG. 11 shows an example of the configuration of the register save write buffer 16 of FIG. Since the relative position where each register data is saved in the save area is fixed, from the address of the save area and the register number,
The address at which the data of the register is written can be easily generated. Therefore, as shown in FIG. 9, instead of preparing a write address for each entry, a register number 19 which is a register number for storing data is set instead.
A register for storing the current save area pointer is prepared, and a write address 20 is generated when a write process is performed. Thus, a storage area for storing the write address can be saved.

[0033]

As described above in detail, according to the present invention, it is necessary to save registers by a program by storing information of a saved flag corresponding to each register constituting a register set. Gone,
Program creation becomes easy. Furthermore, since only the minimum necessary registers are stored, the number of write operations to the memory is reduced, and the processing performance of the program is improved.

Further, a buffer is provided for temporarily storing the write processing to the memory, and when the register data is restored when the procedure or the interrupt processing is completed, data for saving the register data remains in the buffer. If
By returning data from the buffer to the register without reading from the memory, there is an effect that read access to the memory is reduced and the processing performance of the program is improved.

Further, at the time of register data restoration upon completion of the above-described procedure or interrupt processing, if the write processing for the memory has not been completed in the write processing for the buffer, the write processing for the memory is performed. By not doing so, there is an effect that the performance of the computer system is improved by reducing the write access to the memory in the processing of the procedure and the interrupt and decreasing the occupancy of the bus.

Further, a normal write buffer and a write buffer for saving register data are provided in the buffer, and the process of the normal write buffer is prioritized over the process of the write buffer for saving register data. Is less hindered by the memory write access for register saving, and the processing efficiency of the program is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a processor according to the embodiment.

FIG. 3 is a conceptual diagram of a memory according to the embodiment.

FIG. 4 is a conceptual diagram of a register according to the embodiment;

FIG. 5 is a conceptual diagram of a memory according to the embodiment.

FIG. 6 is a flowchart showing a processing operation when a procedure call or an interrupt processing occurs according to the embodiment;

FIG. 7 is a flowchart showing a processing operation for resuming processing before a procedure call or an interrupt occurs after a procedure call or an interrupt processing is completed according to the embodiment;

FIG. 8 is a flowchart showing a processing operation for restoring register data from a save area according to the embodiment;

FIG. 9 is a diagram showing a configuration of a write buffer according to the embodiment.

FIG. 10 is a diagram showing a configuration of a write buffer shown in a state different from that of FIG. 9 according to the embodiment;

FIG. 11 is a diagram showing a configuration of a register save write buffer according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Memory 3 ... Bus 4 ... Execution unit 5 ... Register set 6 ... Internal bus 7 ... Write buffer 8 ... Control unit 9 ... Register 10 ... Saved flag 11 ... Saved data 12 ... Unprocessed flag 13 ... Write address 14 Write data 15 General write buffer 16 Register save write buffer 17 Priority control unit 18 Save area pointer 19 Register number 20 Write address 21 Unprocessed flag 22 Write data

Claims (12)

[Claims] 1. An arithmetic processing device for controlling various processes of a computer system by executing program information, wherein when the arithmetic processing device executes the program information, data used is stored in a memory of the computer system corresponding to the data. Register means comprising a plurality of registers for storing saved flag information to be set when the data is saved in the save area, and control means for controlling the register means and the memory. When a procedure call or an interrupt occurs when the arithmetic processing unit executes the program information, the stored flag information is cleared. When the register is written in the procedure call or the interrupt, the register in which the write is performed is performed. The saved flag information corresponding to If the stored flag information is set, the data of the register to be written is saved in the save area on the memory, and after the procedure call or the interrupt processing is completed, the saved flag information is saved from the save area on the memory. Only for the set register, read the data of the register corresponding to this register, return to the register where the stored flag information is set, clear the stored flag information, and execute the procedure before calling the procedure or interrupt. An arithmetic processing device characterized by restarting. 2. The control means according to claim 1, wherein said stored flag information is stored in a save area on said memory when said procedure call or interrupt processing is performed, and said stored flag information is set in said register. Clear the saved flag information, and if the register is written in the procedure call or interrupt processing, set the saved flag information if the saved flag information corresponding to the register in which the writing is performed is not set. The data of the register to be written is secured and saved in another save area on the memory. After the procedure call or the interrupt processing is completed, the saved flag information is set from the other save area on the memory. Read the data of the register corresponding to this register only for the register To return to the register where the saved flag information is set, clear the saved flag information, and save the saved flag information to the setting before the procedure call or interrupt processing occurrence based on the information saved in the save area. The arithmetic processing device according to claim 1, wherein the operation is returned. 3. A register in which said data is temporarily stored when said data is written and stored in said memory, and wherein said stored flag information is set in said buffer after completion of said procedure call or interrupt processing. When the data of the stored flag information remains, the data of the register in which the stored flag information is set is restored from the buffer means to the register in which the stored flag information is set without reading the data from the save area on the memory. The arithmetic processing device according to claim 1, wherein: 4. A register in which said data is temporarily stored when said data is written and stored in said memory, and wherein said stored flag information is set in said buffer after completion of said procedure call or interrupt processing. If the data of the stored flag information remains, the data of the register in which the stored flag information is set from the buffer means is not read from another save area on the memory. 3. The arithmetic processing device according to claim 2, wherein the operation is returned to a register. 5. When the data of the register in which the stored flag information is set remains in the buffer means, and when the writing of the data to the memory is not completed, the writing to the memory is not performed. The arithmetic processing device according to claim 3 or 4, wherein: 6. The buffer means includes: a general write buffer used for writing to the memory; a register save buffer for saving the register; a general write buffer and the register save buffer. Priority control means for controlling the priority of the write processing of the register. The priority control means is provided in the register save buffer when there is write data in both the general write buffer and the register save buffer. 4. The method according to claim 1, wherein when there is free space, the processing of the general write buffer is prioritized, and when there is no free space in the register save buffer, the process of the register save buffer is prioritized. The arithmetic processing unit according to claim 5. 7. A register management method for an arithmetic processing unit for controlling various processes of a computer system by executing program information, wherein the arithmetic processing unit executes a program, and uses data to be used and corresponding to the data. When the above-mentioned data is stored in the save area on the memory of the computer system, stored flag information to be set is stored in a plurality of registers, and when the above-mentioned arithmetic processing unit executes the program information ヲ, when a procedure call or an interrupt process occurs. Clearing the stored flag information stored, if writing to the register is performed in the procedure call or interrupt processing, and if the stored flag information corresponding to the register in which the writing is performed is not set, the stored flag information is cleared. Register data to be set and written Is saved in the save area on the memory. After the procedure call or the interrupt processing is completed, the data of the register corresponding to this register is read out from the save area on the memory only for the register in which the saved flag information is set. A register management method for an arithmetic processing unit, wherein the method returns to a register in which the stored flag information is set, clears the stored flag information, and resumes the process before the procedure call or the occurrence of the interrupt. 8. When the procedure call or the interrupt processing occurs, when the stored flag information is set in the register, the information of the stored flag information is stored in a save area on the memory, and then the stored flag is stored. If the information is cleared, and if the write to the register is performed in the procedure call or the interrupt processing, if the stored flag information corresponding to the register to be written is not set, the stored flag information is set and the The data of the register to be executed is saved by securing another save area in the memory. After the procedure call or the interrupt processing is completed, the register in which the saved flag information is set from the other save area in the memory. Only read the data of the register corresponding to this register Restore the saved flag information to the register where the saved flag information is set, clear the saved flag information, and return the saved flag information to the settings before the procedure call or interrupt processing occurred based on the information saved in the save area. 8. The register management method for an arithmetic processing device according to claim 7, wherein: 9. When the data is written and stored in the memory, the data is temporarily stored in a buffer, and after the procedure call or the interrupt processing is completed, the data of the register in which the stored flag information is set is stored in the buffer. If it remains, the data of the register in which the stored flag information is set is returned from the buffer to the register in which the stored flag information is set without reading the data from the save area on the memory. 8. The register management method for an arithmetic processing device according to claim 7, wherein: 10. When the data is written and stored in the memory, the data is temporarily stored in a buffer, and after the procedure call or the interrupt processing is completed, the data of the register in which the stored flag information is set is stored in the buffer. If the data remains, the data of the register in which the stored flag information is set is returned from the buffer to the register in which the stored flag information is set without reading data from another save area on the memory. 9. The register management method for an arithmetic processing device according to claim 8, wherein: 11. When the data of the register in which the stored flag information is set remains in the buffer and the writing of the data to the memory is not completed, the writing to the memory is not performed. 11. The register management method for an arithmetic processing device according to claim 9, wherein: 12. The buffer according to claim 1, wherein the buffer includes a general write buffer used for writing to the memory, a register save buffer for saving the register, and a buffer for saving the general write buffer and the register save buffer. Priority control means for controlling the priority of the write processing, wherein the priority control means stores the write data in both the general write buffer and the register save buffer when the general data buffer and the register save buffer have write data. 10. The processing of the general write buffer is prioritized when there is free space, and the processing of the register save buffer is prioritized when there is no free space in the register save buffer. Item 12. The register management method for an arithmetic processing device according to item 11.