IN168920B - - Google Patents
Info
- Publication number
- IN168920B IN168920B IN830/CAL/90A IN830CA1990A IN168920B IN 168920 B IN168920 B IN 168920B IN 830CA1990 A IN830CA1990 A IN 830CA1990A IN 168920 B IN168920 B IN 168920B
- Authority
- IN
- India
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/16—Sound input; Sound output
- G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Health & Medical Sciences (AREA)
- Audiology, Speech & Language Pathology (AREA)
- General Health & Medical Sciences (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Error Detection And Correction (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN830/CAL/90A IN168920B (nl) | 1986-07-18 | 1990-09-25 |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/886,615 US4780844A (en) | 1986-07-18 | 1986-07-18 | Data input circuit with digital phase locked loop |
| PCT/US1987/001624 WO1988000733A1 (en) | 1986-07-18 | 1987-07-14 | Data input circuit with digital phase locked loop |
| IN555/CAL/87A IN167723B (nl) | 1986-07-18 | 1987-07-17 | |
| IN830/CAL/90A IN168920B (nl) | 1986-07-18 | 1990-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN168920B true IN168920B (nl) | 1991-07-13 |
Family
ID=25389384
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN555/CAL/87A IN167723B (nl) | 1986-07-18 | 1987-07-17 | |
| IN830/CAL/90A IN168920B (nl) | 1986-07-18 | 1990-09-25 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN555/CAL/87A IN167723B (nl) | 1986-07-18 | 1987-07-17 |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US4780844A (nl) |
| EP (1) | EP0316340B1 (nl) |
| JP (1) | JP2679791B2 (nl) |
| KR (1) | KR950012077B1 (nl) |
| AU (1) | AU593678B2 (nl) |
| CA (1) | CA1283479C (nl) |
| DE (1) | DE3788804T2 (nl) |
| IL (1) | IL83202A (nl) |
| IN (2) | IN167723B (nl) |
| NO (1) | NO180698C (nl) |
| WO (1) | WO1988000733A1 (nl) |
| ZA (1) | ZA875209B (nl) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4930142A (en) * | 1988-12-06 | 1990-05-29 | Stac, Inc. | Digital phase lock loop |
| US5475656A (en) * | 1989-09-27 | 1995-12-12 | Hitachi, Ltd. | Optical disk memory and information processing apparatus |
| US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
| EP0640261A4 (en) * | 1992-05-14 | 1995-04-05 | Vlsi Technology, Inc. | Data transmission delaying circuit using time-multiplexed latch enable signals. |
| US5436937A (en) * | 1993-02-01 | 1995-07-25 | Motorola, Inc. | Multi-mode digital phase lock loop |
| US5406061A (en) * | 1993-06-19 | 1995-04-11 | Opticon Inc. | Bar code scanner operable at different frequencies |
| JPH0784667A (ja) * | 1993-09-14 | 1995-03-31 | Fujitsu Ltd | クロックドライバの異常監視方法及び装置 |
| EP0671829B1 (en) * | 1994-03-11 | 2006-06-28 | Fujitsu Limited | Clock regeneration circuit |
| US5553100A (en) * | 1994-04-01 | 1996-09-03 | National Semiconductor Corporation | Fully digital data separator and frequency multiplier |
| US5463351A (en) * | 1994-09-29 | 1995-10-31 | Motorola, Inc. | Nested digital phase lock loop |
| JP2877198B2 (ja) * | 1996-05-02 | 1999-03-31 | 日本電気株式会社 | ディジタルｐｌｌ回路及びその起動方法 |
| US5859881A (en) * | 1996-06-07 | 1999-01-12 | International Business Machines Corporation | Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources |
| US5983371A (en) * | 1997-07-11 | 1999-11-09 | Marathon Technologies Corporation | Active failure detection |
| JP3715498B2 (ja) * | 2000-02-28 | 2005-11-09 | 富士通株式会社 | 信号制御装置、伝送システム及び信号乗せ換え制御方法 |
| US20080046684A1 (en) * | 2006-08-17 | 2008-02-21 | International Business Machines Corporation | Multithreaded multicore uniprocessor and a heterogeneous multiprocessor incorporating the same |
| US8402303B2 (en) * | 2011-04-29 | 2013-03-19 | Seagate Technology Llc | Method for encoder frequency shift compensation |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4357707A (en) * | 1979-04-11 | 1982-11-02 | Pertec Computer Corporation | Digital phase lock loop for flexible disk data recovery system |
| JPS5720052A (en) * | 1980-07-11 | 1982-02-02 | Toshiba Corp | Input data synchronizing circuit |
| US4470082A (en) * | 1982-07-06 | 1984-09-04 | Storage Technology Corporation | Digital clocking and detection system for a digital storage system |
| JPS5977633A (ja) * | 1982-10-26 | 1984-05-04 | Nippon Gakki Seizo Kk | デイスク再生装置におけるクロツク再生回路 |
| US4550391A (en) * | 1983-02-22 | 1985-10-29 | Western Digital Corporation | Data capture window extension circuit |
| IT1206332B (it) * | 1983-10-25 | 1989-04-14 | Honeywell Inf Systems | Apparato digitale per sistema di recupero di informazioni binarie registrate su supporti magnetici. |
| DE3483265D1 (de) * | 1984-06-25 | 1990-10-25 | Ibm | Mtl-speicherzelle mit inhaerenter mehrfachfaehigkeit. |
| US4633488A (en) * | 1984-11-13 | 1986-12-30 | Digital Equipment Corporation | Phase-locked loop for MFM data recording |
| US4618898A (en) * | 1984-12-20 | 1986-10-21 | Advanced Micro Devices, Inc. | Method and apparatus for reading a disk |
| US4639680A (en) * | 1985-04-12 | 1987-01-27 | Sperry Corporation | Digital phase and frequency detector |
-
1986
- 1986-07-18 US US06/886,615 patent/US4780844A/en not_active Expired - Lifetime
-
1987
- 1987-07-14 AU AU77597/87A patent/AU593678B2/en not_active Ceased
- 1987-07-14 DE DE87905043T patent/DE3788804T2/de not_active Expired - Fee Related
- 1987-07-14 WO PCT/US1987/001624 patent/WO1988000733A1/en active IP Right Grant
- 1987-07-14 KR KR1019880700301A patent/KR950012077B1/ko not_active IP Right Cessation
- 1987-07-14 EP EP87905043A patent/EP0316340B1/en not_active Expired - Lifetime
- 1987-07-14 JP JP62504548A patent/JP2679791B2/ja not_active Expired - Lifetime
- 1987-07-15 IL IL83202A patent/IL83202A/xx unknown
- 1987-07-16 ZA ZA875209A patent/ZA875209B/xx unknown
- 1987-07-17 IN IN555/CAL/87A patent/IN167723B/en unknown
- 1987-07-17 CA CA000542373A patent/CA1283479C/en not_active Expired - Lifetime
-
1988
- 1988-03-18 NO NO881209A patent/NO180698C/no unknown
-
1990
- 1990-09-25 IN IN830/CAL/90A patent/IN168920B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE3788804D1 (de) | 1994-02-24 |
| IL83202A0 (en) | 1987-12-31 |
| US4780844A (en) | 1988-10-25 |
| DE3788804T2 (de) | 1994-04-28 |
| AU7759787A (en) | 1988-02-10 |
| EP0316340A1 (en) | 1989-05-24 |
| IN167723B (nl) | 1990-12-15 |
| IL83202A (en) | 1991-11-21 |
| AU593678B2 (en) | 1990-02-15 |
| NO180698B (no) | 1997-02-17 |
| ZA875209B (en) | 1988-08-31 |
| NO180698C (no) | 1997-05-28 |
| KR950012077B1 (ko) | 1995-10-13 |
| CA1283479C (en) | 1991-04-23 |
| KR880701910A (ko) | 1988-11-07 |
| JPH01503342A (ja) | 1989-11-09 |
| WO1988000733A1 (en) | 1988-01-28 |
| EP0316340B1 (en) | 1994-01-12 |
| NO881209L (no) | 1988-03-18 |
| EP0316340A4 (en) | 1991-07-17 |
| NO881209D0 (no) | 1988-03-18 |
| JP2679791B2 (ja) | 1997-11-19 |