IL97177A - שיטה ליצירת מעגל עוקב - Google Patents

שיטה ליצירת מעגל עוקב

Info

Publication number
IL97177A
IL97177A IL9717791A IL9717791A IL97177A IL 97177 A IL97177 A IL 97177A IL 9717791 A IL9717791 A IL 9717791A IL 9717791 A IL9717791 A IL 9717791A IL 97177 A IL97177 A IL 97177A
Authority
IL
Israel
Prior art keywords
given
tasks
proc
state
circuit
Prior art date
Application number
IL9717791A
Other languages
English (en)
Other versions
IL97177A0 (en
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of IL97177A0 publication Critical patent/IL97177A0/xx
Publication of IL97177A publication Critical patent/IL97177A/he

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3323Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
IL9717791A 1990-03-06 1991-02-07 שיטה ליצירת מעגל עוקב IL97177A (he)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/489,438 US5163016A (en) 1990-03-06 1990-03-06 Analytical development and verification of control-intensive systems

Publications (2)

Publication Number Publication Date
IL97177A0 IL97177A0 (en) 1992-05-25
IL97177A true IL97177A (he) 1995-12-31

Family

ID=23943860

Family Applications (1)

Application Number Title Priority Date Filing Date
IL9717791A IL97177A (he) 1990-03-06 1991-02-07 שיטה ליצירת מעגל עוקב

Country Status (6)

Country Link
US (1) US5163016A (he)
EP (1) EP0445942A3 (he)
JP (1) JPH0760324B2 (he)
KR (1) KR100237090B1 (he)
CA (1) CA2035844C (he)
IL (1) IL97177A (he)

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02234274A (ja) * 1989-03-08 1990-09-17 Hitachi Ltd パイプライン制御論理の自動生成方法及び制御論理
US6185516B1 (en) * 1990-03-06 2001-02-06 Lucent Technologies Inc. Automata-theoretic verification of systems
US5483470A (en) * 1990-03-06 1996-01-09 At&T Corp. Timing verification by successive approximation
FR2679398B1 (fr) * 1991-07-16 1993-10-08 Alcatel Cit Procede d'aide au developpement d'un ensemble d'automates communicants.
US5910958A (en) * 1991-08-14 1999-06-08 Vlsi Technology, Inc. Automatic generation of test vectors for sequential circuits
US5305229A (en) * 1991-09-06 1994-04-19 Bell Communications Research, Inc. Switch-level timing simulation based on two-connected components
US5299206A (en) * 1991-10-24 1994-03-29 Digital Equipment Corporation System and method for analyzing complex sequences in trace arrays using multiple finite automata
FR2685838B1 (fr) * 1991-12-27 1994-02-25 Sgs Thomson Microelectronics Sa Procede pour verifier la conformite a une norme d'une cellule representative d'un circuit dedie a la gestion d'un protocole de communication, et systeme pour sa mise en óoeuvre.
US5491640A (en) * 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
US5710711A (en) * 1992-10-21 1998-01-20 Lucent Technologies Inc. Method and integrated circuit adapted for partial scan testability
US5477474A (en) * 1992-10-29 1995-12-19 Altera Corporation Computer logic simulation with dynamic modeling
WO1994017478A1 (en) * 1993-01-19 1994-08-04 City Of Hope Method for control of chaotic systems
JP2994926B2 (ja) * 1993-10-29 1999-12-27 松下電器産業株式会社 有限状態機械作成方法とパターン照合機械作成方法とこれらを変形する方法および駆動方法
US5446652A (en) * 1993-04-27 1995-08-29 Ventana Systems, Inc. Constraint knowledge in simulation modeling
US5465216A (en) * 1993-06-02 1995-11-07 Intel Corporation Automatic design verification
US5394347A (en) * 1993-07-29 1995-02-28 Digital Equipment Corporation Method and apparatus for generating tests for structures expressed as extended finite state machines
US5659555A (en) * 1993-08-19 1997-08-19 Lucent Technologies Inc. Method and apparatus for testing protocols
US5493505A (en) * 1993-10-28 1996-02-20 Nec Usa, Inc. Initializable asynchronous circuit design
US5623419A (en) * 1994-04-28 1997-04-22 Cadence Design Systems, Inc. Modeling of multi-disciplinary signals
US5513122A (en) * 1994-06-06 1996-04-30 At&T Corp. Method and apparatus for determining the reachable states in a hybrid model state machine
US5623499A (en) * 1994-06-27 1997-04-22 Lucent Technologies Inc. Method and apparatus for generating conformance test data sequences
US5600579A (en) * 1994-07-08 1997-02-04 Apple Computer, Inc. Hardware simulation and design verification system and method
US5535145A (en) * 1995-02-03 1996-07-09 International Business Machines Corporation Delay model abstraction
WO1996024101A1 (en) * 1995-02-03 1996-08-08 A T & T Corp. An automata-theoretic verification of systems
US5706473A (en) * 1995-03-31 1998-01-06 Synopsys, Inc. Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs
US5878407A (en) * 1995-04-18 1999-03-02 International Business Machines Corporation Storage of a graph
US5703798A (en) * 1995-04-25 1997-12-30 Mentor Graphics Corporation Switch level simulation employing dynamic short-circuit ratio
US5831853A (en) * 1995-06-07 1998-11-03 Xerox Corporation Automatic construction of digital controllers/device drivers for electro-mechanical systems using component models
US5848393A (en) * 1995-12-15 1998-12-08 Ncr Corporation "What if . . . " function for simulating operations within a task workflow management system
US5854929A (en) * 1996-03-08 1998-12-29 Interuniversitair Micro-Elektronica Centrum (Imec Vzw) Method of generating code for programmable processors, code generator and application thereof
US5905883A (en) * 1996-04-15 1999-05-18 Sun Microsystems, Inc. Verification system for circuit simulator
EP0806734B1 (en) * 1996-05-06 2003-03-26 Siemens Aktiengesellschaft Method for modelling a process flow according to time constraints on a computer
EP0806735B1 (en) * 1996-05-06 2003-03-26 Siemens Aktiengesellschaft Method for control of a process flow according to a specified behavior with a computer
US5754760A (en) * 1996-05-30 1998-05-19 Integrity Qa Software, Inc. Automatic software testing tool
US6178394B1 (en) * 1996-12-09 2001-01-23 Lucent Technologies Inc. Protocol checking for concurrent systems
IL119914A (en) 1996-12-25 2000-06-29 Emultek Ltd Device for implementing hierarchical state charts and methods and apparatus useful therefor
US6049662A (en) * 1997-01-27 2000-04-11 International Business Machines Corporation System and method for model size reduction of an integrated circuit utilizing net invariants
EP0867820A3 (en) * 1997-03-14 2000-08-16 Interuniversitair Micro-Elektronica Centrum Vzw A design environment and a method for generating an implementable description of a digital system
US6606588B1 (en) 1997-03-14 2003-08-12 Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) Design apparatus and a method for generating an implementable description of a digital system
US6233540B1 (en) 1997-03-14 2001-05-15 Interuniversitair Micro-Elektronica Centrum Design environment and a method for generating an implementable description of a digital system
US5937181A (en) * 1997-03-31 1999-08-10 Lucent Technologies, Inc. Simulation of a process of a concurrent system
US5901073A (en) * 1997-06-06 1999-05-04 Lucent Technologies Inc. Method for detecting errors in models through restriction
US6138266A (en) 1997-06-16 2000-10-24 Tharas Systems Inc. Functional verification of integrated circuit designs
US6295515B1 (en) * 1997-11-03 2001-09-25 Lucent Technologies Inc. Static partial order reduction
US6059837A (en) * 1997-12-30 2000-05-09 Synopsys, Inc. Method and system for automata-based approach to state reachability of interacting extended finite state machines
US6324496B1 (en) * 1998-06-18 2001-11-27 Lucent Technologies Inc. Model checking of hierarchical state machines
US6099575A (en) * 1998-06-23 2000-08-08 Lucent Technologies Inc. Constraint validity checking
US6446241B1 (en) 1999-07-15 2002-09-03 Texas Instruments Incorporated Automated method for testing cache
US6625783B2 (en) * 2000-02-16 2003-09-23 Logic Research Co., Ltd. State machine, semiconductor device using state machine, and method of design thereof
US6606674B1 (en) * 2000-02-24 2003-08-12 Intel Corporation Method and apparatus for reducing circular list's thrashing by detecting the queues' status on a circular linked list
US6708143B1 (en) * 2000-05-22 2004-03-16 Lucent Technologies Inc. Verification coverage method
US6564354B1 (en) * 2000-06-01 2003-05-13 Hewlett Packard Development Company, L.P. Method for translating conditional expressions from a non-verilog hardware description language to verilog hardware description language while preserving structure suitable for logic synthesis
DE60130836T2 (de) * 2000-06-12 2008-07-17 Broadcom Corp., Irvine Architektur und Verfahren zur Kontextumschaltung
US20020032551A1 (en) * 2000-08-07 2002-03-14 Jabari Zakiya Systems and methods for implementing hash algorithms
DE60037429T2 (de) * 2000-10-30 2008-11-27 Siemens Ag Verfahren zur Reduzierung von endlichen Steuerautomaten sowie entsprechendes rechnerlesbares Medium
US7283945B2 (en) * 2000-11-03 2007-10-16 Fujitsu Limited High level verification of software and hardware descriptions by symbolic simulation using assume-guarantee relationships with linear arithmetic assumptions
US6470480B2 (en) * 2000-12-14 2002-10-22 Tharas Systems, Inc. Tracing different states reached by a signal in a functional verification system
US6629297B2 (en) 2000-12-14 2003-09-30 Tharas Systems Inc. Tracing the change of state of a signal in a functional verification system
US6625786B2 (en) 2000-12-14 2003-09-23 Tharas Systems, Inc. Run-time controller in a functional verification system
US6691287B2 (en) 2000-12-14 2004-02-10 Tharas Systems Inc. Functional verification system
US6957178B2 (en) * 2001-10-29 2005-10-18 Honeywell International Inc. Incremental automata verification
US6931615B1 (en) * 2002-06-04 2005-08-16 Cadence Design Systems, Inc. Method and apparatus for identifying a path between source and target states
US7231630B2 (en) * 2002-07-12 2007-06-12 Ensequence Inc. Method and system automatic control of graphical computer application appearance and execution
US7653520B2 (en) * 2002-07-19 2010-01-26 Sri International Method for combining decision procedures with satisfiability solvers
US6778943B2 (en) * 2002-08-13 2004-08-17 Xerox Corporation Systems and methods for distributed fault diagnosis using precompiled finite state automata
US7119577B2 (en) * 2002-08-28 2006-10-10 Cisco Systems, Inc. Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata
US7451143B2 (en) * 2002-08-28 2008-11-11 Cisco Technology, Inc. Programmable rule processing apparatus for conducting high speed contextual searches and characterizations of patterns in data
US20040209676A1 (en) * 2002-11-18 2004-10-21 Takahiro Onishi Gaming machine
US7464254B2 (en) * 2003-01-09 2008-12-09 Cisco Technology, Inc. Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
US7085918B2 (en) * 2003-01-09 2006-08-01 Cisco Systems, Inc. Methods and apparatuses for evaluation of regular expressions of arbitrary size
DE10325513B8 (de) * 2003-06-05 2006-08-03 Onespin Solutions Gmbh Verfahren und Vorrichtung zum Erstellen eines Verhaltensaspekts einer Schaltung zur formalen Verifikation
CN100461186C (zh) * 2003-10-31 2009-02-11 富士通微电子株式会社 验证支持装置、验证支持方法
US7543274B2 (en) 2003-12-22 2009-06-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration System and method for deriving a process-based specification
US7895552B1 (en) * 2004-03-26 2011-02-22 Jasper Design Automation, Inc. Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
JP4691374B2 (ja) * 2004-04-08 2011-06-01 日立オートモティブシステムズ株式会社 設計支援システム
US7581199B1 (en) * 2005-08-08 2009-08-25 National Semiconductor Corporation Use of state nodes for efficient simulation of large digital circuits at the transistor level
US7434183B2 (en) * 2005-08-17 2008-10-07 Cadence Design Systems, Inc. Method and system for validating a hierarchical simulation database
WO2007028226A1 (en) * 2005-09-09 2007-03-15 Ibm Canada Limited - Ibm Canada Limitee Method and system for state machine translation
JP4496205B2 (ja) * 2006-12-18 2010-07-07 日立オートモティブシステムズ株式会社 制御用マイクロコンピュータの検証装置および車載用制御装置
US9082104B2 (en) * 2007-02-02 2015-07-14 Alcatel Lucent Method and apparatus for managing system specifications
US20090093901A1 (en) * 2007-10-03 2009-04-09 International Business Machines Corporation Method and apparatus for using design specifications and measurements on manufactured products in conceptual design models
US9002899B2 (en) * 2008-07-07 2015-04-07 International Business Machines Corporation Method of merging and incremental construction of minimal finite state machines
US8885510B2 (en) 2012-10-09 2014-11-11 Netspeed Systems Heterogeneous channel capacities in an interconnect
US9009648B2 (en) * 2013-01-18 2015-04-14 Netspeed Systems Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification
US9471726B2 (en) 2013-07-25 2016-10-18 Netspeed Systems System level simulation in network on chip architecture
US9473388B2 (en) 2013-08-07 2016-10-18 Netspeed Systems Supporting multicast in NOC interconnect
US9699079B2 (en) 2013-12-30 2017-07-04 Netspeed Systems Streaming bridge design with host interfaces and network on chip (NoC) layers
US9473415B2 (en) 2014-02-20 2016-10-18 Netspeed Systems QoS in a system with end-to-end flow control and QoS aware buffer allocation
GB2526052B (en) * 2014-03-31 2016-04-13 Imagination Tech Ltd Deadlock detection using assertions
US9742630B2 (en) 2014-09-22 2017-08-22 Netspeed Systems Configurable router for a network on chip (NoC)
US9571341B1 (en) 2014-10-01 2017-02-14 Netspeed Systems Clock gating for system-on-chip elements
US9660942B2 (en) 2015-02-03 2017-05-23 Netspeed Systems Automatic buffer sizing for optimal network-on-chip design
US9444702B1 (en) 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9568970B1 (en) 2015-02-12 2017-02-14 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US9928204B2 (en) 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design
US10050843B2 (en) 2015-02-18 2018-08-14 Netspeed Systems Generation of network-on-chip layout based on user specified topological constraints
US10348563B2 (en) 2015-02-18 2019-07-09 Netspeed Systems, Inc. System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
US9864728B2 (en) 2015-05-29 2018-01-09 Netspeed Systems, Inc. Automatic generation of physically aware aggregation/distribution networks
US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US10218580B2 (en) 2015-06-18 2019-02-26 Netspeed Systems Generating physically aware network-on-chip design from a physical system-on-chip specification
US10452124B2 (en) 2016-09-12 2019-10-22 Netspeed Systems, Inc. Systems and methods for facilitating low power on a network-on-chip
US20180159786A1 (en) 2016-12-02 2018-06-07 Netspeed Systems, Inc. Interface virtualization and fast path for network on chip
US10313269B2 (en) 2016-12-26 2019-06-04 Netspeed Systems, Inc. System and method for network on chip construction through machine learning
US10063496B2 (en) 2017-01-10 2018-08-28 Netspeed Systems Inc. Buffer sizing of a NoC through machine learning
US10084725B2 (en) 2017-01-11 2018-09-25 Netspeed Systems, Inc. Extracting features from a NoC for machine learning construction
US10469337B2 (en) 2017-02-01 2019-11-05 Netspeed Systems, Inc. Cost management against requirements for the generation of a NoC
US10298485B2 (en) 2017-02-06 2019-05-21 Netspeed Systems, Inc. Systems and methods for NoC construction
US10983910B2 (en) 2018-02-22 2021-04-20 Netspeed Systems, Inc. Bandwidth weighting mechanism based network-on-chip (NoC) configuration
US10547514B2 (en) 2018-02-22 2020-01-28 Netspeed Systems, Inc. Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
US11144457B2 (en) 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10896476B2 (en) 2018-02-22 2021-01-19 Netspeed Systems, Inc. Repository of integration description of hardware intellectual property for NoC construction and SoC integration
US11176302B2 (en) 2018-02-23 2021-11-16 Netspeed Systems, Inc. System on chip (SoC) builder
US11023377B2 (en) 2018-02-23 2021-06-01 Netspeed Systems, Inc. Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
CN110383232B (zh) * 2019-05-05 2021-03-23 长江存储科技有限责任公司 具有序列处理单元的存储器控制系统
GB2588134B (en) 2019-10-08 2021-12-01 Imagination Tech Ltd Verification of hardware design for data transformation component
US11669613B2 (en) * 2020-05-29 2023-06-06 EnSoft Corp. Method for analyzing and verifying software for safety and security
US11914993B1 (en) * 2021-06-30 2024-02-27 Amazon Technologies, Inc. Example-based synthesis of rules for detecting violations of software coding practices
US12353848B2 (en) * 2023-06-23 2025-07-08 Maplebear Inc. Validating code ownership of software components in a software development system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
US4694411A (en) * 1985-02-04 1987-09-15 Sanders Associates, Inc. Simulation apparatus and method
US4862347A (en) * 1986-04-22 1989-08-29 International Business Machine Corporation System for simulating memory arrays in a logic simulation machine
US4907180A (en) * 1987-05-04 1990-03-06 Hewlett-Packard Company Hardware switch level simulator for MOS circuits
US4965758A (en) * 1988-03-01 1990-10-23 Digital Equipment Corporation Aiding the design of an operation having timing interactions by operating a computer system

Also Published As

Publication number Publication date
KR910017301A (ko) 1991-11-05
JPH04219804A (ja) 1992-08-10
EP0445942A2 (en) 1991-09-11
US5163016A (en) 1992-11-10
EP0445942A3 (en) 1994-09-21
CA2035844C (en) 1995-05-16
JPH0760324B2 (ja) 1995-06-28
KR100237090B1 (ko) 2000-01-15
IL97177A0 (en) 1992-05-25

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