IL183814A0 - Reduction of etch mask feature critical dimensions - Google Patents
Reduction of etch mask feature critical dimensionsInfo
- Publication number
- IL183814A0 IL183814A0 IL183814A IL18381407A IL183814A0 IL 183814 A0 IL183814 A0 IL 183814A0 IL 183814 A IL183814 A IL 183814A IL 18381407 A IL18381407 A IL 18381407A IL 183814 A0 IL183814 A0 IL 183814A0
- Authority
- IL
- Israel
- Prior art keywords
- reduction
- etch mask
- critical dimensions
- mask feature
- feature critical
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0418—Apparatus for fluid treatment for etching
- H10P72/0421—Apparatus for fluid treatment for etching for drying etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70508—Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70541—Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4088—Processes for improving the resolution of the masks
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/016,455 US20060134917A1 (en) | 2004-12-16 | 2004-12-16 | Reduction of etch mask feature critical dimensions |
| PCT/US2005/044505 WO2006065630A2 (en) | 2004-12-16 | 2005-12-06 | Reduction of etch mask feature critical dimensions |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IL183814A0 true IL183814A0 (en) | 2007-09-20 |
Family
ID=36588391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IL183814A IL183814A0 (en) | 2004-12-16 | 2007-06-10 | Reduction of etch mask feature critical dimensions |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20060134917A1 (https=) |
| JP (1) | JP2008524851A (https=) |
| KR (1) | KR20070092282A (https=) |
| CN (1) | CN100543946C (https=) |
| IL (1) | IL183814A0 (https=) |
| TW (1) | TW200641519A (https=) |
| WO (1) | WO2006065630A2 (https=) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7250371B2 (en) * | 2003-08-26 | 2007-07-31 | Lam Research Corporation | Reduction of feature critical dimensions |
| US7491647B2 (en) * | 2005-03-08 | 2009-02-17 | Lam Research Corporation | Etch with striation control |
| JP2007012819A (ja) * | 2005-06-29 | 2007-01-18 | Toshiba Corp | ドライエッチング方法 |
| US7273815B2 (en) * | 2005-08-18 | 2007-09-25 | Lam Research Corporation | Etch features with reduced line edge roughness |
| US7682516B2 (en) * | 2005-10-05 | 2010-03-23 | Lam Research Corporation | Vertical profile fixing |
| US7264743B2 (en) * | 2006-01-23 | 2007-09-04 | Lam Research Corporation | Fin structure formation |
| US7309646B1 (en) * | 2006-10-10 | 2007-12-18 | Lam Research Corporation | De-fluoridation process |
| US20080152823A1 (en) * | 2006-12-20 | 2008-06-26 | Lam Research Corporation | Self-limiting plating method |
| US7794530B2 (en) * | 2006-12-22 | 2010-09-14 | Lam Research Corporation | Electroless deposition of cobalt alloys |
| US7521358B2 (en) * | 2006-12-26 | 2009-04-21 | Lam Research Corporation | Process integration scheme to lower overall dielectric constant in BEoL interconnect structures |
| JP5065787B2 (ja) * | 2007-07-27 | 2012-11-07 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置、および記憶媒体 |
| JP2010041028A (ja) | 2008-07-11 | 2010-02-18 | Tokyo Electron Ltd | 基板処理方法 |
| US7772122B2 (en) * | 2008-09-18 | 2010-08-10 | Lam Research Corporation | Sidewall forming processes |
| US8394722B2 (en) * | 2008-11-03 | 2013-03-12 | Lam Research Corporation | Bi-layer, tri-layer mask CD control |
| US9601349B2 (en) | 2009-02-17 | 2017-03-21 | Macronix International Co., Ltd. | Etching method |
| US20120094494A1 (en) * | 2010-10-14 | 2012-04-19 | Macronix International Co., Ltd. | Methods for etching multi-layer hardmasks |
| US8304262B2 (en) * | 2011-02-17 | 2012-11-06 | Lam Research Corporation | Wiggling control for pseudo-hardmask |
| CN103000505B (zh) * | 2011-09-16 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 多栅器件的形成方法 |
| CN104157556B (zh) * | 2013-05-15 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | 金属硬掩模开口刻蚀方法 |
| CN103337476A (zh) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | 一种减小铜互连沟槽关键尺寸的方法 |
| CN103346119A (zh) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | 一种减小铜互连沟槽关键尺寸的方法 |
| GB201322931D0 (en) | 2013-12-23 | 2014-02-12 | Spts Technologies Ltd | Method of etching |
| US9324578B2 (en) | 2014-01-29 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company Limited | Hard mask reshaping |
| CN104241100A (zh) * | 2014-09-23 | 2014-12-24 | 上海华力微电子有限公司 | 小尺寸图形的制作方法 |
| US10037890B2 (en) * | 2016-10-11 | 2018-07-31 | Lam Research Corporation | Method for selectively etching with reduced aspect ratio dependence |
| KR102313431B1 (ko) | 2016-11-21 | 2021-10-18 | 나노스트링 테크놀로지스, 인크. | 화학적 조성물 및 이것을 사용하는 방법 |
| US10734238B2 (en) * | 2017-11-21 | 2020-08-04 | Lam Research Corporation | Atomic layer deposition and etch in a single plasma chamber for critical dimension control |
| JP7145031B2 (ja) * | 2017-12-25 | 2022-09-30 | 東京エレクトロン株式会社 | 基板を処理する方法、プラズマ処理装置、及び基板処理装置 |
| CN110010464B (zh) * | 2017-12-25 | 2023-07-14 | 东京毅力科创株式会社 | 处理基板的方法 |
| AU2019271028B2 (en) | 2018-05-14 | 2025-09-18 | Bruker Spatial Biology, Inc. | Chemical compositions and methods of using same |
| US10818508B2 (en) * | 2018-10-17 | 2020-10-27 | Nanya Technology Corporation | Semiconductor structure and method for preparing the same |
| JP2021174902A (ja) * | 2020-04-27 | 2021-11-01 | 東京エレクトロン株式会社 | 処理方法及び基板処理装置 |
| CN116031203B (zh) * | 2022-11-30 | 2026-04-03 | 联合微电子中心有限责任公司 | 半导体器件接触孔的制备方法 |
| US12224160B2 (en) | 2023-05-23 | 2025-02-11 | Tokyo Electron Limited | Topographic selective deposition |
| CN120824255B (zh) * | 2025-09-16 | 2026-02-24 | 芯联集成电路制造股份有限公司 | 一种半导体器件及其制造方法 |
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| JPS5378170A (en) * | 1976-12-22 | 1978-07-11 | Toshiba Corp | Continuous processor for gas plasma etching |
| US4871630A (en) * | 1986-10-28 | 1989-10-03 | International Business Machines Corporation | Mask using lithographic image size reduction |
| US5013680A (en) * | 1990-07-18 | 1991-05-07 | Micron Technology, Inc. | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography |
| US5273609A (en) * | 1990-09-12 | 1993-12-28 | Texas Instruments Incorporated | Method and apparatus for time-division plasma chopping in a multi-channel plasma processing equipment |
| DE4241045C1 (de) * | 1992-12-05 | 1994-05-26 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silicium |
| US5296410A (en) * | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
| JPH0997833A (ja) * | 1995-07-22 | 1997-04-08 | Ricoh Co Ltd | 半導体装置とその製造方法 |
| US5879853A (en) * | 1996-01-18 | 1999-03-09 | Kabushiki Kaisha Toshiba | Top antireflective coating material and its process for DUV and VUV lithography systems |
| US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
| GB9616225D0 (en) * | 1996-08-01 | 1996-09-11 | Surface Tech Sys Ltd | Method of surface treatment of semiconductor substrates |
| US5895740A (en) * | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
| US5766998A (en) * | 1996-12-27 | 1998-06-16 | Vanguard International Semiconductor Corporation | Method for fabricating narrow channel field effect transistors having titanium shallow junctions |
| US5907775A (en) * | 1997-04-11 | 1999-05-25 | Vanguard International Semiconductor Corporation | Non-volatile memory device with high gate coupling ratio and manufacturing process therefor |
| US6187685B1 (en) * | 1997-08-01 | 2001-02-13 | Surface Technology Systems Limited | Method and apparatus for etching a substrate |
| FR2777145B1 (fr) * | 1998-04-02 | 2000-04-28 | Alsthom Cge Alcatel | Modulateur multiporteuses large bande et procede de programmation correspondant |
| US6218288B1 (en) * | 1998-05-11 | 2001-04-17 | Micron Technology, Inc. | Multiple step methods for forming conformal layers |
| US6100014A (en) * | 1998-11-24 | 2000-08-08 | United Microelectronics Corp. | Method of forming an opening in a dielectric layer through a photoresist layer with silylated sidewall spacers |
| US6162733A (en) * | 1999-01-15 | 2000-12-19 | Lucent Technologies Inc. | Method for removing contaminants from integrated circuits |
| US6368974B1 (en) * | 1999-08-02 | 2002-04-09 | United Microelectronics Corp. | Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching |
| US6905800B1 (en) * | 2000-11-21 | 2005-06-14 | Stephen Yuen | Etching a substrate in a process zone |
| US6656282B2 (en) * | 2001-10-11 | 2003-12-02 | Moohan Co., Ltd. | Atomic layer deposition apparatus and process using remote plasma |
| US6750150B2 (en) * | 2001-10-18 | 2004-06-15 | Macronix International Co., Ltd. | Method for reducing dimensions between patterns on a photoresist |
| KR100448714B1 (ko) * | 2002-04-24 | 2004-09-13 | 삼성전자주식회사 | 다층 나노라미네이트 구조를 갖는 반도체 장치의 절연막및 그의 형성방법 |
| US7105442B2 (en) * | 2002-05-22 | 2006-09-12 | Applied Materials, Inc. | Ashable layers for reducing critical dimensions of integrated circuit features |
| US20030235998A1 (en) * | 2002-06-24 | 2003-12-25 | Ming-Chung Liang | Method for eliminating standing waves in a photoresist profile |
| US20040010769A1 (en) * | 2002-07-12 | 2004-01-15 | Macronix International Co., Ltd. | Method for reducing a pitch of a procedure |
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| US7169695B2 (en) * | 2002-10-11 | 2007-01-30 | Lam Research Corporation | Method for forming a dual damascene structure |
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| US6829056B1 (en) * | 2003-08-21 | 2004-12-07 | Michael Barnes | Monitoring dimensions of features at different locations in the processing of substrates |
| US7250371B2 (en) * | 2003-08-26 | 2007-07-31 | Lam Research Corporation | Reduction of feature critical dimensions |
| US7012027B2 (en) * | 2004-01-27 | 2006-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Zirconium oxide and hafnium oxide etching using halogen containing chemicals |
| US6864184B1 (en) * | 2004-02-05 | 2005-03-08 | Advanced Micro Devices, Inc. | Method for reducing critical dimension attainable via the use of an organic conforming layer |
| US20060032833A1 (en) * | 2004-08-10 | 2006-02-16 | Applied Materials, Inc. | Encapsulation of post-etch halogenic residue |
| US7723235B2 (en) * | 2004-09-17 | 2010-05-25 | Renesas Technology Corp. | Method for smoothing a resist pattern prior to etching a layer using the resist pattern |
| US7053003B2 (en) * | 2004-10-27 | 2006-05-30 | Lam Research Corporation | Photoresist conditioning with hydrogen ramping |
| US7282441B2 (en) * | 2004-11-10 | 2007-10-16 | International Business Machines Corporation | De-fluorination after via etch to preserve passivation |
| US20070026682A1 (en) * | 2005-02-10 | 2007-02-01 | Hochberg Michael J | Method for advanced time-multiplexed etching |
| US7241683B2 (en) * | 2005-03-08 | 2007-07-10 | Lam Research Corporation | Stabilized photoresist structure for etching process |
| US7049209B1 (en) * | 2005-04-01 | 2006-05-23 | International Business Machines Corporation | De-fluorination of wafer surface and related structure |
| KR100810303B1 (ko) * | 2005-04-28 | 2008-03-06 | 삼성전자주식회사 | 휴대단말기의 데이터 표시 및 전송방법 |
| US7695632B2 (en) * | 2005-05-31 | 2010-04-13 | Lam Research Corporation | Critical dimension reduction and roughness control |
| US7273815B2 (en) * | 2005-08-18 | 2007-09-25 | Lam Research Corporation | Etch features with reduced line edge roughness |
-
2004
- 2004-12-16 US US11/016,455 patent/US20060134917A1/en not_active Abandoned
-
2005
- 2005-12-06 WO PCT/US2005/044505 patent/WO2006065630A2/en not_active Ceased
- 2005-12-06 KR KR1020077016328A patent/KR20070092282A/ko not_active Ceased
- 2005-12-06 CN CNB2005800479848A patent/CN100543946C/zh not_active Expired - Fee Related
- 2005-12-06 JP JP2007546765A patent/JP2008524851A/ja not_active Withdrawn
- 2005-12-14 TW TW094144362A patent/TW200641519A/zh unknown
-
2007
- 2007-06-10 IL IL183814A patent/IL183814A0/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US20060134917A1 (en) | 2006-06-22 |
| WO2006065630A2 (en) | 2006-06-22 |
| WO2006065630A3 (en) | 2007-04-12 |
| KR20070092282A (ko) | 2007-09-12 |
| TW200641519A (en) | 2006-12-01 |
| CN100543946C (zh) | 2009-09-23 |
| JP2008524851A (ja) | 2008-07-10 |
| CN101116177A (zh) | 2008-01-30 |
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