IES84232Y1 - Phase locked loop with a switch capacitor resistor in the loop filter - Google Patents

Abstract

ABSTRACT A filter couples an output of a phase detector to an input of a voltage controlled oscillator. The filter has a first capacitor and a switch capacitor resistor that is in series with the first capacitor, between the first capacitor and the output of the phase detector. The switch capacitor resistor is to display a resistance that is obtained by switching back and forth a second capacitor to the first capacitor and to the phase detector output. Other embodiments are also described and claimed. 2006) IE 050 369 IItcI.<..____ HOSL 7/o6 PHASE LOCKED LOOP WITH A SWITCH CAPACITOR RESISTOR IN THE LOOP FILTER am to PUBLIC msvrcrum Main sections 29 AID RULE 23 Jill no. of §.‘..S.§*°<* Background [0002] Phased locked loop circuits (PLLS) are typically used whenever a periodic signal is to be generated whose frequency is an accurate multiple of the frequency of a very stable and low noise reference signal. A PLL is also used where the phase of an output signal has to track the phase of the reference signal. Applications include the generation of local oscillator signals in radio receivers are transmitters, as well as in clock recovery of digital communication systems . [0003] The PLL is a closed loop feedback control system that continuously tries to reduce the error between the frequency or phase of its output signal and that of the reference. A typical PLL has what is referred to as a loop filter that connects a phase detector to a voltage controlled oscillator (VCO). The phase detector responds to the phase error between the reference and a feedback signal derived from the output, by making adjustments to a voltage signal in proportion to the phase error. Rather than directly applying the voltage signal to the input of the VCO, however, the signal is conditioned by the filter to produce the control voltage that adjusts the output frequency of the VCO. The filter is designed to help maintain the control loop stable, so that the loop does not enter an oscillatory condition. The filter may be viewed as smoothing out the input voltage to the VCO. The input Voltage to the VCO adjusts the output frequency until a, for example, reference clock edge and a feedback clock edge are aligned. [0004] In certain types of PLLs, stabilization using the loop filter is typically achieved by including a resistor in series with a capacitor, which together are in parallel with the output of the phase detector. Circuit designers have been faced with the challenge of reducing the size of such a PLL, l

Description

PHASE LOCKED LOOP WITH A SWITCH CAPACITOR RESISTOR IN THE LOOP FILTER This application claims the benefit of the earlier filing date of U.S.

Provisional Application Serial Number 60/633,232 filed December 2, 2004.

Background Phased locked loop circuits (PLLs) are typically used whenever a periodic signal is to be generated whose frequency is an accurate multiple of the frequency of a very stable and low noise reference signal. A PLL is also used where the phase of an output signal has to track the phase of the reference signal. Applications include the generation of local oscillator signals in radio receivers are transmitters, as well as in clock recovery of digital communication systems.

The PLL is a closed loop feedback control system that continuously tries to reduce the error between the frequency or phase of its output signal and that of the reference. A typical PLL has what is referred to as a loop filter that connects a phase detector to a voltage controlled oscillator (VCO). The phase detector responds to the phase error between the reference and a feedback signal derived from the output, by making adjustments to a voltage signal in proportion to the phase error. Rather than directly applying the voltage signal to the input of the VCO, however, the signal is conditioned by the filter to produce the control voltage that adjusts the output frequency of the VCO. The filter is designed to help maintain the control loop stable, so that the loop does not enter an oscillatory condition. The filter may be viewed as smoothing out the input voltage to the VCO. The input voltage to the VCO adjusts the output frequency until a, for example, reference clock edge and a feedback clock edge are aligned.

In certain types of PLLs, stabilization using the loop filter is typically achieved by including a resistor in series with a capacitor, which together are in parallel with the output of the phase detector. Circuit designers have been faced with the challenge of reducing the size of such a PLL, particularly where it is implemented by advanced, small feature size integrated circuit manufacturing techniques.

BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to "an" embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one.

Fig. 1 shows a simplified schematic diagram of part of a PLL that features a loop filter with a switch capacitor resistor.

Fig. 2 is a block diagram of a PLL featuring a filter with a switch capacitor resistor.

Fig. 3 shows a conventional loop filter with parallel capacitors and a passive resistor.

Fig. 4 shows a plot of the open loop transfer function of an example PLL.

Fig. 5 shows an example modified loop filter, according to an embodiment of the invention.

Fig. 6 shows an implementation of a switch capacitor resistor for the loop filter.

DETAILED DESCRIPTION According to an embodiment of the invention, a modification to the loop filter is described which achieves significant area reduction in the loop filter, without a degradation in performance that would normally be associated with the area reduction. Another embodiment of the invention lies in modifying the loop filter to make it possible for the filter to automatically adjust its characteristics appropriately, in response to a wide range of PLL input reference frequencies. A simplified schematic diagram of an embodiment of the invention is shown in Fig. 1. A loop filter 106 that is coupled between a phase detector (PD) 104 and VCO 108 is modified so that a switching capacitor circuit 109 is in series with the capacitor C1, between C1 and the input of the VCO 108. The switching capacitor circuit 109 has a second capacitor C2 that is coupled to the power return node at one end, and at its other end is alternatively coupled to C1 in one state and the VCO input in another state.

This may be achieved by a pair of solid state switches as shown, that are controlled by non-overlapping clock signals phi and phi’. These non- overlapping clock signals may be generated by a clock generator 110 that derives from the input reference signal REF. Operation of the circuit in Fig. 1 may be understood following a description below of a basic PLL and its associated control loop, as well as appreciating the significance of the loop filter in the control loop.

The basic building blocks of an example PLL, without input and feedback frequency dividers, can be seen in Fig. 2. This PLL works in the following manner. A phase frequency detector (PFD) 202 detects the phase error between its input edges (REF & FB) and produces voltage pulses, the widths of which are proportional to the phase error. These pulses are converted to electrical current pulses by a charge pump (CP) 206. The electrical current pulses are then conditioned by the filter 109 to produce a control voltage (Vcmm). This voltage adjusts the output frequency of the voltage- controlled oscillator (V CO) 108 until the reference edge (REF) and the fed-back clock edge (FB) are aligned.

The PLL as described above is a closed loop system. It has a number of constraints. These include stability and bandwidth requirements. By examining its open-loop transfer function, some of a PLLs stability concerns and how these are affected by the PLL components can be appreciated. The transfer function which relates the input to output phase (<|>i to tho) of the transfer function may be £1:-If’-xZ(s)x£K-Q (1) Q 2% s In this expression, Ip is the charge pump current, Kvco is the frequency sensitivity of the VCO 108 and Z(s) is the impedance of the filter 109.

For a conventional, second order passive filter, as shown in Fig. 3, the impedance of the loop filter 109 may be given by sRCS+1 SCPCSR C,,+CS Z(s) = (2) (C, +CS)s(1+ Based on Equation (1) and (2) above, it can be seen that there is a zero at 1 / RC5 and a pole at (C1=+ Cs)/ (Cp CsR), or because Cs >> Cp the pole is approximated by 1/ RCP.

A graphical plot of a typical transfer function for a PLL is shown in Fig. 4, for an input reference frequency of one MHz and an output of 200 MHz. As an example, the parameters for such a system might be Table D Ip R Cs Cp Kvco 10microA 22Kohms 350pF 15pF 500MHz / V From Fig. 4, the Bandwidth (BW) of the system may be set at 100 KI-Iz, which is ten times lower than the input frequency for the stability of the system. This example ratio of 10:1 allows for the fact that the PLL control loop may be viewed as a sampled data system with the phase error being sampled at the reference frequency. Thus the system response time (related to the reciprocal of the BW) should be somewhat less than the reference frequency to avoid instability due to under sampling.

According to an embodiment of the invention, the size of the filter may be reduced by realizing that its size is dominated by the size of the capacitor C5 (Fig. 3). To reduce the size of the filter, the size of the capacitor C5 is reduced.

However, this also decreases the capacitance exhibited by C5, so that to maintain the position of the important pole and zero described above, it may be necessary to increase the value of the filter resistor R. To maintain a similar magnitude response in the transfer function (Fig. 4), the current of the charge pump 206 may also need to be scaled down. Following this thinking, a potential system which has a substantially identical transfer function to the above may be given by Table G Ip R Cs Cp Kvco 1microA 220I The system above reduces the area of the loop filter by a factor of 10, however, it has a drawback in that the increased filter resistance at 220KQ generates a relatively large amount of thermal noise, which directly modulates the sensitive input node of the VCO 108 and thus degrades the phase noise of the PLL.

According to an embodiment of the invention, the modification to the filter 106, which maintains its small size, is to replace the resistor R with a switching capacitor circuit 109, as shown in Fig. 1 (where C1 may be viewed as being analogous to C5 of Fig. 3). In other words, the resistor R is replaced with a switch capacitor resistor that is preferably composed of a pair of transistor switches that share a node with the capacitor C2 referenced to a power supply return node (e. g., ground) as shown in Fig. 2. Note that the filter 106 may also be equipped with a further capacitor Cp that is also in parallel with the output of the phase detector 104 or the input of the VCO 108.

The effective resistance of the switching capacitor circuit 109, redrawn in Fig. 5, is given by R=Ts/ C2 where T5 is the period of the switching clock phi, phi’. Note that such a switch capacitor resistor does not generate the same level of noise that a linear resistor of the same value would typically generate, and therefore helps maintain the performance of the PLL.

In yet a further embodiment of the invention, the switch capacitor resistor is clocked from a derivative of the reference clock. This allows the pole and zero of the open loop transfer function to be moved along with the reference clock, and thus positions the pole and zero appropriately for a range of reference frequencies (to maintain a desirable phase margin for stability). In other words, the frequency response of the loop filter is automatically tuned for a wide range of reference frequencies.

Fig. 6 shows a simplified schematic of another embodiment of the loop filter, featuring a selectable "linear" resistor RL in parallel with the switch capacitor resistor. The term linear is used here merely to distinguish the " switching" aspect of the switch capacitor resistor. The linear (or "normal") resistor RL may be implemented by, for example, a passive device or by properly biased transistor. In such a loop filter, either the switch cap resistor or alternatively the linear resistor is selected to be in series with the capacitor C1.

This may be achieved by turning off the switches (normally clocked by phi and phi’), and switching in the linear resistor R1. as shown. A purpose for having this option is as follows. At relatively high reference frequencies, the time constant of the switching in the switch capacitor resistor becomes comparable to the bandwidth of the PLL loop. Accordingly, there is, in that case, an increased risk of destabilizing the loop. At the same time, at relatively high reference frequencies, a linear resistor RL in series with C1 works well as part of the loop filter, because the resistance needed in series with C1 is relative low and so thermal noise from such a resistor is not as much of a problem. For example, there may be two reference frequency ranges defined, one up to 50 MHz and another beyond. Up to 50 MHZ it is the switch capacitor resistor that is used. Beyond 50 MHz, the switch cap resistor is replaced with a combination of one or more linear resistors.

The embodiments of the PLL described above may be implemented in a complementary metal oxide semiconductor (CMOS) fabrication process. The passive capacitors would be MOS devices while the switching circuits would include CMOS transmission gates. Other microelectronic fabrication technologies may also be used to implement the PLL.

The PLL designs described above may be embodied in an electronic design automation / computer aided design file format that is popular in the industry for transferring or archiving a mask drawing and layout design of an integrated circuit. An example is a GDS file that describes the physical layout and identifies the components of the PLL and its loop filter for a particular fabrication technology. The GDS file may be stored in a machine—readable medium, such as a CDROM or a distributed medium such as an Internet transfer. Such a medium would have stored therein instructions which, when executed by a processor, describe the PLL circuit design and its loop filter according to any of the embodiments mentioned above.

The invention is not limited to the specific embodiments described above. For example, the switch capacitor resistor may be implemented with more than one passive capacitor that is switched to yield the desired effective resistance and / or open loop transfer function. In another alternative, more than one linear resistor may be coupled in parallel with the switch capacitor resistor (e. g., a selectable bank of resistors), and more than two reference frequency ranges can be defined for which a resistance selection can be made.

Accordingly, other embodiments are within the scope of the claims.

Claims (5)

CLAIMS What is claimed is:

1. A phase-locked loop circuit, comprising: a voltage controlled oscillator (VCO); a phase detector to respond to a phase difference between a reference signal and a feedback signal derived from an output of the VCO; and a loop filter that couples an output of the phase detector to an input of the VCO, the loop filter having (a) a first capacitor coupled to a power return node, and (b) a switching capacitor circuit in series with the first capacitor between the first capacitor and the input of the VCO, the switching capacitor circuit having (a) a second capacitor coupled to the power return node, and (b) a switching circuit that alternatively couples the second capacitor to the first capacitor in one state and the VCO input in another state.

2. The circuit of claim 1 wherein the phase detector comprises a phase- frequency detector (PFD) to compare the reference and feedback signals, and a charge pump controlled by a pair of outputs of the PFD, wherein the phase detector output is an output of the charge pump.

3. The circuit of claim 2 wherein the loop filter further comprises a third capacitor coupled in parallel with the output of the phase detector.

4. A method for operating a feedback loop, comprising: generating an oscillating output signal in accordance with a voltage signal; detecting a phase difference between a reference signal and a feedback signal, the feedback signal having been derived from the output signal; updating the voltage signal according to the detected phase difference; and 10 filtering the voltage signal using a parallel-coupled filter having (a) a first capacitor, and (b) a switching capacitor circuit in series with the first capacitor, wherein the switching capacitor circuit has (a) a second capacitor, and (b) a switching circuit that alternatively couples the second capacitor to the first capacitor in one state and the voltage signal in another state.

5. A machine-readable medium having stored therein instructions which, when executed by a processor, describe a phase-locked loop (PLL) circuit design that comprises: a voltage controlled oscillator (VCO); a phase detector; and a filter that couples an output of the phase detector to an input of the VCO, the filter having a first capacitor and a switch-capacitor resistor that is in series with the first capacitor between the first capacitor and the output of the phase detector, the switch-capacitor resistor to display a resistance that is obtained by switching back and forth a second capacitor to the first capacitor and to the phase detector output. 584232