ID27920A - Modul khusus penerapan dengan upaya modifikasi yang berkurang - Google Patents
Modul khusus penerapan dengan upaya modifikasi yang berkurangInfo
- Publication number
- ID27920A ID27920A IDW20010702A ID20010702A ID27920A ID 27920 A ID27920 A ID 27920A ID W20010702 A IDW20010702 A ID W20010702A ID 20010702 A ID20010702 A ID 20010702A ID 27920 A ID27920 A ID 27920A
- Authority
- ID
- Indonesia
- Prior art keywords
- application
- special module
- reduce modification
- modification efforts
- efforts
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
- G01R31/318538—Topological or mechanical aspects
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19844731 | 1998-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
ID27920A true ID27920A (id) | 2001-05-03 |
Family
ID=7882710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IDW20010702A ID27920A (id) | 1998-09-29 | 1999-09-01 | Modul khusus penerapan dengan upaya modifikasi yang berkurang |
Country Status (5)
Country | Link |
---|---|
US (1) | US6742150B1 (id) |
CN (1) | CN1145040C (id) |
DE (1) | DE19981944D2 (id) |
ID (1) | ID27920A (id) |
WO (1) | WO2000019223A1 (id) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7174340B1 (en) * | 2000-08-17 | 2007-02-06 | Oracle International Corporation | Interval-based adjustment data includes computing an adjustment value from the data for a pending adjustment in response to retrieval of an adjusted data value from a database |
US9201117B2 (en) | 2013-05-06 | 2015-12-01 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5412260A (en) * | 1991-05-03 | 1995-05-02 | Lattice Semiconductor Corporation | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device |
JP2616410B2 (ja) | 1993-11-29 | 1997-06-04 | 日本電気株式会社 | バウンダリスキャン用回路を具備する半導体集積回路 |
US5544174A (en) | 1994-03-17 | 1996-08-06 | The United States Of America As Represented By The Secretary Of The Air Force | Programmable boundary scan and input output parameter device for testing integrated circuits |
JP3698166B2 (ja) | 1995-06-07 | 2005-09-21 | サムスン エレクトロニクス カンパニー,リミテッド | Jtagを用してasic内のメガセルを試験する方法と装置 |
-
1999
- 1999-09-01 WO PCT/DE1999/002733 patent/WO2000019223A1/de active Application Filing
- 1999-09-01 US US09/806,105 patent/US6742150B1/en not_active Expired - Fee Related
- 1999-09-01 ID IDW20010702A patent/ID27920A/id unknown
- 1999-09-01 CN CNB998115479A patent/CN1145040C/zh not_active Expired - Fee Related
- 1999-09-01 DE DE19981944T patent/DE19981944D2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2000019223A1 (de) | 2000-04-06 |
DE19981944D2 (de) | 2002-08-29 |
CN1145040C (zh) | 2004-04-07 |
CN1320215A (zh) | 2001-10-31 |
US6742150B1 (en) | 2004-05-25 |
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