ID24794A - Metode pelekatan barang-barang penyalur panas ke bidang penampang cetakan dan peralatan yang dibentuk dengan cara itu - Google Patents

Metode pelekatan barang-barang penyalur panas ke bidang penampang cetakan dan peralatan yang dibentuk dengan cara itu

Info

Publication number
ID24794A
ID24794A IDP991157D ID991157D ID24794A ID 24794 A ID24794 A ID 24794A ID P991157 D IDP991157 D ID P991157D ID 991157 D ID991157 D ID 991157D ID 24794 A ID24794 A ID 24794A
Authority
ID
Indonesia
Prior art keywords
plasma
film
heat
adhesive
bonding
Prior art date
Application number
IDP991157D
Other languages
English (en)
Inventor
Frank D Egitto
Michael A Gaynes
Ramesh Kodnani
Luis J Mationso
Mark V Pierson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of ID24794A publication Critical patent/ID24794A/id

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C59/00—Surface shaping of articles, e.g. embossing; Apparatus therefor
    • B29C59/14—Surface shaping of articles, e.g. embossing; Apparatus therefor by plasma treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Adhesives Or Adhesive Processes (AREA)
IDP991157D 1999-02-11 1999-12-20 Metode pelekatan barang-barang penyalur panas ke bidang penampang cetakan dan peralatan yang dibentuk dengan cara itu ID24794A (id)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/248,341 US6206997B1 (en) 1999-02-11 1999-02-11 Method for bonding heat sinks to overmolds and device formed thereby

Publications (1)

Publication Number Publication Date
ID24794A true ID24794A (id) 2000-08-16

Family

ID=22938686

Family Applications (1)

Application Number Title Priority Date Filing Date
IDP991157D ID24794A (id) 1999-02-11 1999-12-20 Metode pelekatan barang-barang penyalur panas ke bidang penampang cetakan dan peralatan yang dibentuk dengan cara itu

Country Status (2)

Country Link
US (4) US6206997B1 (id)
ID (1) ID24794A (id)

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WO1998039053A1 (en) * 1997-03-06 1998-09-11 Scimed Life Systems, Inc. Distal protection device and method
US6206997B1 (en) * 1999-02-11 2001-03-27 International Business Machines Corporation Method for bonding heat sinks to overmolds and device formed thereby
US6893523B2 (en) * 1999-02-11 2005-05-17 International Business Machines Corporation Method for bonding heat sinks to overmold material
US6963141B2 (en) * 1999-12-31 2005-11-08 Jung-Yu Lee Semiconductor package for efficient heat spreading
TW490820B (en) * 2000-10-04 2002-06-11 Advanced Semiconductor Eng Heat dissipation enhanced ball grid array package
US20030030139A1 (en) * 2001-06-26 2003-02-13 Marcos Karnezos Integral heatsink plastic ball grid array
US7015072B2 (en) 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
JP3786097B2 (ja) * 2002-03-25 2006-06-14 セイコーエプソン株式会社 圧電デバイスの蓋封止方法及び圧電デバイスの製造方法並びに圧電デバイスの蓋封止装置
TW549592U (en) * 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US20040119158A1 (en) * 2002-12-19 2004-06-24 Tatt Koay Hean Thermally enhanced package for an integrated circuit
US7332797B2 (en) * 2003-06-30 2008-02-19 Intel Corporation Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold
JP2005109068A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体装置およびその製造方法
TWI237363B (en) * 2003-12-31 2005-08-01 Advanced Semiconductor Eng Semiconductor package
US7329948B2 (en) * 2004-10-15 2008-02-12 International Business Machines Corporation Microelectronic devices and methods
US7259580B2 (en) * 2005-02-22 2007-08-21 International Business Machines Corporation Method and apparatus for temporary thermal coupling of an electronic device to a heat sink during test
US7566591B2 (en) * 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US20110139364A1 (en) * 2009-12-16 2011-06-16 Matienzo Luis J Chemical modification of chromate conversion coated aluminum work pieces
KR20120079325A (ko) 2011-01-04 2012-07-12 페어차일드코리아반도체 주식회사 반도체 패키지 및 그 제조방법
KR20130089473A (ko) * 2012-02-02 2013-08-12 삼성전자주식회사 반도체 패키지
KR102031731B1 (ko) 2012-12-18 2019-10-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법
KR101625264B1 (ko) * 2013-05-30 2016-05-27 제일모직주식회사 방열 접착 필름, 이를 포함하는 반도체 장치 및 상기 장치의 제조 방법
DE102013220880B4 (de) * 2013-10-15 2016-08-18 Infineon Technologies Ag Elektronisches Halbleitergehäuse mit einer elektrisch isolierenden, thermischen Schnittstellenstruktur auf einer Diskontinuität einer Verkapselungsstruktur sowie ein Herstellungsverfahren dafür und eine elektronische Anordung dies aufweisend
DE102015118245A1 (de) * 2015-10-26 2017-04-27 Infineon Technologies Austria Ag Thermisches Schnittstellenmaterial mit definierten thermischen, mechanischen und elektrischen Eigenschaften
US9653411B1 (en) * 2015-12-18 2017-05-16 Intel Corporation Electronic package that includes fine powder coating
DE102016122251A1 (de) * 2016-11-18 2018-05-24 Infineon Technologies Austria Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelement
KR102420589B1 (ko) 2017-12-04 2022-07-13 삼성전자주식회사 히트 싱크를 가지는 반도체 패키지
US10923412B2 (en) * 2018-08-10 2021-02-16 Cerebras Systems Inc. Apparatuses and methods for implementing a sliding thermal interface between substrates with varying coefficients of thermal expansion

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Also Published As

Publication number Publication date
US6719871B2 (en) 2004-04-13
US20010001183A1 (en) 2001-05-17
US6770968B2 (en) 2004-08-03
US20020005245A1 (en) 2002-01-17
US20030123229A1 (en) 2003-07-03
US6576996B2 (en) 2003-06-10
US6206997B1 (en) 2001-03-27

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