ID19414A - Kemasan sirkuit terpadu - Google Patents
Kemasan sirkuit terpaduInfo
- Publication number
- ID19414A ID19414A IDP973071A ID973071A ID19414A ID 19414 A ID19414 A ID 19414A ID P973071 A IDP973071 A ID P973071A ID 973071 A ID973071 A ID 973071A ID 19414 A ID19414 A ID 19414A
- Authority
- ID
- Indonesia
- Prior art keywords
- integrated circuit
- circuit packaging
- packaging
- integrated
- circuit
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/709,728 US6043559A (en) | 1996-09-09 | 1996-09-09 | Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses |
Publications (1)
Publication Number | Publication Date |
---|---|
ID19414A true ID19414A (id) | 1998-07-09 |
Family
ID=24851095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IDP973071A ID19414A (id) | 1996-09-09 | 1997-09-03 | Kemasan sirkuit terpadu |
Country Status (5)
Country | Link |
---|---|
US (2) | US6043559A (id) |
AU (1) | AU3509397A (id) |
ID (1) | ID19414A (id) |
MY (1) | MY116965A (id) |
WO (1) | WO1998010630A1 (id) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278618B1 (en) * | 1999-07-23 | 2001-08-21 | National Semiconductor Corporation | Substrate strips for use in integrated circuit packaging |
US7098084B2 (en) * | 2000-03-08 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6515354B1 (en) * | 2000-06-28 | 2003-02-04 | Advanced Micro Devices, Inc. | Micro-BGA beam lead connection with cantilevered beam leads |
US6790760B1 (en) * | 2000-07-21 | 2004-09-14 | Agere Systems Inc. | Method of manufacturing an integrated circuit package |
US6577508B1 (en) | 2000-08-10 | 2003-06-10 | Nortel Networks Limited | Multilayer circuit board |
US6538336B1 (en) | 2000-11-14 | 2003-03-25 | Rambus Inc. | Wirebond assembly for high-speed integrated circuits |
US6790710B2 (en) * | 2002-01-31 | 2004-09-14 | Asat Limited | Method of manufacturing an integrated circuit package |
US20030048624A1 (en) * | 2001-08-22 | 2003-03-13 | Tessera, Inc. | Low-height multi-component assemblies |
US6982485B1 (en) * | 2002-02-13 | 2006-01-03 | Amkor Technology, Inc. | Stacking structure for semiconductor chips and a semiconductor package using it |
US6806563B2 (en) * | 2003-03-20 | 2004-10-19 | International Business Machines Corporation | Composite capacitor and stiffener for chip carrier |
TW566674U (en) * | 2003-04-17 | 2003-12-11 | Advanced Semiconductor Eng | Package substrate for improving electrical performance |
US7116557B1 (en) * | 2003-05-23 | 2006-10-03 | Sti Electronics, Inc. | Imbedded component integrated circuit assembly and method of making same |
US7242097B2 (en) | 2003-06-30 | 2007-07-10 | Intel Corporation | Electromigration barrier layers for solder joints |
US7061096B2 (en) * | 2003-09-24 | 2006-06-13 | Silicon Pipe, Inc. | Multi-surface IC packaging structures and methods for their manufacture |
US7732904B2 (en) * | 2003-10-10 | 2010-06-08 | Interconnect Portfolio Llc | Multi-surface contact IC packaging structures and assemblies |
US7652381B2 (en) * | 2003-11-13 | 2010-01-26 | Interconnect Portfolio Llc | Interconnect system without through-holes |
US7280372B2 (en) * | 2003-11-13 | 2007-10-09 | Silicon Pipe | Stair step printed circuit board structures for high speed signal transmissions |
US7143022B1 (en) | 2003-12-30 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | System and method for integrating subcircuit models in an integrated power grid analysis environment |
US7278855B2 (en) * | 2004-02-09 | 2007-10-09 | Silicon Pipe, Inc | High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture |
US7327583B2 (en) * | 2004-09-13 | 2008-02-05 | Hewlett-Packard Development Company, L.P. | Routing power and ground vias in a substrate |
US7075185B2 (en) * | 2004-09-14 | 2006-07-11 | Hewlett-Packard Development Company, L.P. | Routing vias in a substrate from bypass capacitor pads |
US7227247B2 (en) * | 2005-02-16 | 2007-06-05 | Intel Corporation | IC package with signal land pads |
US20070145543A1 (en) * | 2005-12-28 | 2007-06-28 | Zeng Xiang Y | Plating bar design for high speed package design |
US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
US20080246129A1 (en) * | 2007-04-04 | 2008-10-09 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
US8354743B2 (en) * | 2010-01-27 | 2013-01-15 | Honeywell International Inc. | Multi-tiered integrated circuit package |
US9107294B2 (en) | 2010-07-26 | 2015-08-11 | Hewlett-Packard Development Company, L.P. | System including a module |
US8649183B2 (en) * | 2011-02-10 | 2014-02-11 | Mulpin Research Laboratories, Ltd. | Electronic assembly |
US8713256B2 (en) * | 2011-12-23 | 2014-04-29 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance |
US8653626B2 (en) | 2012-07-18 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures including a capacitor and methods of forming the same |
US9679865B2 (en) * | 2013-11-08 | 2017-06-13 | SK Hynix Inc. | Substrate for semiconductor package and semiconductor package having the same |
US9741644B2 (en) | 2015-05-04 | 2017-08-22 | Honeywell International Inc. | Stacking arrangement for integration of multiple integrated circuits |
Family Cites Families (60)
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US3388457A (en) * | 1966-05-31 | 1968-06-18 | Ibm | Interface resistance monitor |
US4420767A (en) | 1978-11-09 | 1983-12-13 | Zilog, Inc. | Thermally balanced leadless microelectronic circuit chip carrier |
US4608592A (en) * | 1982-07-09 | 1986-08-26 | Nec Corporation | Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage |
US4819041A (en) | 1983-12-30 | 1989-04-04 | Amp Incorporated | Surface mounted integrated circuit chip package and method for making same |
US4891687A (en) | 1987-01-12 | 1990-01-02 | Intel Corporation | Multi-layer molded plastic IC package |
US4951098A (en) * | 1988-12-21 | 1990-08-21 | Eastman Kodak Company | Electrode structure for light emitting diode array chip |
US4899118A (en) | 1988-12-27 | 1990-02-06 | Hughes Aircraft Company | Low temperature cofired ceramic packages for microwave and millimeter wave gallium arsenide integrated circuits |
US5235211A (en) * | 1990-06-22 | 1993-08-10 | Digital Equipment Corporation | Semiconductor package having wraparound metallization |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
JPH04256342A (ja) * | 1991-02-08 | 1992-09-11 | Toshiba Corp | 半導体パッケージ |
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JPH06507275A (ja) | 1992-02-18 | 1994-08-11 | インテル コーポレーション | 薄膜法を用いた多層成形プラスチックパッケージ |
US5218515A (en) | 1992-03-13 | 1993-06-08 | The United States Of America As Represented By The United States Department Of Energy | Microchannel cooling of face down bonded chips |
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JPH05343605A (ja) * | 1992-06-11 | 1993-12-24 | Matsushita Electric Ind Co Ltd | 混成集積回路装置 |
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US5777265A (en) | 1993-01-21 | 1998-07-07 | Intel Corporation | Multilayer molded plastic package design |
FR2701153B1 (fr) * | 1993-02-02 | 1995-04-07 | Matra Marconi Space France | Composant et module de mémoire à semi-conducteur. |
US5291062A (en) | 1993-03-01 | 1994-03-01 | Motorola, Inc. | Area array semiconductor device having a lid with functional contacts |
JP2901835B2 (ja) * | 1993-04-05 | 1999-06-07 | 株式会社東芝 | 半導体装置 |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
AU6582294A (en) * | 1993-04-23 | 1994-11-21 | Nihon Micron Kabushiki Kaisha | Ic package and method of its manufacture |
DE4314910A1 (de) * | 1993-05-05 | 1994-06-30 | Siemens Ag | Gehäuse für eine integrierte Schaltung |
US5357672A (en) | 1993-08-13 | 1994-10-25 | Lsi Logic Corporation | Method and system for fabricating IC packages from laminated boards and heat spreader |
US5490324A (en) * | 1993-09-15 | 1996-02-13 | Lsi Logic Corporation | Method of making integrated circuit package having multiple bonding tiers |
JP2931741B2 (ja) * | 1993-09-24 | 1999-08-09 | 株式会社東芝 | 半導体装置 |
US5371403A (en) * | 1993-09-24 | 1994-12-06 | Vlsi Technology, Inc. | High performance package using high dielectric constant materials for power/ground and low dielectric constant materials for signal lines |
US5442852A (en) | 1993-10-26 | 1995-08-22 | Pacific Microelectronics Corporation | Method of fabricating solder ball array |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
JP3123343B2 (ja) * | 1994-05-11 | 2001-01-09 | 富士電機株式会社 | 安定化電源装置とその製造方法 |
US5400220A (en) | 1994-05-18 | 1995-03-21 | Dell Usa, L.P. | Mechanical printed circuit board and ball grid array interconnect apparatus |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5741729A (en) * | 1994-07-11 | 1998-04-21 | Sun Microsystems, Inc. | Ball grid array package for an integrated circuit |
JPH0846136A (ja) * | 1994-07-26 | 1996-02-16 | Fujitsu Ltd | 半導体装置 |
US5530287A (en) * | 1994-09-14 | 1996-06-25 | Unisys Corporation | High density wire bond pattern for integratd circuit package |
US5569955A (en) * | 1994-09-16 | 1996-10-29 | National Semiconductor Corporation | High density integrated circuit assembly combining leadframe leads with conductive traces |
US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
US5666004A (en) * | 1994-09-28 | 1997-09-09 | Intel Corporation | Use of tantalum oxide capacitor on ceramic co-fired technology |
US5625166A (en) | 1994-11-01 | 1997-04-29 | Intel Corporation | Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect |
US5608261A (en) * | 1994-12-28 | 1997-03-04 | Intel Corporation | High performance and high capacitance package with improved thermal dissipation |
US5672909A (en) * | 1995-02-07 | 1997-09-30 | Amkor Electronics, Inc. | Interdigitated wirebond programmable fixed voltage planes |
US5798909A (en) * | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
US5557502A (en) * | 1995-03-02 | 1996-09-17 | Intel Corporation | Structure of a thermally and electrically enhanced plastic ball grid array package |
US5652463A (en) * | 1995-05-26 | 1997-07-29 | Hestia Technologies, Inc. | Transfer modlded electronic package having a passage means |
US5691041A (en) * | 1995-09-29 | 1997-11-25 | International Business Machines Corporation | Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer |
US5767575A (en) * | 1995-10-17 | 1998-06-16 | Prolinx Labs Corporation | Ball grid array structure and method for packaging an integrated circuit chip |
US5796589A (en) | 1995-12-20 | 1998-08-18 | Intel Corporation | Ball grid array integrated circuit package that has vias located within the solder pads of a package |
US5796170A (en) * | 1996-02-15 | 1998-08-18 | Northern Telecom Limited | Ball grid array (BGA) integrated circuit packages |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
US5726860A (en) | 1996-03-28 | 1998-03-10 | Intel Corporation | Method and apparatus to reduce cavity size and the bondwire length in three tier PGA packages by interdigitating the VCC/VSS |
US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
US5691568A (en) * | 1996-05-31 | 1997-11-25 | Lsi Logic Corporation | Wire bondable package design with maxium electrical performance and minimum number of layers |
US5753976A (en) * | 1996-06-14 | 1998-05-19 | Minnesota Mining And Manufacturing Company | Multi-layer circuit having a via matrix interlayer connection |
US6031283A (en) | 1996-09-09 | 2000-02-29 | Intel Corporation | Integrated circuit package |
US5787575A (en) | 1996-09-09 | 1998-08-04 | Intel Corporation | Method for plating a bond finger of an intergrated circuit package |
US5689091A (en) * | 1996-09-19 | 1997-11-18 | Vlsi Technology, Inc. | Multi-layer substrate structure |
US5801450A (en) | 1996-10-18 | 1998-09-01 | Intel Corporation | Variable pitch stagger die for optimal density |
US5880529A (en) | 1996-10-22 | 1999-03-09 | Intel Corporation | Silicon metal-pillar conductors under stagger bond pads |
US5847936A (en) * | 1997-06-20 | 1998-12-08 | Sun Microsystems, Inc. | Optimized routing scheme for an integrated circuit/printed circuit board |
US6020631A (en) | 1998-01-06 | 2000-02-01 | Intel Corporation | Method and apparatus for connecting a bondwire to a bondring near a via |
-
1996
- 1996-09-09 US US08/709,728 patent/US6043559A/en not_active Expired - Lifetime
-
1997
- 1997-06-27 WO PCT/US1997/011277 patent/WO1998010630A1/en active Application Filing
- 1997-06-27 AU AU35093/97A patent/AU3509397A/en not_active Abandoned
- 1997-09-03 ID IDP973071A patent/ID19414A/id unknown
- 1997-09-09 MY MYPI97004162A patent/MY116965A/en unknown
-
2000
- 2000-03-27 US US09/535,571 patent/US6440770B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
MY116965A (en) | 2004-04-30 |
WO1998010630A1 (en) | 1998-03-12 |
US6440770B1 (en) | 2002-08-27 |
AU3509397A (en) | 1998-03-26 |
US6043559A (en) | 2000-03-28 |
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