HUE049862T2 - N-faktoriális kettõs adatsebességû óra és adat-helyreállítás - Google Patents
N-faktoriális kettõs adatsebességû óra és adat-helyreállításInfo
- Publication number
- HUE049862T2 HUE049862T2 HUE14793347A HUE14793347A HUE049862T2 HU E049862 T2 HUE049862 T2 HU E049862T2 HU E14793347 A HUE14793347 A HU E14793347A HU E14793347 A HUE14793347 A HU E14793347A HU E049862 T2 HUE049862 T2 HU E049862T2
- Authority
- HU
- Hungary
- Prior art keywords
- factorial
- rate clock
- dual
- data
- data rate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Power Engineering (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361886567P | 2013-10-03 | 2013-10-03 | |
US14/252,450 US9178690B2 (en) | 2013-10-03 | 2014-04-14 | N factorial dual data rate clock and data recovery |
Publications (1)
Publication Number | Publication Date |
---|---|
HUE049862T2 true HUE049862T2 (hu) | 2020-10-28 |
Family
ID=52776945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HUE14793347A HUE049862T2 (hu) | 2013-10-03 | 2014-10-01 | N-faktoriális kettõs adatsebességû óra és adat-helyreállítás |
Country Status (8)
Country | Link |
---|---|
US (1) | US9178690B2 (hu) |
EP (1) | EP3053296B1 (hu) |
JP (1) | JP6059404B2 (hu) |
KR (1) | KR101661089B1 (hu) |
CN (1) | CN105637797B (hu) |
ES (1) | ES2791781T3 (hu) |
HU (1) | HUE049862T2 (hu) |
WO (1) | WO2015050980A1 (hu) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9313058B2 (en) | 2013-03-07 | 2016-04-12 | Qualcomm Incorporated | Compact and fast N-factorial single data rate clock and data recovery circuits |
US9337997B2 (en) | 2013-03-07 | 2016-05-10 | Qualcomm Incorporated | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
US9374216B2 (en) | 2013-03-20 | 2016-06-21 | Qualcomm Incorporated | Multi-wire open-drain link with data symbol transition based clocking |
US9203599B2 (en) | 2014-04-10 | 2015-12-01 | Qualcomm Incorporated | Multi-lane N-factorial (N!) and other multi-wire communication systems |
US9755818B2 (en) | 2013-10-03 | 2017-09-05 | Qualcomm Incorporated | Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes |
US9735948B2 (en) | 2013-10-03 | 2017-08-15 | Qualcomm Incorporated | Multi-lane N-factorial (N!) and other multi-wire communication systems |
JP6219538B2 (ja) * | 2014-03-06 | 2017-10-25 | クアルコム,インコーポレイテッド | 複数のワイヤデータ信号のためのクロック復元回路 |
US9621332B2 (en) * | 2015-04-13 | 2017-04-11 | Qualcomm Incorporated | Clock and data recovery for pulse based multi-wire link |
US9520988B1 (en) * | 2015-08-04 | 2016-12-13 | Qualcomm Incorporated | Adaptation to 3-phase signal swap within a trio |
US9485080B1 (en) * | 2015-09-01 | 2016-11-01 | Qualcomm Incorporated | Multiphase clock data recovery circuit calibration |
US20180062887A1 (en) * | 2016-08-24 | 2018-03-01 | Qualcomm Incorporated | Using full ternary transcoding in i3c high data rate mode |
EP3529956B1 (en) * | 2016-10-24 | 2021-07-21 | Qualcomm Incorporated | Reducing transmitter encoding jitter in a c-phy interface using multiple clock phases to launch symbols |
CN111934707A (zh) | 2019-04-25 | 2020-11-13 | 恩智浦有限公司 | 数据发射代码和接口 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5959568A (en) * | 1996-06-26 | 1999-09-28 | Par Goverment Systems Corporation | Measuring distance |
JP3425905B2 (ja) | 1999-10-14 | 2003-07-14 | Necエレクトロニクス株式会社 | クロック信号抽出回路及びそれを有するパラレルディジタルインタフェース並びにクロック信号抽出方法及びそれを有するパラレルデータビット信号の同期化方法 |
US7346357B1 (en) * | 2001-11-08 | 2008-03-18 | At&T Corp. | Frequency assignment for multi-cell IEEE 802.11 wireless networks |
US7167527B1 (en) * | 2002-05-02 | 2007-01-23 | Integrated Memory Logic, Inc. | System and method for multi-symbol interfacing |
EP1385306B1 (en) | 2002-07-22 | 2006-05-24 | Texas Instruments Limited | Method and apparatus for synchronising multiple serial datastreams in parallel |
US7397848B2 (en) | 2003-04-09 | 2008-07-08 | Rambus Inc. | Partial response receiver |
JP2005210695A (ja) * | 2003-12-22 | 2005-08-04 | Kawasaki Microelectronics Kk | データ伝送方式およびデータ伝送回路 |
DE102004013093B3 (de) | 2004-03-17 | 2005-07-21 | Infineon Technologies Ag | Empfängerschaltung für ein Gegentaktübertragungsverfahren |
US7307554B2 (en) | 2004-12-20 | 2007-12-11 | Kawasaki Microelectronics, Inc. | Parallel data transmission method and parallel data transmission system |
US20070073932A1 (en) * | 2005-09-13 | 2007-03-29 | Alcatel | Method and apparatus for a configurable data path interface |
JP4850253B2 (ja) * | 2006-09-29 | 2012-01-11 | 株式会社エヌ・ティ・ティ・ドコモ | 送信装置及び送信フレーム構成方法 |
US7881415B2 (en) | 2006-12-29 | 2011-02-01 | Atmel Corporation | Communication protocol method and apparatus for a single wire device |
US8064535B2 (en) * | 2007-03-02 | 2011-11-22 | Qualcomm Incorporated | Three phase and polarity encoded serial interface |
US8649460B2 (en) | 2007-06-05 | 2014-02-11 | Rambus Inc. | Techniques for multi-wire encoding with an embedded clock |
US8588280B2 (en) | 2007-12-19 | 2013-11-19 | Rambus Inc. | Asymmetric communication on shared links |
US8848810B2 (en) * | 2008-03-05 | 2014-09-30 | Qualcomm Incorporated | Multiple transmitter system and method |
US8659957B2 (en) | 2011-03-07 | 2014-02-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
US9838226B2 (en) * | 2012-01-27 | 2017-12-05 | Apple Inc. | Methods and apparatus for the intelligent scrambling of control symbols |
US9374216B2 (en) | 2013-03-20 | 2016-06-21 | Qualcomm Incorporated | Multi-wire open-drain link with data symbol transition based clocking |
US9337997B2 (en) | 2013-03-07 | 2016-05-10 | Qualcomm Incorporated | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
-
2014
- 2014-04-14 US US14/252,450 patent/US9178690B2/en active Active
- 2014-10-01 HU HUE14793347A patent/HUE049862T2/hu unknown
- 2014-10-01 CN CN201480054735.0A patent/CN105637797B/zh active Active
- 2014-10-01 WO PCT/US2014/058609 patent/WO2015050980A1/en active Application Filing
- 2014-10-01 EP EP14793347.7A patent/EP3053296B1/en active Active
- 2014-10-01 JP JP2016518120A patent/JP6059404B2/ja active Active
- 2014-10-01 ES ES14793347T patent/ES2791781T3/es active Active
- 2014-10-01 KR KR1020167010807A patent/KR101661089B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CN105637797B (zh) | 2019-01-04 |
JP6059404B2 (ja) | 2017-01-11 |
KR101661089B1 (ko) | 2016-09-28 |
US9178690B2 (en) | 2015-11-03 |
ES2791781T3 (es) | 2020-11-05 |
JP2016536842A (ja) | 2016-11-24 |
WO2015050980A1 (en) | 2015-04-09 |
CN105637797A (zh) | 2016-06-01 |
KR20160057483A (ko) | 2016-05-23 |
EP3053296B1 (en) | 2020-03-18 |
US20150098536A1 (en) | 2015-04-09 |
EP3053296A1 (en) | 2016-08-10 |
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