HK87293A - Cmos integrated circuit with a substrate bias generator - Google Patents

Cmos integrated circuit with a substrate bias generator

Info

Publication number
HK87293A
HK87293A HK872/93A HK87293A HK87293A HK 87293 A HK87293 A HK 87293A HK 872/93 A HK872/93 A HK 872/93A HK 87293 A HK87293 A HK 87293A HK 87293 A HK87293 A HK 87293A
Authority
HK
Hong Kong
Prior art keywords
substrate
substrate bias
bias generator
integrated circuit
cmos integrated
Prior art date
Application number
HK872/93A
Other languages
English (en)
Inventor
Josef Dr-Ing Winnerl
Dezsoe Dipl-Phys Takacs
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of HK87293A publication Critical patent/HK87293A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
HK872/93A 1986-09-30 1993-08-26 Cmos integrated circuit with a substrate bias generator HK87293A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3633301 1986-09-30

Publications (1)

Publication Number Publication Date
HK87293A true HK87293A (en) 1993-09-03

Family

ID=6310744

Family Applications (1)

Application Number Title Priority Date Filing Date
HK872/93A HK87293A (en) 1986-09-30 1993-08-26 Cmos integrated circuit with a substrate bias generator

Country Status (8)

Country Link
US (1) US4873668A (xx)
EP (1) EP0262357B1 (xx)
JP (1) JPS6390847A (xx)
KR (1) KR950009225B1 (xx)
AT (1) ATE74453T1 (xx)
CA (1) CA1275457C (xx)
DE (1) DE3777938D1 (xx)
HK (1) HK87293A (xx)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960012249B1 (ko) * 1987-01-12 1996-09-18 지멘스 악티엔게젤샤프트 래치업 방지회로를 가진 cmos 집적회로장치
JPH0666443B2 (ja) * 1988-07-07 1994-08-24 株式会社東芝 半導体メモリセルおよび半導体メモリ
JPH0265358U (xx) * 1988-11-07 1990-05-16
JPH0783254B2 (ja) * 1989-03-22 1995-09-06 株式会社東芝 半導体集積回路
US5079742A (en) * 1989-07-28 1992-01-07 Texas Instruments Incorporated Read-only-memory having sectional output lines with related memory elements responsive to early and late-occurring input signals
FR2717918B1 (fr) * 1994-03-25 1996-05-24 Suisse Electronique Microtech Circuit pour contrôler les tensions entre caisson et sources des transistors mos et système d'asservissement du rapport entre les courants dynamique et statique d'un circuit logique mos.
TW328641B (en) 1995-12-04 1998-03-21 Hitachi Ltd Semiconductor integrated circuit device and process for producing the same
US6014053A (en) * 1997-05-12 2000-01-11 Philips Electronics North America Corporation Amplifier MOS biasing circuit for a avoiding latch-up
JP4014708B2 (ja) 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
US6252452B1 (en) 1998-08-25 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device
DE10211932B9 (de) * 2002-03-18 2006-03-30 Infineon Technologies Ag Schaltungsanordnung zum Auslesen, Bewerten und Wiedereinlesen eines Ladungszustandes in eine Speicherzelle
US7309898B1 (en) * 2002-05-20 2007-12-18 International Business Machines Corporation Method and apparatus for providing noise suppression in an integrated circuit
JP2007103863A (ja) * 2005-10-07 2007-04-19 Nec Electronics Corp 半導体デバイス

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460835A (en) * 1980-05-13 1984-07-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator
US4438346A (en) * 1981-10-15 1984-03-20 Advanced Micro Devices, Inc. Regulated substrate bias generator for random access memory
US4571505A (en) * 1983-11-16 1986-02-18 Inmos Corporation Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits
JPS60253090A (ja) * 1984-05-30 1985-12-13 Hitachi Ltd 半導体装置
US4670669A (en) * 1984-08-13 1987-06-02 International Business Machines Corporation Charge pumping structure for a substrate bias generator
JPS6177421A (ja) * 1984-08-21 1986-04-21 ラテイス・セミコンダクター・コーポレーシヨン Ｃｍｏｓデバイスのラツチアツプを防止する回路と方法
US4670668A (en) * 1985-05-09 1987-06-02 Advanced Micro Devices, Inc. Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up
ATE67617T1 (de) * 1985-08-26 1991-10-15 Siemens Ag Integrierte schaltung in komplementaerer schaltungstechnik mit einem substratvorspannungs- generator.

Also Published As

Publication number Publication date
KR880004589A (ko) 1988-06-07
US4873668A (en) 1989-10-10
EP0262357A3 (en) 1988-06-22
KR950009225B1 (en) 1995-08-18
EP0262357A2 (de) 1988-04-06
JPS6390847A (ja) 1988-04-21
CA1275457C (en) 1990-10-23
EP0262357B1 (de) 1992-04-01
ATE74453T1 (de) 1992-04-15
DE3777938D1 (de) 1992-05-07

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Legal Events

Date Code Title Description
NR Patent deemed never to have been added to the register under section 13(7) of patents (transitional arrangements) rules