HK1183969A1 - 具有無半導體通孔的超薄中介片的半導體封裝件 - Google Patents
具有無半導體通孔的超薄中介片的半導體封裝件Info
- Publication number
- HK1183969A1 HK1183969A1 HK13111137.6A HK13111137A HK1183969A1 HK 1183969 A1 HK1183969 A1 HK 1183969A1 HK 13111137 A HK13111137 A HK 13111137A HK 1183969 A1 HK1183969 A1 HK 1183969A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- semiconductor
- ultra
- vias
- thin interposer
- semiconductor package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/339,234 US9013041B2 (en) | 2011-12-28 | 2011-12-28 | Semiconductor package with ultra-thin interposer without through-semiconductor vias |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1183969A1 true HK1183969A1 (zh) | 2014-01-10 |
Family
ID=48678487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK13111137.6A HK1183969A1 (zh) | 2011-12-28 | 2013-09-29 | 具有無半導體通孔的超薄中介片的半導體封裝件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9013041B2 (zh) |
KR (1) | KR20130076748A (zh) |
CN (2) | CN103187396B (zh) |
HK (1) | HK1183969A1 (zh) |
TW (1) | TWI559476B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9013041B2 (en) | 2011-12-28 | 2015-04-21 | Broadcom Corporation | Semiconductor package with ultra-thin interposer without through-semiconductor vias |
US20130242493A1 (en) * | 2012-03-13 | 2013-09-19 | Qualcomm Mems Technologies, Inc. | Low cost interposer fabricated with additive processes |
US10475732B2 (en) | 2013-07-12 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3DIC package integration for high-frequency RF system |
CN105556648B (zh) | 2013-10-16 | 2019-08-27 | 英特尔公司 | 集成电路封装衬底 |
US9275955B2 (en) | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
KR101622453B1 (ko) | 2014-01-22 | 2016-05-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR20150135611A (ko) | 2014-05-22 | 2015-12-03 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지 및 제조 방법 |
US10211169B2 (en) | 2014-05-27 | 2019-02-19 | University Of Florida Research Foundation, Inc. | Glass interposer integrated high quality electronic components and systems |
CN104637909A (zh) * | 2015-01-30 | 2015-05-20 | 华进半导体封装先导技术研发中心有限公司 | 一种三维芯片集成结构及其加工工艺 |
US10074630B2 (en) * | 2015-04-14 | 2018-09-11 | Amkor Technology, Inc. | Semiconductor package with high routing density patch |
US9735079B2 (en) * | 2015-10-08 | 2017-08-15 | Dyi-chung Hu | Molding compound wrapped package substrate |
US10163856B2 (en) * | 2015-10-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuit structure and method of forming |
US10276403B2 (en) * | 2016-06-15 | 2019-04-30 | Avago Technologies International Sales Pe. Limited | High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer |
US20180102776A1 (en) * | 2016-10-07 | 2018-04-12 | Altera Corporation | Methods and apparatus for managing application-specific power gating on multichip packages |
KR20180086804A (ko) * | 2017-01-23 | 2018-08-01 | 앰코 테크놀로지 인코포레이티드 | 반도체 디바이스 및 그 제조 방법 |
US10057976B1 (en) * | 2017-08-31 | 2018-08-21 | Xilinx, Inc. | Power-ground co-reference transceiver structure to deliver ultra-low crosstalk |
US11282776B2 (en) * | 2018-02-22 | 2022-03-22 | Xilinx, Inc. | High density routing for heterogeneous package integration |
US20190312019A1 (en) * | 2018-04-10 | 2019-10-10 | Intel Corporation | Techniques for die tiling |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6636416B2 (en) | 2001-06-14 | 2003-10-21 | Intel Corporation | Electronic assembly with laterally connected capacitors and manufacturing method |
JP3674780B2 (ja) | 2001-11-29 | 2005-07-20 | ユーディナデバイス株式会社 | 高周波半導体装置 |
US7317622B2 (en) | 2002-12-31 | 2008-01-08 | Intel Corporation | Method and apparatus for supplying power to a semiconductor device using a capacitor DC shunt |
US6819001B2 (en) * | 2003-03-14 | 2004-11-16 | General Electric Company | Interposer, interposer package and device assembly employing the same |
US7027289B2 (en) * | 2004-03-25 | 2006-04-11 | Intel Corporation | Extended thin film capacitor (TFC) |
US7486525B2 (en) * | 2006-08-04 | 2009-02-03 | International Business Machines Corporation | Temporary chip attach carrier |
US7576435B2 (en) * | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
US20090014852A1 (en) | 2007-07-11 | 2009-01-15 | Hsin-Hui Lee | Flip-Chip Packaging with Stud Bumps |
US7619441B1 (en) * | 2008-03-03 | 2009-11-17 | Xilinx, Inc. | Apparatus for interconnecting stacked dice on a programmable integrated circuit |
US8138014B2 (en) | 2010-01-29 | 2012-03-20 | Stats Chippac, Ltd. | Method of forming thin profile WLCSP with vertical interconnect over package footprint |
US8951839B2 (en) | 2010-03-15 | 2015-02-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP |
US9406738B2 (en) * | 2011-07-20 | 2016-08-02 | Xilinx, Inc. | Inductive structure formed using through silicon vias |
US9013041B2 (en) | 2011-12-28 | 2015-04-21 | Broadcom Corporation | Semiconductor package with ultra-thin interposer without through-semiconductor vias |
-
2011
- 2011-12-28 US US13/339,234 patent/US9013041B2/en active Active
-
2012
- 2012-12-10 TW TW101146369A patent/TWI559476B/zh not_active IP Right Cessation
- 2012-12-20 CN CN201210559301.9A patent/CN103187396B/zh active Active
- 2012-12-20 CN CN2012207127688U patent/CN203103294U/zh not_active Expired - Fee Related
- 2012-12-27 KR KR1020120154172A patent/KR20130076748A/ko not_active Application Discontinuation
-
2013
- 2013-09-29 HK HK13111137.6A patent/HK1183969A1/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN103187396A (zh) | 2013-07-03 |
TW201330200A (zh) | 2013-07-16 |
CN103187396B (zh) | 2016-03-30 |
TWI559476B (zh) | 2016-11-21 |
US9013041B2 (en) | 2015-04-21 |
US20130168860A1 (en) | 2013-07-04 |
CN203103294U (zh) | 2013-07-31 |
KR20130076748A (ko) | 2013-07-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |
Effective date: 20201218 |