HK1169222A1 - 包含用於減少鎖定時間之機制之延遲鎖定迴路 - Google Patents

包含用於減少鎖定時間之機制之延遲鎖定迴路

Info

Publication number
HK1169222A1
HK1169222A1 HK12109708.0A HK12109708A HK1169222A1 HK 1169222 A1 HK1169222 A1 HK 1169222A1 HK 12109708 A HK12109708 A HK 12109708A HK 1169222 A1 HK1169222 A1 HK 1169222A1
Authority
HK
Hong Kong
Prior art keywords
locked loop
delay locked
loop including
lock time
reducing lock
Prior art date
Application number
HK12109708.0A
Other languages
English (en)
Inventor
Pradeep R Trivedi
Kaenel Vincent R Von
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of HK1169222A1 publication Critical patent/HK1169222A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
HK12109708.0A 2010-10-11 2012-10-03 包含用於減少鎖定時間之機制之延遲鎖定迴路 HK1169222A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/901,745 US8368444B2 (en) 2010-10-11 2010-10-11 Delay locked loop including a mechanism for reducing lock time

Publications (1)

Publication Number Publication Date
HK1169222A1 true HK1169222A1 (zh) 2013-01-18

Family

ID=44759567

Family Applications (1)

Application Number Title Priority Date Filing Date
HK12109708.0A HK1169222A1 (zh) 2010-10-11 2012-10-03 包含用於減少鎖定時間之機制之延遲鎖定迴路

Country Status (7)

Country Link
US (1) US8368444B2 (zh)
EP (1) EP2439848B1 (zh)
KR (1) KR101296000B1 (zh)
HK (1) HK1169222A1 (zh)
NL (1) NL2007558C2 (zh)
TW (1) TWI469523B (zh)
WO (1) WO2012051023A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8373470B2 (en) * 2010-10-11 2013-02-12 Apple Inc. Modular programmable delay line blocks for use in a delay locked loop
KR102062844B1 (ko) 2013-11-06 2020-02-11 에스케이하이닉스 주식회사 동기 회로 및 이를 이용한 반도체 장치
US10511313B1 (en) * 2019-03-04 2019-12-17 Goke Taiwan Research Laboratory Ltd. Phase-detecting method and circuit for testing a delay locked loop/delay line
CN113659979B (zh) * 2021-08-20 2024-07-05 长江存储科技有限责任公司 延迟锁相环及其延迟线锁定方法、装置、介质及系统

Family Cites Families (25)

* Cited by examiner, † Cited by third party
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US6388482B1 (en) 2000-06-21 2002-05-14 Infineon Technologies North America Corp. DLL lock scheme with multiple phase detection
US7028206B2 (en) 2002-12-16 2006-04-11 William Kenneth Waller Circuit and method for generating a local clock signal synchronized to an externally generated reference clock signal
US7336752B2 (en) * 2002-12-31 2008-02-26 Mosaid Technologies Inc. Wide frequency range delay locked loop
US6970047B1 (en) 2003-07-28 2005-11-29 Lattice Semiconductor Corporation Programmable lock detector and corrector
US6914492B2 (en) 2003-09-25 2005-07-05 Lsi Logic Corporation Digital programmable delay scheme with automatic calibration
KR100540930B1 (ko) * 2003-10-31 2006-01-11 삼성전자주식회사 지연동기루프 회로
KR100564595B1 (ko) * 2003-12-13 2006-03-28 삼성전자주식회사 위상 보간 스텝의 크기를 선택적으로 변경시키는 ｄｌｌ
US6958634B2 (en) 2003-12-24 2005-10-25 Intel Corporation Programmable direct interpolating delay locked loop
US7034589B2 (en) 2004-02-26 2006-04-25 Silicon Integrated Systems Corp. Multi-stage delay clock generator
KR100711547B1 (ko) * 2005-08-29 2007-04-27 주식회사 하이닉스반도체 지연 고정 루프
GB2434930B (en) * 2006-02-01 2009-08-26 Wolfson Microelectronics Plc Delay-locked loop circuits
JP4665809B2 (ja) * 2006-03-24 2011-04-06 トヨタ自動車株式会社 電動機駆動制御システム
KR100780952B1 (ko) * 2006-06-27 2007-12-03 삼성전자주식회사 디스큐 장치 및 방법, 그리고 이를 이용한 데이터 수신장치및 방법
US7716001B2 (en) * 2006-11-15 2010-05-11 Qualcomm Incorporated Delay line calibration
US7667504B2 (en) * 2007-05-22 2010-02-23 International Business Machines Corporation Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals
US7573307B2 (en) 2007-08-01 2009-08-11 Texas Instruments Incorporated Systems and methods for reduced area delay locked loop
KR100822307B1 (ko) * 2007-09-20 2008-04-16 주식회사 아나패스 데이터 구동 회로 및 지연 고정 루프
KR100956774B1 (ko) * 2007-12-28 2010-05-12 주식회사 하이닉스반도체 지연 고정 루프 회로 및 그 제어 방법
US8054116B2 (en) * 2008-01-23 2011-11-08 Qualcomm Incorporated Threshold dithering for time-to-digital converters
US7733149B2 (en) 2008-06-11 2010-06-08 Pmc-Sierra, Inc. Variable-length digitally-controlled delay chain with interpolation-based tuning
KR101679755B1 (ko) * 2009-01-23 2016-11-28 삼성전자주식회사 빠른 락킹 타임을 갖는 클럭 신호 생성기
JP2010200090A (ja) 2009-02-26 2010-09-09 Toshiba Corp 位相補償用クロック同期回路
KR101004766B1 (ko) * 2010-05-31 2011-01-03 주식회사 아나패스 Ｌｃ ｖｃｏ를 포함하는 ｐｌｌ 및 타이밍 컨트롤러
KR101035856B1 (ko) * 2010-05-31 2011-05-19 주식회사 아나패스 타이밍 컨트롤러와 데이터 구동ｉｃ들 사이의 인터페이스 시스템 및 디스플레이 장치
US8804888B2 (en) * 2010-07-12 2014-08-12 Ensphere Solutions, Inc. Wide band clock data recovery

Also Published As

Publication number Publication date
KR20120037356A (ko) 2012-04-19
EP2439848A1 (en) 2012-04-11
US8368444B2 (en) 2013-02-05
WO2012051023A1 (en) 2012-04-19
US20120086484A1 (en) 2012-04-12
KR101296000B1 (ko) 2013-08-14
TW201223162A (en) 2012-06-01
NL2007558C2 (en) 2012-04-12
TWI469523B (zh) 2015-01-11
EP2439848B1 (en) 2015-07-22

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20191015