HK109194A - Microprocessor bus interface unit - Google Patents

Microprocessor bus interface unit

Info

Publication number
HK109194A
HK109194A HK109194A HK109194A HK109194A HK 109194 A HK109194 A HK 109194A HK 109194 A HK109194 A HK 109194A HK 109194 A HK109194 A HK 109194A HK 109194 A HK109194 A HK 109194A
Authority
HK
Hong Kong
Prior art keywords
interface unit
bus interface
microprocessor bus
microprocessor
unit
Prior art date
Application number
HK109194A
Other languages
English (en)
Inventor
Kenneth D Shoemaker
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK109194A publication Critical patent/HK109194A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
HK109194A 1988-08-01 1994-10-12 Microprocessor bus interface unit HK109194A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/227,078 US5073969A (en) 1988-08-01 1988-08-01 Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal

Publications (1)

Publication Number Publication Date
HK109194A true HK109194A (en) 1994-10-21

Family

ID=22851663

Family Applications (1)

Application Number Title Priority Date Filing Date
HK109194A HK109194A (en) 1988-08-01 1994-10-12 Microprocessor bus interface unit

Country Status (9)

Country Link
US (1) US5073969A (de)
JP (1) JPH0248747A (de)
KR (1) KR960016412B1 (de)
CN (1) CN1018098B (de)
DE (1) DE3923253C2 (de)
FR (1) FR2634919B1 (de)
GB (1) GB2221553B (de)
HK (1) HK109194A (de)
SG (1) SG58393G (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
JP2504206B2 (ja) * 1989-07-27 1996-06-05 三菱電機株式会社 バスコントロ―ラ
US5319769A (en) * 1989-09-11 1994-06-07 Sharp Kabushiki Kaisha Memory access circuit for handling data pockets including data having misaligned addresses and different widths
US5416907A (en) * 1990-06-15 1995-05-16 Digital Equipment Corporation Method and apparatus for transferring data processing data transfer sizes
JP2502403B2 (ja) * 1990-07-20 1996-05-29 三菱電機株式会社 Ｄｍａ制御装置
KR0181471B1 (ko) * 1990-07-27 1999-05-15 윌리암 피.브레이든 컴퓨터 데이타 경로배정 시스템
DE69130967T2 (de) * 1990-08-06 1999-10-21 Ncr International, Inc. Rechnerspeicheranordnung
GB9018993D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station interfacing means having burst mode capability
GB9018992D0 (en) * 1990-08-31 1990-10-17 Ncr Co Internal bus for work station interfacing means
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
US5386579A (en) * 1991-09-16 1995-01-31 Integrated Device Technology, Inc. Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer
JP2519860B2 (ja) * 1991-09-16 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション バ―ストデ―タ転送装置および方法
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
TW276312B (de) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5422029A (en) * 1993-06-18 1995-06-06 Potini; Chimpiramma Composition for cleaning contact lenses
US5555392A (en) * 1993-10-01 1996-09-10 Intel Corporation Method and apparatus for a line based non-blocking data cache
US5649127A (en) * 1994-05-04 1997-07-15 Samsung Semiconductor, Inc. Method and apparatus for packing digital data
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
CN103345380B (zh) * 1995-08-31 2016-05-18 英特尔公司 控制移位分组数据的位校正的装置
US5752267A (en) * 1995-09-27 1998-05-12 Motorola Inc. Data processing system for accessing an external device during a burst mode of operation and method therefor
US5689659A (en) * 1995-10-30 1997-11-18 Motorola, Inc. Method and apparatus for bursting operand transfers during dynamic bus sizing
KR102701876B1 (ko) * 2024-02-07 2024-09-04 주식회사 대호 효소 복합 사료첨가제

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079451A (en) * 1976-04-07 1978-03-14 Honeywell Information Systems Inc. Word, byte and bit indexed addressing in a data processing system
US4099253A (en) * 1976-09-13 1978-07-04 Dynage, Incorporated Random access memory with bit or byte addressing capability
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4131940A (en) * 1977-07-25 1978-12-26 International Business Machines Corporation Channel data buffer apparatus for a digital data processing system
US4447878A (en) * 1978-05-30 1984-05-08 Intel Corporation Apparatus and method for providing byte and word compatible information transfers
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
US4443846A (en) * 1980-12-29 1984-04-17 Sperry Corporation Dual port exchange memory between multiple microprocessors
JPS5955525A (ja) * 1982-09-25 1984-03-30 Toshiba Corp マイクロプロセツサ
US4507731A (en) * 1982-11-01 1985-03-26 Raytheon Company Bidirectional data byte aligner
KR900007564B1 (ko) * 1984-06-26 1990-10-15 모토로라 인코포레이티드 동적 버스를 갖는 데이터 처리기
US4716527A (en) * 1984-12-10 1987-12-29 Ing. C. Olivetti Bus converter
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
JPS62102344A (ja) * 1985-10-29 1987-05-12 Fujitsu Ltd バツフア・メモリ制御方式
US4920483A (en) * 1985-11-15 1990-04-24 Data General Corporation A computer memory for accessing any word-sized group of contiguous bits
JPH0772886B2 (ja) * 1986-08-01 1995-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーション データ処理システム
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
US4816997A (en) * 1987-09-21 1989-03-28 Motorola, Inc. Bus master having selective burst deferral
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access
US4912630A (en) * 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control

Also Published As

Publication number Publication date
GB8827743D0 (en) 1988-12-29
FR2634919A1 (fr) 1990-02-02
FR2634919B1 (fr) 1993-08-13
CN1040105A (zh) 1990-02-28
DE3923253A1 (de) 1990-02-08
GB2221553B (en) 1992-08-19
GB2221553A (en) 1990-02-07
KR960016412B1 (ko) 1996-12-11
CN1018098B (zh) 1992-09-02
US5073969A (en) 1991-12-17
KR900003747A (ko) 1990-03-27
DE3923253C2 (de) 1997-01-23
SG58393G (en) 1993-08-06
JPH0248747A (ja) 1990-02-19

Similar Documents

Publication Publication Date Title
GB2221553B (en) Microprocessor bus interface unit
EP0432866A3 (en) Line interface unit
GB2222900B (en) User interface system
GB8722475D0 (en) Microprocessor system
GB2194085B (en) Bus
GB2230923B (en) An interface unit
EP0250952A3 (en) Microprocessor
GB8608369D0 (en) Interface unit
EP0417290A4 (en) Interface for electric endermism
EP0344677A3 (en) Microprocessor system
GB2221748B (en) Safety unit
GB2227766B (en) Panel unit
GB8806836D0 (en) Arbitration system
GB2215557B (en) Interface unit
GB8907675D0 (en) Microprocessor initialization assurance system
GB2216649B (en) Hob unit
GB8806257D0 (en) Microprocessor system
GB8805058D0 (en) Indicating controls
GB2228111B (en) Microcomputer interface arrangement
BG45674A1 (en) Microprocessor interface
GB8819079D0 (en) Bus connector
AU109627S (en) Bus bar
IE881292L (en) Backplane bus
GB8800251D0 (en) One unit mop-bucket
AU107075S (en) Wiring unit

Legal Events

Date Code Title Description
PF Patent in force
PE Patent expired

Effective date: 20081127