FR2634919B1 - Interface de bus pour microprocesseur - Google Patents

Interface de bus pour microprocesseur

Info

Publication number
FR2634919B1
FR2634919B1 FR898901180A FR8901180A FR2634919B1 FR 2634919 B1 FR2634919 B1 FR 2634919B1 FR 898901180 A FR898901180 A FR 898901180A FR 8901180 A FR8901180 A FR 8901180A FR 2634919 B1 FR2634919 B1 FR 2634919B1
Authority
FR
France
Prior art keywords
microprocessor
bus interface
bus
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR898901180A
Other languages
English (en)
Other versions
FR2634919A1 (fr
Inventor
Kenneth D Shoemaker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2634919A1 publication Critical patent/FR2634919A1/fr
Application granted granted Critical
Publication of FR2634919B1 publication Critical patent/FR2634919B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
FR898901180A 1988-08-01 1989-01-31 Interface de bus pour microprocesseur Expired - Fee Related FR2634919B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/227,078 US5073969A (en) 1988-08-01 1988-08-01 Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal

Publications (2)

Publication Number Publication Date
FR2634919A1 FR2634919A1 (fr) 1990-02-02
FR2634919B1 true FR2634919B1 (fr) 1993-08-13

Family

ID=22851663

Family Applications (1)

Application Number Title Priority Date Filing Date
FR898901180A Expired - Fee Related FR2634919B1 (fr) 1988-08-01 1989-01-31 Interface de bus pour microprocesseur

Country Status (9)

Country Link
US (1) US5073969A (fr)
JP (1) JPH0248747A (fr)
KR (1) KR960016412B1 (fr)
CN (1) CN1018098B (fr)
DE (1) DE3923253C2 (fr)
FR (1) FR2634919B1 (fr)
GB (1) GB2221553B (fr)
HK (1) HK109194A (fr)
SG (1) SG58393G (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
JP2504206B2 (ja) * 1989-07-27 1996-06-05 三菱電機株式会社 バスコントロ―ラ
US5319769A (en) * 1989-09-11 1994-06-07 Sharp Kabushiki Kaisha Memory access circuit for handling data pockets including data having misaligned addresses and different widths
US5416907A (en) * 1990-06-15 1995-05-16 Digital Equipment Corporation Method and apparatus for transferring data processing data transfer sizes
JP2502403B2 (ja) * 1990-07-20 1996-05-29 三菱電機株式会社 Ｄｍａ制御装置
KR0181471B1 (ko) * 1990-07-27 1999-05-15 윌리암 피.브레이든 컴퓨터 데이타 경로배정 시스템
EP0470735B1 (fr) * 1990-08-06 1999-03-10 NCR International, Inc. Système de mémoire d'ordinateur
GB9018992D0 (en) * 1990-08-31 1990-10-17 Ncr Co Internal bus for work station interfacing means
GB9018993D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station interfacing means having burst mode capability
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
JP2519860B2 (ja) * 1991-09-16 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション バ―ストデ―タ転送装置および方法
US5386579A (en) * 1991-09-16 1995-01-31 Integrated Device Technology, Inc. Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
TW276312B (fr) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5422029A (en) * 1993-06-18 1995-06-06 Potini; Chimpiramma Composition for cleaning contact lenses
US5555392A (en) * 1993-10-01 1996-09-10 Intel Corporation Method and apparatus for a line based non-blocking data cache
US5649127A (en) * 1994-05-04 1997-07-15 Samsung Semiconductor, Inc. Method and apparatus for packing digital data
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
CN1252587C (zh) * 1995-08-31 2006-04-19 英特尔公司 移位分组数据的方法、装置和处理数字音频信号的系统
US5752267A (en) * 1995-09-27 1998-05-12 Motorola Inc. Data processing system for accessing an external device during a burst mode of operation and method therefor
US5689659A (en) * 1995-10-30 1997-11-18 Motorola, Inc. Method and apparatus for bursting operand transfers during dynamic bus sizing
KR102701876B1 (ko) * 2024-02-07 2024-09-04 주식회사 대호 효소 복합 사료첨가제

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079451A (en) * 1976-04-07 1978-03-14 Honeywell Information Systems Inc. Word, byte and bit indexed addressing in a data processing system
US4099253A (en) * 1976-09-13 1978-07-04 Dynage, Incorporated Random access memory with bit or byte addressing capability
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4131940A (en) * 1977-07-25 1978-12-26 International Business Machines Corporation Channel data buffer apparatus for a digital data processing system
US4447878A (en) * 1978-05-30 1984-05-08 Intel Corporation Apparatus and method for providing byte and word compatible information transfers
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
US4443846A (en) * 1980-12-29 1984-04-17 Sperry Corporation Dual port exchange memory between multiple microprocessors
JPS5955525A (ja) * 1982-09-25 1984-03-30 Toshiba Corp マイクロプロセツサ
US4507731A (en) * 1982-11-01 1985-03-26 Raytheon Company Bidirectional data byte aligner
KR900007564B1 (ko) * 1984-06-26 1990-10-15 모토로라 인코포레이티드 동적 버스를 갖는 데이터 처리기
US4716527A (en) * 1984-12-10 1987-12-29 Ing. C. Olivetti Bus converter
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
JPS62102344A (ja) * 1985-10-29 1987-05-12 Fujitsu Ltd バツフア・メモリ制御方式
US4920483A (en) * 1985-11-15 1990-04-24 Data General Corporation A computer memory for accessing any word-sized group of contiguous bits
JPH0772886B2 (ja) * 1986-08-01 1995-08-02 インターナショナル・ビジネス・マシーンズ・コーポレーション データ処理システム
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
US4816997A (en) * 1987-09-21 1989-03-28 Motorola, Inc. Bus master having selective burst deferral
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access
US4912630A (en) * 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control

Also Published As

Publication number Publication date
JPH0248747A (ja) 1990-02-19
DE3923253A1 (de) 1990-02-08
SG58393G (en) 1993-08-06
GB2221553B (en) 1992-08-19
US5073969A (en) 1991-12-17
FR2634919A1 (fr) 1990-02-02
KR960016412B1 (ko) 1996-12-11
DE3923253C2 (de) 1997-01-23
GB2221553A (en) 1990-02-07
HK109194A (en) 1994-10-21
KR900003747A (ko) 1990-03-27
CN1018098B (zh) 1992-09-02
CN1040105A (zh) 1990-02-28
GB8827743D0 (en) 1988-12-29

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20081029