HK1042013B - Integrated circuit package having a substrate vent hole - Google Patents

Integrated circuit package having a substrate vent hole Download PDF

Info

Publication number
HK1042013B
HK1042013B HK02103549.8A HK02103549A HK1042013B HK 1042013 B HK1042013 B HK 1042013B HK 02103549 A HK02103549 A HK 02103549A HK 1042013 B HK1042013 B HK 1042013B
Authority
HK
Hong Kong
Prior art keywords
substrate
integrated circuit
opening
package
underfill material
Prior art date
Application number
HK02103549.8A
Other languages
German (de)
English (en)
French (fr)
Chinese (zh)
Other versions
HK1042013A1 (en
Inventor
Suresh Ramalingam
Nagesh Vodrahalli
Michael J. Costello
Mun Leong Loke
Ravi V. Mahajan
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of HK1042013A1 publication Critical patent/HK1042013A1/en
Publication of HK1042013B publication Critical patent/HK1042013B/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00Packaging processes not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/012Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/681Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/856Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49163Manufacturing circuit on or in base with sintering of base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
HK02103549.8A 1999-06-11 2000-06-05 Integrated circuit package having a substrate vent hole HK1042013B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US330373 1999-06-11
US09/330,373 US6490166B1 (en) 1999-06-11 1999-06-11 Integrated circuit package having a substrate vent hole
PCT/US2000/040107 WO2000078103A1 (en) 1999-06-11 2000-06-05 Integrated circuit package having a substrate vent hole

Publications (2)

Publication Number Publication Date
HK1042013A1 HK1042013A1 (en) 2002-07-26
HK1042013B true HK1042013B (en) 2006-06-02

Family

ID=23289477

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02103549.8A HK1042013B (en) 1999-06-11 2000-06-05 Integrated circuit package having a substrate vent hole

Country Status (9)

Country Link
US (2) US6490166B1 (https=)
EP (1) EP1186212B1 (https=)
JP (1) JP2003501841A (https=)
KR (1) KR100456443B1 (https=)
AU (1) AU5790700A (https=)
DE (1) DE60026028T2 (https=)
HK (1) HK1042013B (https=)
IL (2) IL146865A0 (https=)
WO (1) WO2000078103A1 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154658A (ja) * 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US6483101B1 (en) 1999-12-08 2002-11-19 Amkor Technology, Inc. Molded image sensor package having lens holder
US6861720B1 (en) * 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
US6693239B2 (en) * 2001-09-06 2004-02-17 Delphi Technologies Inc. Overmolded circuit board with underfilled surface-mount component and method therefor
US6800946B2 (en) * 2002-12-23 2004-10-05 Motorola, Inc Selective underfill for flip chips and flip-chip assemblies
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050218528A1 (en) * 2004-03-31 2005-10-06 Beatty John J Capillary underfill channel
US20060046321A1 (en) * 2004-08-27 2006-03-02 Hewlett-Packard Development Company, L.P. Underfill injection mold
US20070087481A1 (en) * 2005-10-19 2007-04-19 Himax Technologies, Inc. Underfill aiding process for a tape
WO2009044863A1 (ja) * 2007-10-03 2009-04-09 Fujikura Ltd. モジュール、配線板、及びモジュールの製造方法
US9105647B2 (en) * 2010-05-17 2015-08-11 Stats Chippac, Ltd. Method of forming perforated opening in bottom substrate of flipchip pop assembly to reduce bleeding of underfill material
US8522426B2 (en) * 2010-06-05 2013-09-03 Raytheon Company Vent blocking on vented ball grid arrays to provide a cleaner solution barrier
AU2013201130B2 (en) * 2012-02-29 2014-12-11 Robert Bosch (Australia) Pty Ltd Printed circuit board
KR101970667B1 (ko) 2012-07-31 2019-04-19 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101934917B1 (ko) * 2012-08-06 2019-01-04 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9331370B1 (en) 2013-03-14 2016-05-03 Altera Corporation Multilayer integrated circuit packages with localized air structures
US9917068B2 (en) * 2014-03-14 2018-03-13 Taiwan Semiconductor Manufacturing Company Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
EP3045909B1 (en) 2015-01-14 2020-11-04 Sensirion AG Sensor package
KR102437774B1 (ko) 2015-11-17 2022-08-30 삼성전자주식회사 인쇄 회로 기판
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US20220028704A1 (en) * 2018-12-18 2022-01-27 Octavo Systems Llc Molded packages in a molded device
KR102932547B1 (ko) 2020-05-22 2026-03-03 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
US5218234A (en) 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5313365A (en) * 1992-06-30 1994-05-17 Motorola, Inc. Encapsulated electronic package
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
US5385869A (en) * 1993-07-22 1995-01-31 Motorola, Inc. Semiconductor chip bonded to a substrate and method of making
US5473512A (en) * 1993-12-16 1995-12-05 At&T Corp. Electronic device package having electronic device boonded, at a localized region thereof, to circuit board
US5721450A (en) 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US5766982A (en) * 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
CA2198305A1 (en) 1996-05-01 1997-11-02 Yinon Degani Integrated circuit bonding method and apparatus
JPH10261661A (ja) 1997-03-19 1998-09-29 Toshiba Corp アンダーフィル充填方法及びプリント配線板構造
US5981312A (en) * 1997-06-27 1999-11-09 International Business Machines Corporation Method for injection molded flip chip encapsulation
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JPH11340375A (ja) 1998-05-26 1999-12-10 Toshiba Corp 配線基板および電子ユニットおよび電子部品実装方法

Also Published As

Publication number Publication date
EP1186212B1 (en) 2006-02-15
JP2003501841A (ja) 2003-01-14
WO2000078103A1 (en) 2000-12-21
KR100456443B1 (ko) 2004-11-09
HK1042013A1 (en) 2002-07-26
USRE44629E1 (en) 2013-12-10
DE60026028D1 (de) 2006-04-20
DE60026028T2 (de) 2006-08-10
EP1186212A1 (en) 2002-03-13
KR20020007424A (ko) 2002-01-26
IL146865A0 (en) 2002-07-25
AU5790700A (en) 2001-01-02
US6490166B1 (en) 2002-12-03
IL146865A (en) 2007-03-08

Similar Documents

Publication Publication Date Title
EP1186212B1 (en) Integrated circuit package having a substrate vent hole
US6969636B1 (en) Semiconductor package with stress inhibiting intermediate mounting substrate
US6573592B2 (en) Semiconductor die packages with standard ball grid array footprint and method for assembling the same
US6987058B2 (en) Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material
KR100412156B1 (ko) 반도체장치 및 그 제조방법
US7208410B2 (en) Methods relating to forming interconnects
US6238948B1 (en) Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
US6963142B2 (en) Flip chip integrated package mount support
US7510108B2 (en) Method of making an electronic assembly
US20020014688A1 (en) Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6331446B1 (en) Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US6528345B1 (en) Process line for underfilling a controlled collapse
US6266249B1 (en) Semiconductor flip chip ball grid array package

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20130605