GB782406A - - Google Patents

Abstract

782,406. Transistor bistable pulse generating and frequency dividing circuits. NATIONAL CASH REGISTER CO. Jan. 9, 1956 [Feb. 4, 1955], No. 658/56. Class 40 (6). In a circuit for producing pulses F1<SP>1</SP>C, F1C on one or other lead 33, 34, a first gating circuit 16, controlled by a twostable state transistor circuit 12, is fed with clock pulses C, the output of which is also fed to gating circuits 35, 36 which are also supplied with clock pulses C. Assuming transistor T1 to be in the fully conducting or on condition, the collector potential and thus the base potential of transistor T2 is high so that the transistor T2 is cut off and no clock pulses C pass to the collector circuit. Since battery 58 is arranged to have a lower negative potential than the two equal-valued batteries 46, 64 diode 68 is conducting and pulses C are fed out to lead 33 over diode 68 but are not passed by diode 72 since it will present a high impedance. When transistor T1 is off and transistor T2 conducts clock pulses C are fed to transformer 27 to generate gating pulses F1<SP>1</SP>, F1 which bias off diode 68 and allow clock pulses to pass through diode 72 to lead 34. With transistor T1 off, Fig. 2, the positive-going clock pulses C are passed by transistor T2, generating gating pulses F1 and F1<SP>1</SP> which switch gates 35, 36 to feed out pulse F1C. When a pulse Of1 is applied at terminal 9 it is differentiated by the input capacitor and resistor and the negative-going spike 80 triggers the transistor T1 to its on state thereby cutting off transistor T2. The next clock pulse C is not passed by transistor T2 and since the gating pulses F1<SP>1</SP> and F1 do not appear, the clock pulse passes through diode 68 a pulse F1<SP>1</SP>C. The train of clock pulses continues in this manner until a pulsef is applied at terminal 8 and the negative-going spike 81 resets transistor T1 at the emitter opening the gate T2 so that pulses F1C again pass out over lead 34. Bi-stable state circuit. With transistor T1 in the off state the junction 7 is caught at the potential of supply 22 due to diode 21 conducting while the collector is caught at the potential of supply 43 due to diode 44. When a negative triggering potential is applied to the base, the diode 14a presents a high impedance and improves the triggering sensitivity. Diodes 19 and 78 define the peak and valley of the V/I characteristic of the emitter, Fig. 3 (not shown). Frequency division. The circuit may be back-coupled, Fig. 4, to give a frequency division of two and a further stage or stages may be added. Assuming bi-stable state circuit 12<SP>1</SP> to be on, the gate 16<SP>1</SP> is closed and a pulse appears at output F1<SP>1</SP>C which is fed back as input to terminal f to cause circuit 12<SP>1</SP> to pass to the off state and the gate 16<SP>1</SP> to open. The succeeding clock pulse C is then passed through the gate and appears on the lead F1C which is in turn fed back to the input Of1 to reset the circuit 12<SP>1</SP> to its original state. The pulses appearing on the lead F1<SP>1</SP>C, F1C occur at half the clock pulse frequency and by employing them in a second circuit F2 a further subdivision may be obtained. Assuming the circuit 12<SP>11</SP> to be off and the gate 16" to be open, the clock pulses C are fed out on the lead F1<SP>1</SP>, F2C and thus back to the input Of2 which sets the circuit 12<SP>11</SP> off and closes the gate 16<SP>11</SP> so that the next F1<SP>1</SP>C pulses passes out on the lead F1<SP>1</SP>, F2<SP>1</SP>C and back to the input f2 which resets the circuit 12<SP>11</SP> to its off state.