GB813676A - Improvements in or relating to delay networks incorporating diode amplifiers - Google Patents

Abstract

813,676. Semi-conductor pulse delaying and frequency dividing circuits. SIEMENS & HALSKE A.G. Sept. 27, 1957 [Sept. 28, 1956], No. 30399/57. Class 40 (6). In a circuit comprising a series of diode amplifiers D1, Fig. 3, an input pulse E1, Fig. 5, is applied to the first stage fed with clock pulses S1 to generate a pulse which is fed over a forward-conducting only coupling to the next stage fed with phase-shifted clock pulses S2 so that the input pulse is fed through the circuit to the output A4 in synchronism with the clock pulses. The input pulse E1 is fed over normal diode D2 to the carrier storage diode D1 to establish a charge storage condition. After the termination of the pulse E1 the positive-going clock pulse Sl is applied in the reverse direction to diode D1 to generate a pulse across resistor R2. This pulse is gated by pulse S1 in the AND circuit T1 to produce the pulse A1 as input to the next stage. A small pulse is produced across resistor R2 during the input pulse, Fig. 2 (not shown), but this does not pass to the next stage due to the circuit T1. The pulse is passed through the amplifier stages and fed out as pulse A4. The circuits T1 may be replaced by amplifiers which are insensitive to pulses below a certain amplitude, Fig. 4 (not shown). Transistor amplifiers K, Fig. 6, may be employed connected in the common collector arrangement with the base biased negatively so that small positive-going pulses are ineffective. The base is biased over resistors W1, W2 while the junction of diodes D1, D2 is prevented from falling appreciably below earth due to diode D3 conducting. In a further modification, Figs. 7 and 8 (not shown), a series of four clock pulses is employed with each phase-shifted one quarter of a cycle with respect to the next. The output pulse in any stage can be delayed from one to three quarters of a cycle and by employing six stages of three quarters and one of a half a total delay of five cycles can be achieved. Pulse frequency division.-By connecting the output A4 to the input E 1 a division of two may be obtained or in the modification of Fig. 7 (not shown) a division of five may be achieved, the output being taken from any stage.