GB666842A - Improvements in electronic pulse generating devices - Google Patents
Improvements in electronic pulse generating devicesInfo
- Publication number
- GB666842A GB666842A GB37539/46A GB3753946A GB666842A GB 666842 A GB666842 A GB 666842A GB 37539/46 A GB37539/46 A GB 37539/46A GB 3753946 A GB3753946 A GB 3753946A GB 666842 A GB666842 A GB 666842A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- flip
- pulses
- output
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
666,842. Pulse delaying circuits. BRITISH THOMSON-HOUSTON CO., Ltd. Dec. 20, 1946 [Dec. 28, 1945], No. 37539/46. Class 40 (vi). A generator, fed with a series of marker pulses from an oscillator, is arranged to produce an output pulse, delayed from a triggering pulse by a whole number of marker pulses. In the system described, 25 c/s. triggering pulses are derived by employing a 100 kc/s. crystal oscillator to synchronize a pulse generator, the output being fed into a frequency dividing chain. The triggering pulse operates a flip-flop, which, upon restoration, generates a pulse. This pulse is used as a pedestal to raise a selected marker pulse from a suitable point in the divider chain sufficiently to operate a second flip-flop. The operation may be repeated to give a more accurately known delay to the final output pulse. Blocking oscillator 1, synchronized by 100 kc/s. crystal oscillator 2 feeds pulses to the cup and bucket circuit 17 to give a division of five. Further counter circuits 40, 42, 44, 46, 48, 50 in cascade, produce the 25 c/s. square wave 51, which, after differentiation appears as short pulses 70 at the cathode-coupled flip-flop 52. The positive-going short pulses operate the flip-flop to generate the output wave 71 which is differentiated by circuit 82 to feed the wave 72 to valve 86 of the mixer circuit 85. Pulses from counter circuit 44 are applied to valve 87, the output across the common load 92 appearing as in curve 73. Only when the pedestal due to the negative pulse of wave 72 is present, is the output amplitude sufficiently great to trigger a further flip-flop 100 to produce wave 74. After differentiation this wave is combined with marker pulses from circuit 40 of ten times the frequency of those from circuit 44, thus giving the second digit of the delay time. The process is repeated; the output from the final flip-flop 105 being utilized directly without selecting a pulse from the marker chain. The particular pulse from the chain selected by the flip-flops 52, 100 and 103 is controlled by the settings of the respective bias potentiometers 67.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US666842XA | 1945-12-28 | 1945-12-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB666842A true GB666842A (en) | 1952-02-20 |
Family
ID=22071031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB37539/46A Expired GB666842A (en) | 1945-12-28 | 1946-12-20 | Improvements in electronic pulse generating devices |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB666842A (en) |
-
1946
- 1946-12-20 GB GB37539/46A patent/GB666842A/en not_active Expired
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