GB639556A - Improvements in frequency multiplier - Google Patents

Abstract

639,556. Valve circuits. BENDIX AVIATION CORPORATION. March 11, 1947, No. 6800. Convention date, April 30, 1946. [Class 40 (vi)] In a frequency multiplier in which a train of pulses derived from a sinusoidal source are fed to an amplifier having a feedback path including a delay network, the delay period is adjusted to be an integral submultiple of the pulse repetition period so that the output pulse train which may be converted into sinusoidal waveform has a frequency which is a multiple of that of the input source. The Figure shows a pulse generator 14 which is synchronized from a sine wave oscillator 10, the pulses then being fed into an amplifier 20 which has a feedback path associated with it comprising a delay network 24. The delay time of the network is adjusted to be an integral sub-multiple of the pulse repetition period by varying the delay, e.g. by varying capacitors 52, 54 until a dip is obtained on the amplifier output current meter 30. The output pulse train which has a repetition frequency which is a multiple of that of the input pulse train is amplified in a Class C amplifier 34 having an output circuit 42 which is tuned to the required multiple frequency to produce a sinusoidal output voltage across coil 48. The variable capacitors 52, 54 of the delay network and that of the tuned output circuit are preferably ganged so that they can be tuned together to a given output frequency. In a modification, Fig. 2 (not' shown), a blocking circuit is included which is synchronized from the pulse generator and renders the feedback circuit of the amplifier inoperative during any given portion of the input pulse interval. Thus any given pulse of the input pulse train will be followed by a given number of pulses which have been delayed in the delay network and then by an interval before the commencement of the next pulse of the input train.