GB2527685A

GB2527685A - Signal processing apparatus

Info

Publication number: GB2527685A
Application number: GB1514508.9A
Authority: GB
Inventors: Yasuhiro Omori; Yu Minagawa; Tsutomu Motohama
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2013-02-04
Filing date: 2013-02-04
Publication date: 2015-12-30
Anticipated expiration: 2033-02-04
Also published as: KR101665903B1; GB2527685B; GB201514508D0; HK1212039A1; WO2014118984A1; CN105026938B; JPWO2014118984A1; KR20150100821A; JP5936716B2; CN105026938A

Abstract

A 1PPS signal reception unit (101) receives a 1PPS signal. An operation clock generation unit (102) generates an operation clock. A clock deviation measurement unit (103) measures a clock deviation that is a frequency deviation of the operation clock relative to the 1PPS signal. A counter (105) starts a count in accordance with the clock period of the operation clock when the 1PPS signal is inputted. The counter (105) completes one round of count when the count reaches a predetermined count completion value. Thereafter, the counter (105) starts another round of count. A sampling signal generation unit (106) outputs a sampling signal each time the counter (105) completes one round of count. A correction value calculation unit (110) and a change timing calculation unit (111) change, on the basis of the clock deviation, the count completion value of any round, thereby adjusting the output timing of the sampling signal.

Description

Title of Invention: SIGNAL PROCESSING APPARATUS

Technical Field

[0001] The present invention relatcs to a time synchronization control technology. More specifically, the invention relates to a time synchronization control technology in an apparatus that collects electrical quantities of a power transmission line and a busbar.

Background Art

[0002] There is a protection control system that collects electrical quantities (voltage values and current values) of a power transmission line and a husbar at a plurality of locations. Upon detection of abnormality from those electrical quantities, this system immediately cuts off an electric power system, thereby restraining influence of an accident.

In this protection control system, in order to reduce a phase deviation of a collected electrical quantity, signals that arc synchronized among collecting locations are needed as a guide for electrical quantity collection.

In a protection relay apparatus in recent years, a plurality of data collection apparatuses (hereinafter, also referred to as MUs: Merging Units) are connected to one operation apparatus (hereinafter also referred to as an lED: Intelligent Electronic Device) through a local area network (process bus).

Each MU achieves timing synchronization, based on a synchronization signal (1PPS signal: 1 Pulse Per Second signal), thereby making data sampling timings or time stamp values to coincide with one another among the MUs.

Citation List Patent Literature [0003] Patent Literature 1: JP 2001-305177

Summary of Invention

Technical Problem [0004] The reception cycle of the 1PPS signal is an interval of one second.

For this reason, it is necessary for each MU to install a high-precision crystal oscillator (with a frequency deviation of± several ppm) on a clock generation circuit to generate a high-precision clock with a small frequency deviation and thereby restrain a sampling timing deviation among the MtJs to be not more than ± several microseconds per second.

Consequently, there is a problem that a low-cost general-purpose oscillator circuit (with a frequency deviation precision of approximately ± 50 ppm) commonly used in a digital circuit cannot be used, thus leading to an increase in the cost.

[0005] The present invention has been made to solve the problem as described above. It is therefore a main object of the present invention to allow execution of high-precision synchronization control even if a general-purpose oscillator circuit with a frequency deviation of approximately ± 50 ppm is used Solution to Problem [0006] A signal processing apparatus according to the present invention may include: a pulse signal receiving unit that receives a pulse signal for each unit time; an operation clock generation unit that generates an operation clock signal having a tiny clock cycle compared to the unit time; a counter that inputs the pulse signal from the pulse signal receiving unit, inputs the operation clock signal from the operation clock generation unit, starts counting in accordance with the clock cycle of the operation clock signal upon input of the pulse signal, completes one round of counting when counting to a predetermined count completion value is finished, and starts a next round of counting; a control signal output unit that outputs a control signal every time the counter completes one round of counting; a clock deviation measurement unit that inputs the pulse signal from the pulse signal receiving unit, inputs the operation clock signal from the operation clock gcncration unit, and measures a clock deviation being a frequency deviation between the operation clock signal and the pulse signal; and a count completion value change unit that changes a count completion value of any one of rounds, based on the clock deviation measured by the clock deviation measurement unit; wherein when the count completion value of any one of the rounds is changed by the count completion value change unit and when counting to a count completion value after the change is finished, the counter completes said round of counting and starts a next round of counting.

Advantageous Effects of Invention [0007] According to the present invention, a clock deviation is measured, and an output timing of the control signal is adjusted based on the measured clock deviation. Thus, even if a general-purpose oscillator circuit with a frequency deviation of approximately ± 50 ppm is used, high-precision synchronization control may be executed.

Brief Description of Drawings

[0008] [Fig. 1] is a diagram illustrating a configuration example of a data collection apparatus according to Embodiment 1.

[Fig. 2] is a diagram illustrating an operation example of a clock deviation measurement unit according to Embodiment 1.

[Fig. 3] is a diagram explaining a delay in an output timing of a sampling signal duc to a dcviation of an operation clock according to Embodiment 1.

[Fig. 4] is a diagram illustrating an example of operations of a correction value computation unit and a change timing computation unit according to Embodiment 1.

[Fig. 5] is a diagram illustrating a configuration example of a data collection apparatus according to Embodiment 2.

[Fig. 6] is a diagram illustrating a configuration example of a counter modification unit according to Embodiment 2.

[Fig. 7] is a diagram illustrating a configuration example of a counter modification completion notification unit according to Embodiment 2.

[Fig. 8] is a diagram illustrating a hardware configuration example of the data collection apparatus according to each of the first and sccond embodiments.

Description of Embodiments

[0009] Embodiment 1.

In this embodiment, a description will be directed to a data collection apparatus (MU) that computes a correction value for a counter (sampling cycle counter) which determines a cycle for sampling an electrical quantity, according to a clock frequency deviation.

With the data collection apparatus, it is possible to achieve high-precision synchronization, even if a general-purpose oscillator circuit with a frequency deviation of approximately ±50 ppm is used.

Generally, an oscillator used in an embedded device can perform counting just every ten several nanoseconds to every several ten nanoseconds.

In a case where the correction value for the sampling cycle counter is computed using the clock frequency deviation as described above, when the correction value for the counter is in several nanoseconds, there is a problem that adjustment in several nanoseconds cannot be made with the resolution of a crystal oscillator in the MU.

Thus, several times of corrections need to be collectively performed in accordance with the count unit of the crystal oscillator. A mechanism for dynamically modifying the sampling cycle counter during operation of the MU is needed.

In this embodiment, a description will be given about a sampling signal generation method capable of solving the above-mentioned problem and capable of achieving synchronization among the MUs with high precision.

[0010] Fig. 1 is a diagram illustrating a configuration example of a data collection apparatus 100 according to this embodiment.

The data collection apparatus 100 receives a 1PPS signal from an operation apparatus 200, and transmits data indicating a measured electrical quantity to the operation apparatus 200.

The data collection apparatus 100 corresponds to an example of a signal processing apparatus.

The operation apparatus 200, which is an lED, detects abnormality of an electric power system, and restrains influence of an accident by cutting off the system.

A transmission source of the 1PPS signal is not limited to the TED, and a different apparatus including a GPS receiver, for example, may be set to the transmission source.

[0011] A IPPS signal receiving unit 101 in the data collection apparatus 100 receives thc 1PPS signal.

That is, the 1PPS signal receiving unit 101 receives a pulse signal for each second.

The 1PPS signal receiving unit 101 corresponds to an examplc of a pulse signal receiving unit.

[0012] An operation clock generation unit 102 generates an operation clock signal (hereinafter referred to just as an operation clock) for the data collection apparatus 100.

[0013] A clock deviation measurement unit 103 measures a clock deviation that is a frequency deviation between the operation clock for the data collection apparatus 100 and the cycle of the 1PPS signal.

[0014] A measured clock deviation value holding unit 104 holds a measured value of the clock deviation measured by the clock deviation measurement unit 103.

[0015] A sampling cycle counter 105 counts a time interval between timings for electrical quantity sampling.

The sampling cycle counter 105 inputs the 1PPS signal from the 1PPS signal receiving unit 101, inputs the operation clock from the operation clock generation unit 102, starts counting in accordance with the clock cycle of the operation clock upon input of the 1PPS signal, completes one round of counting when counting tO a predetermined count completion value is finished, and starts a next round of counting The sampling cycle counter 105 is also written as a counter 105.

[0016] A sampling signal generation unit 106 generates a sampling signal that is a pulse for indicating a sampling timing, based on a count value of the sampling cycle counter 105.

More specifically, the sampling signal generation unit 106 outputs the sampling signal every time the sampling cycle counter 105 completes one round of counting The sampling signal is a control signal for controlling a timing of measuring an electrical quantity.

The sampling signal generation unit 106 corresponds to an example of a control signal output unit.

[0017] An electrical quantity measurement unit 107 measures the electrical quantity of the electric power system at the timing of the pulse (sampling signal) generated by the sampling signal generation unit 106.

[0018] A data generation unit 108 converts the electrical quantity measured by the electrical quantity measurement unit 107 into digital data in the format of a communication frame that may be transmitted to a local area network (process bus).

[0019] A data transmitting unit 109 transmits the digital data generated by the data generation unit 108 to the operation apparatus 200 through the local area network (process bus).

[0020j A correction value computation unit 110 computes a correction value for the count completion value of the sampling cycle counter 105, based on the clock deviation value held in the measured cock deviation value holding unit 104.

[0021] A change timing computation unit ill computes a timing of applying the correction value computed by the correction value computation unit 110 to thc sampling cycle counter 105, and changes the count completion value to the correction value at the computed timing.

[0022] The correction value computation unit 110 and the change timing computation unit ill change the count completion value of one of rounds, based on the clock deviation measured by the clock deviation measurement unit 103, and adjusts the timing of outputting the sampling signal by the sampling signal generation unit 106.

More specifically, based on the number of times of the rounds to occur per second, the clock deviation, and the clock cycle of the operation clock, the correction value computation unit 110 determines the round targeted for the change, for which the count completion value is to be changed, and the correction value that is a count completion value after the change.

Then, the change timing computation unit 111 changes the count completion value of the round targeted for the change determined by the correction value computation unit 110 to the correction value.

The correction value computation unit 110 and the change timing computation unit 111 correspond to an example of a count completion value change unit.

[0023] A counter initial value holding unit 112 restores the count completion value of the sampling cycle counter 105 to an initial value after the sampling signal has been output.

The counter initial value holding unit 112 corresponds to an example of a count completion value restoration unit.

[0024] Next, an operation example of the data collection apparatus 100 according to this embodiment will be described.

[0025] A 1PPS signal is input to thc data collection apparatus 100 from the operation apparatus 200, using transmission means such as an optical fiber cable or an electrical signal cable.

The I PPS signal is a pulse signal indicating the cycle of one second of absolute time.

The 1PPS signal is received by the 1PPS signal receiving unit 101, and is transferred to each of the clock deviation measurement unit 103 and the sampling cycle counter 105.

[0026] An operation clock for the data collection apparatus 100 is generated by the operation clock generation unit 102, and is transferred to each of the clock deviation measurement unit 103 and the sampling cycle counter 105.

The clock deviation measurement unit 1 03 measures a clock deviation that is a gap between the reception timing of the 1PPS signal and one second counted by the operation clock for the data collection apparatus 100, and a result of measurement is held in the measured clock deviation value holding unit 104.

[0027] An operation example of the clock deviation measurement unit 103 will be described, using Fig. 2.

[0028] When the 1PPS signal is input to the clock deviation measurement unit 103, a counter for 10 milliseconds, which performs counting in accordance with the clock cycle of the operation clock, operates.

Where the operation clock is 80 MHz, for example, counting every 12.5 nanoseconds is performed. Thus, 800000 counts correspond to 10 milliseconds.

Reaching 800000 counts by the counter at the 99th time of this counting of 10 milliseconds corresponds to onc sccond in the measurement of the operation clock of the data collection apparatus 100.

A difference between the one second counted by this operation clock and a IPPS signal reception timing is a measured clock deviation value.

Referring to Fig. 2, a 1PPS signal is received when the counter for 10 milliseconds reaches 798400 counts. Thus, the operation clock counts 20 microseconds behind per second (800000 -798400) >< 12.5 nanoseconds).

This value of 20 microseconds is the measured clock deviation value.

With such an operation, the clock deviation measurement unit 103 measures a clock deviation, which is a discrepancy time per second between the operation clock and the 1PPS signal, and stores a measured deviation value in the measured clock deviation value holding unit 104.

[0029] The sampling cycle counter 105 inputs the 1PPS signal and the operation clock to operate.

Where the AC frequency of the electric power system is 50 Hz, and the number of times of sampling per AC cycle is 80 times, for example, a sampling cycle is 250 microseconds.

In the case of the operation clock of 80 MHz (counting every 12.5 nanoseconds), the cycle of 250 microseconds is attained when the number of times of counting by the sampling cycle counter 105 reaches 20000 counts.

Simultaneously when receiving the 1PPS signal, the sampling cycle counter 105 starts counting, and transmits to the sampling signal generation unit 106 a count value indicating the number of times of counting.

The sampling signal generation unit 106 outputs a sampling signal, when the count value is 20000 (count completion value).

That is, when the count value reaches 20000, which is an upper limit value, the sampling cycle counter 105 completes one round of counting, and starts a next round of counting. The sampling signal generation unit 106 outputs the sampling signal, every time the sampling cycle counter 105 completes one round of counting.

Where the operation clock has no deviation, the sampling signal is output precisely every 250 microseconds. Thus, the sampling signal is output 4000 times per second (in other words, 4000 rounds occur in one second) from receipt of the 1PPS signal to receipt of a subsequent 1PPS signal.

However, the operation clock has a deviation. Thus, actually, it often happens that the sampling signal is not output 4000 times.

If counting of one second by the operation clock is behind from the 1PPS signal by 200 microseconds, for example, the sampling signal is output only 3999 times pcr second, as illustrated in Fig 3 Therefore the sampling signal is not able to be output in the cycle of 250 microseconds.

For this reason, it is necessary to change the count completion value of the sampling cycle counter in order to make correction for compensating the 20 microseconds.

[0030] As a method of the correction, the correction value computation unit first determines a correction value for the count completion value of the sampling cycle counter 105, based on the measured deviation value held in the measured clock deviation value holding unit 104.

If the measured deviation value is 20 microseconds, each sampling cycle is shortened by 5 nanoseconds (20 microseconds/4000 times) . The sampling signal is thereby output in the cycle of 250 microseconds.

l-lowevcr, an operation clock commonly uscd in a digital circuit is that of several MHz to several ten MHz (for counting every ten several nanoseconds to every several ten nanoseconds). Thus, counter adjustment for every several nanoseconds cannot be made. It is therefore necessary to collectively make adjustments of the several nanoseconds.

If the correction value is several nanoseconds, the correction value computation unit 110 determines the correction value for the count completion value and a timing of performing collective correction in accordance with the count unit of the operation clock.

[0031] An example of operations of the correction value computation unit and the change timing computation unit 111 will be described, using Fig. 4.

[0032] Where the operation clock is 80MHz, the sampling cycle counter 105 performs counting every 12.5 nanoseconds. If the correction amount of 5 nanoseconds for each time of sampling is adjusted to the unit of this counting, collective correction of five times (25 nanoseconds) of sampling is to be performed.

That is, the correction value for the sampling cycle counter 105 is 25 nanoseconds, and the correction is performed at a timing for every five sampling cycles (for every 5 rounds).

[0033] The change timing computation unit ill counts the number of times of sampling signal output (number of times of the rounds of the counter 105), and shortens the upper limit value (20000 counts) of the sampling cycle counter 105 by 25 nanoseconds (reduces two counts) after counting four times.

[0034] In this way, the correction value computation unit 110 and the change timing computation unit 111 divide the measured clock deviation value (20 microseconds) by the number of times (4000 times) of the rounds that are to occur in one second, and determine the correction value based on a common multiple (25 nanoseconds) between a divided value (5 nanoseconds) and the clock cycle (12.5 nanoseconds) of the operation clock.

[0035] Ihe sampling signal generation unit 106 outputs the sampling signal when the sampling cycle counter 105 reaches a changed count completion value (19998 counts).

Upon receipt of the sampling signal, the counter initial value holding unit 112 restores the count completion vaiue of the sampling cycle counter to the initial value (20000 counts). Then, the sampling signal is output in the cycle of 20000 counts in each of subsequent four rounds.

As for the five cycles, the sampling signal is output precisely five times during 1.25 milliseconds (250 microseconds)< 5) With the above-mentioned operations, the sampling signal for which the deviation of 20 microseconds has been corrected may be output. The sampling signal may be thereby output the precise number of times (4000 times) per second.

[0036] The electrical quantity measurement unit 107 receives the sampling signal for which the clock deviation has been corrected by the above-mentioned procedure. The electrical quantity measurement unit 107 measures the electrical quantity (such as the current value or the voltage value) of the electric power system.

The data generation unit 108 generates a communication frame having the format whereby the measured electrical quantity may be transmitted to the operation apparatus 200, and transmits the generated communication frame to the operation apparatus 200.

[0037j In this way, according to this embodiment, a correction value for the sampling cycle counter is computed according to a clock deviation, and the count completion value of the sampling cycle counter is dynamically changed, based on the computed correction value. Thus, even if a general-purpose oscillator circuit with a frequency deviation of approximately ±50 ppm is used, a sampling signal may be output at an accurate timing, and an electrical quantity may be measured at an accurate timing.

[0038] The above description has been directed to the example where the sampling signal generation unit 106 outputs the sampling signal when detecting that the count value of the sampling cycle counter 105 has reached the count completion value (2000 counts or 1998 counts).

In place of this arrangement, the sampling cycle counter 105 may output a pulse signal to the sampling signal generation unit 106 when the count value of the sampling cycle counter 105 has reached the count completion value (20000 counts or 19998 counts), and the sampling signal generation unit 106 may output the sampling signal at a timing of inputting the pulse signal from the sampling cycle counter 105.

[0039] The above description has been directed to the example where the operation clock is behind the 1PPS signal. Even if the operation clock is ahead of the 1PPS signal, the sampling signal maybe output at an accurate timing by changing the count completion value in a similar way.

When the operation clock is ahead of the I PPS signal, a count completion value larger than the initial value is set in one of the rounds.

[0040] The above description has been directed to the example where the sampling cycle counter 105 performs incremental counting. Thus, the count completion value is the upper limit value of the sampling cycle counter 105.

However, if the sampling cycle counter 105 performs decremental counting, the count completion value is a lower limit value of the sampling cycle counter.

[00411 This embodiment has described the data collection apparatus that collects an electrical quantity of the electric power system and transmits it to the operation apparatus, and includes the following means: (a) means for receiving a 1PPS signal; (b) means for measuring a frequency deviation between the IPPS signal and an in-apparatus clock; (c) means for holding a measured value of the frequency deviation between tile 1PPS signal and the in-apparatus clock; (d) means for changing a counting range of the samphng cycle counter based on the frequency deviation between the IPPS signal and the in-apparatus clock; (e) means for measuring a timing of changing the counting range of the sampling cycle counter; means for generating a sampling signal based on a count value of the sampling cycle counter; (g) means for holding the initial value of the count value of the sampling cycle counter and restoring the count value of the sampling cycle countcr to the initial value; (Ii) means for measuring the electrical quantity of the electric power system at a timing of the sampling signal; (i) means for digitalizing the electrical quantity into a communication frame; and means for transmitting the communication frame to the operation apparatus.

[0042] Embodiment 2.

In this embodiment, a description will be given about a configuration in which a value of correction for a count completion value of the sampling cycle counter and a timing of the correction are changed during one second.

[0043] Fig. 5 illustrates a configuration example of the data collection apparatus 100 according to this embodiment.

Referring to Fig. 5, a counter modification unit 113 changes an upper limit value of the sampling cycle counter 105.

The counter modification unit 113, together with the correction valuc computation unit 110 and the change timing computation unit 111, correspond to an example of a count completion value change unit.

A counter modification completion notification unit 114 notifies the change of the upper limit value of the sampling cycle counter 105 to each of the change timing computation unit Ill and the counter initial value holding unit 112.

Elements other than the counter modification unit 113 and the counter modification completion notification unit 114 are the same as those illustrated in Fig. 1. Thus, descriptions of the elements other than the counter modification unit 113 and the counter modification completion notification unit 114 will be omitted.

[0044] Next, an operation example of the data collection apparatus 100 according to this embodiment will be described.

[0045] The clock deviation measurement unit 103 measures a clock deviation, and a measured deviation value is stored in the measured clock deviation value holding unit 104, as in Embodiment 1.

The correction value computation unit 110 computes a correction value for the sampling cycle counter 105 based on the clock deviation value, as in Embodiment 1.

Tn this embodiment, the change timing computation unit 111 detcrmines a timing of modifying the counter, based on a counter modification compiction notification from the counter modification completion notification unit 114.

The change timing computation unit 111 sets the correction value for the count completion value of the sampling cycle counter 105 in the counter modification unit 113, and the counter modification unit 113 changes the count complction value of the sampling cycle counter 105.

[0046] Thc correction value computation unit 110 and the change timing computation unit 111 are configured by software processing by a CPU (Central Processing Unit), and the counter modification unit 113 is configured by a register in which the correction value is set, for example.

The counter modification completion notification from the counter modification completion notification unit 114 is implemented by an interrupt to software or polling processing from the software.

[0047] Specifically, the counter modification unit 113 is configured by an 8-bit register as illustrated in Fig. 6.

The most significant bit (bit 7) in Fig. 6 is a bit in which a plus or a minus is sct, and bit 6 to bit 0 are bits in which a correction value is set, for

example.

When the plus is set in the most significant bit (bit 7), the correction value set in the bit 6 to hit 0 is added to the count completion valuc of thc sampling cycle counter 105. When the minus is set in the most significant bit (bit 7), the correction value set in the bit 6 to bit 0 is subtracted from the count completion value of the sampling cycle counter 105.

With this arrangement, the upper limit value of the sampling cycle counter 105 may he changed up to ±127 counts (the upper limit value becomes 127 in decimal number when the bit 6 to the bit 0 are all "1").

When an operation clock is 80 MHz (for counting every 12. 5 nanoseconds), correction in the range from 12. 5 nanoseconds to approximately 1.5 microseconds may be obtained.

[0048] The counter modification completion notification unit 114 may measure a sampling signal output after correction of the count completion value of the sampling cycle counter 105 based on receipt of the sampling signal generated by the sampling single generation unit 106 and the timing of the correction for the sampling cycle counter 105.

For this reason, the counter modification completion notification unit 114 may notify completion of counter modification to each of the change timing computation unit 111 and the counter initial value holding unit 112.

The counter modification completion notification unit 114 is configured by a 1-bit register as illustrated in Fig. 7, for example.

Then, when "1" is in this register, the set value of the counter modification unit 113 is rcflceted on the sampling cycle counter 105 to indicate that correction is completed. When "0" is in this rcgistcr, it indicates that the correction is not completed.

[0049] The change timing computation unit ill and the counter initial value holding unit 112 may determine whether the correction is completed or not by referring to the register in Fig. 7.

When the correction is completed, the change timing computation unit ill sets a correction value in the counter modification unit 113 at a subsequent timing of performing correction.

When the correction is complctcd, the counter initial value holding unit 112 rcstores the count completion value of the sampling cycle counter to an initial value (20000 counts).

The sampling signal is output in a cycle according to the initial value of the count completion value until the count completion value is subsequently changed.

[0050] By the above-mentioned operations, the correction value for the sampling cycle counter 105 may be variably set. Then, even if the correction value obtained as a result of computation based on a clock deviation has a fraction, an amount corresponding to the fraction may be adjusted.

If the correction value computed based on the clock deviation is 23 microseconds, for example, the correction amount for each time is 5.75 nanoseconds.

In the case of 5.75 nanoseconds, adjusting 5.75 nanoseconds in accordancc with counting every 12.5 nanoseconds generates a fraction (the fraction corresponding to 3 microseconds in total when correction of 25 nanoseconds is applied once in five times).

hi order to apply correction to this fraction (3 microseconds) as well, it is necessary to perform correction of 25 nanoseconds once in 33 times, in addition to performing correction of 25 nanoseconds once in five times.

In this example, a value for correction for once in five times and a value for correction for once in 33 times are common to be 25 nanoseconds.

However, the value for correction for once in five times and the value for correction for once in 33 times may be different.

[0051] Inclusion of a mechanism configured to vary a correction value and a correction timing as in this embodiment makes it possible to perform correction even if the correction value has a fraction.

That is, in this embodiment, the correction value computation unit determines a plurality of sets of a round targeted for change for which the counting determination value is to be changed and a counting completion value after the change. Then, the change timing computation unit 111 and the counter modification unit 113 change the count completion value of the round targeted for the change to the count completion value (correction value) after the change, which has been determined for the round targeted for the change.

With such an arrangement, an output timing of a sampling signal may be controlled with high precision.

[0052] This embodiment has described the data collection apparatus that collects an clcctrical quantity of the electric power system and transmits it to the operation apparatus, and includcs thc following means: (a) means for receiving a 1PPS signal; (b) means for measuring a frequency deviation between the 1PPS signal and an in-apparatus clock; (c) means for holding a measured value of the frequency deviation between the 1PPS signal and the in-apparatus clock; (d) means for setting a change value for a counting range of the sampling cycle counter based on the frequency deviation between the I PPS signal and the in-apparatus clock; (e) means for changing the counting range according to the setting of the change value for the counting range of the sampling cycle counter; (f) means for measuring a timing of changing the counting range of the sampling cycle counter; (g) means for generating a sampling signal based on a count value of the sampling cycle counter; (h) means for holding the initial value of the count value of the sampling cycle counter and restoring the count value of the sampling cycle counter to the initial value; (i) means for notifying generation of the sampling signal based on a changed value for the counting range of the sample cycle counter; (j) means for measuring the electrical quantity of the electric power system at a timing of the sampling signal; (k) means for digitalizing the electrical quantity into a communication frame; and (1) means for transmitting the communication frame to the operation apparatus.

[0053J Finally, a hardware configuration example of the data collection apparatus 100 illustrated in each of the first and second embodiments will be described, with reference to Fig. S. The data collection apparatus 100 is a computer, and each element of the data collection apparatus 100 may be implemented by a program.

As the hardware configuration of the data collection apparatus 100, a control device 901, an external storage device 902, a main storage device 903, a communication device 904, an input/output device 905, a clock generation circuit 906, and a counter 907 are connected to a bus.

[0054] The control device 901 is a Cpu that executes the program.

The external storage device 902 is a ROM (Read Only Memory), a flash memory, or a hard disk drive, for example.

The main storage device 903 is a RAM (Random Access Memory).

The measured clock deviation value holding unit 104 is implemented by the main storage device 903, for example.

The communication device 904 corresponds to the physical layer of the 1PPA signal rccciving unit 101 and the data transmitting unit 109.

The input/output device 905 is a mouse, a keyboard, a display device, or the like, for example.

The clock generation circuit 906 includes the crystal oscillator and generates an operation clock signal for the data collection apparatus 100.

The operation clock generation unit 102 is implemented by the clock generation circuit 906.

The sampling cycle counter 105 is implemented by the counter 90L [0055] The programs are usually stored in the external storage device 902, are sequentially read into and executed by the control device 901 after having been loaded into the main storage device 903.

The programs are the ones that execute functions described as ".. .units" illustrated in Figs. 1 to 5 (excluding the operation clock generation unit 102, the measured clock deviation value holding unit 104, the counter modification unit 113, and the counter modification completion notification unit 114. The same applies hereinafter).

Further, an operating system (OS) is also stored in the external storage device 902. At least a part of the OS is loaded into the main storage device 903, and the control device 901 executes the programs that implcmcnt the functions of the "...unit" illustrated in Fig. I, while executing the OS.

In the explanation of Embodiments 1 and 2, information, data, signal values, and variable values that indicate results of processes that are explained as "measurement of, "counting of. . . ", "change of...

"decision of... ", "setting of... ", "designation of, " "computation of...

"determination of... ", "judgment of... " , selection of... ", "generation of ", "inputting of -, "receipt of.... ", etc. are stored in the main storage device 903 as files.

0056] The configuration in Fig. 8 just illustrates the hardware configuration example of the data collection apparatus 100. The hardware configuration of the data collection apparatus 100 is not limited to the configuration in Fig. 8, and a different configuration may be employed.

Reference Signs List [0057] 100: data collection apparatus, 101: 1PPS signal receiving unit, 102: operation clock generation unit, 103: clock deviation measurement unit, 104: measured clock deviation value holding unit, 105: sampling cycle counter, 106: sampling signal generation unit, 107: electrical quantity measurement unit, 108: data generation unit, 109: data transmitting unit, 110: correction value computation unit, Ill: change timing computation unit, 112: counter initial value holding unit, 113: counter modification unit 114: counter modification completion notification unit