KR101665903B1 - Signal processing apparatus - Google Patents

Abstract

The 1PPS signal receiving unit 101 receives the 1PPS signal and the operation clock generating unit 102 generates the operation clock and the clock deviation measuring unit 103 measures the clock deviation which is the frequency deviation of the operation clock with respect to the 1PPS signal do. The counter 105 starts counting in accordance with the clock cycle of the operation clock when the 1PPS signal is input, and when counting up to the predetermined count completion value is completed, the counter 105 completes the count of one round and starts counting the next round . The sampling signal generator 106 outputs a sampling signal every time the counter 105 completes the count of the first round. The correction value calculation unit 110 and the change timing calculation unit 111 adjust the output timing of the sampling signal by changing the count completion value of any one round on the basis of the clock deviation.

Description

[0001] SIGNAL PROCESSING APPARATUS [0002]

TECHNICAL FIELD The present invention relates to a time synchronization control technique, and particularly relates to a time synchronization control technique in an apparatus for collecting electric quantities of a transmission line and a bus.

There is a protection control system that collects electric quantities (voltage value and current value) of a power transmission line or a bus line in a plurality of parts and immediately disconnects the system when an abnormality is detected from these electric quantities, thereby suppressing the spread of accidents.

In this protection control system, a signal synchronized between collection points is required as a reference of collection of electricity quantity in order to reduce phase deviation of the collected electricity quantity.

In recent protection relay devices, a plurality of data collecting devices (hereinafter, also referred to as MUs) are connected to a single computing device (hereinafter also referred to as IED) through a local area network (process bus) Respectively.

Each of the MUs performs timing synchronization based on a synchronization signal (1PPS signal: 1 Pulse Per Second signal), thereby matching the data sampling timing and the time stamp value between the MUs.

(Prior art document)

(Patent Literature)

(Patent Document 1) Japanese Patent Laid-Open No. 2001-305177

The reception period of 1PPS signal is 1 second interval.

For this reason, each MU mounts a high-precision crystal oscillator (frequency deviation: several ppm) on the clock generation circuit to generate a high-precision clock with small frequency deviation, and the deviation of the sampling timing between MUs is ± several μs Or less.

Therefore, a low-cost general-purpose oscillation circuit (frequency deviation precision of about 50 ppm or so) generally used in a digital circuit can not be used, and there is a problem that the cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its main object is to enable high-precision synchronous control even when a general-purpose oscillation circuit having a frequency deviation of about 50 ppm is used.

A signal processing apparatus according to the present invention comprises: a pulse signal receiving unit for receiving a pulse signal at every unit time; an operation clock generating unit for generating an operation clock signal with a small clock period compared with the unit time; And a counter for counting the number of pulses to a predetermined count completion value when the pulse signal is input, A counter for counting the first round when the count is completed and a counter for counting the next round; a control signal output unit for outputting a control signal each time the counter completes the count of the first round; And the operation clock signal is input from the operation clock generation unit A clock deviation measuring unit for measuring a clock deviation, which is a frequency deviation of the operation clock signal with respect to the pulse signal; and a control unit for changing the count completion value of any one round based on the clock deviation measured by the clock deviation measuring unit And when the count completion value of one round has been changed by the count completion value changing unit, when counting up to the count completion value after the change is finished, the counter finishes the count of the round , And starts counting of the next round.

According to the present invention, since the clock deviation is measured and the output timing of the control signal is adjusted based on the measured clock deviation, even if a general-purpose oscillation circuit with a frequency deviation of about 50 ppm is used, have.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram showing a configuration example of a data collection device according to a first embodiment; FIG.
2 is a diagram showing an example of the operation of the clock deviation measuring unit according to the first embodiment;
3 is a view for explaining the delay of the output timing of the sampling signal due to the deviation of the operation clock according to the first embodiment;
4 is a diagram showing an example of the operation of a correction value calculation unit and a change timing calculation unit according to the first embodiment;
5 is a diagram showing a configuration example of a data collection device according to a second embodiment;
6 is a diagram showing a configuration example of a counter changing unit according to the second embodiment;
7 is a diagram showing a configuration example of a counter change completion notification unit according to the second embodiment;
8 is a diagram showing a hardware configuration example of a data collecting apparatus according to the first and second embodiments;

Embodiment Mode 1.

In the present embodiment, a data collecting apparatus MU for calculating a correction value of a counter (sampling period counter) for determining the sampling period of the electricity quantity in accordance with the clock frequency deviation will be described.

This makes it possible to achieve high-precision synchronization even when a general-purpose oscillation circuit having a frequency deviation of about 50 ppm or so is used.

In general, an oscillator used in a built-in device can only count in units of tens to hundreds of milliseconds.

When the correction value of the sampling period counter is calculated from the clock frequency deviation as described above, there is a problem that when the correction value of the counter becomes several units, it is not possible to adjust the resolution to the resolution of the MU crystal oscillator .

Therefore, it is necessary to perform several times of correction in combination with the count unit of the crystal oscillator at a time, and a structure for dynamically changing the sampling period counter during the MU operation is required.

In this embodiment, a sampling signal generating method capable of achieving high-precision synchronization between MUs which solves the above problems will be described.

Fig. 1 shows a configuration example of a data collecting apparatus 100 according to the present embodiment.

The data collecting apparatus 100 receives the 1PPS signal from the calculating apparatus 200 and transmits data indicating the measured quantity of electricity to the calculating apparatus 200. [

The data collecting apparatus 100 corresponds to an example of a signal processing apparatus.

The computing device 200, which is an IED, detects an abnormality in the power system, and inhibits the spread of an accident by blocking the system.

In addition, the transmission source of the 1PPS signal is not limited to the IED, and for example, a separate device having a GPS receiver may be used as the transmission source.

In the data collecting apparatus 100, the 1PPS signal receiving unit 101 receives 1PPS signal.

In other words, the 1PPS signal receiving unit 101 receives the pulse signal every one second.

The 1PPS signal receiving unit 101 corresponds to an example of a pulse signal receiving unit.

The operation clock generation unit 102 generates an operation clock signal (hereinafter simply referred to as an operation clock) of the data collection device 100. [

The clock deviation measuring unit 103 measures a clock deviation which is a frequency deviation of the operation clock of the data collecting apparatus 100 with respect to the period of the 1PPS signal.

The clock deviation measurement value holding unit 104 holds the clock deviation measurement value measured by the clock deviation measurement unit 103. [

The sampling period counter 105 counts the time interval of the timing of sampling the electricity quantity.

The sampling period counter 105 receives a 1PPS signal from the 1PPS signal receiving unit 101 and inputs an operation clock from the operation clock generating unit 102 and outputs a count corresponding to the clock cycle of the operation clock when the 1PPS signal is input And when counting to a predetermined count completion value is finished, the count of the first round is completed and the count of the next round is started.

The sampling period counter 105 is also referred to as a counter 105.

The sampling signal generation unit 106 generates a sampling signal, which is a pulse indicating the sampling timing, from the count value of the sampling period counter 105. [

More specifically, the sampling signal generator 106 outputs a sampling signal every time the sampling period counter 105 completes the count of the first round.

The sampling signal is a control signal for controlling the measurement timing of the electricity quantity.

The sampling signal generation section 106 corresponds to an example of the control signal output section.

The electricity amount measuring unit 107 measures the electricity amount of the power system at the timing of the pulse (sampling signal) generated by the sampling signal generating unit 106.

The data generating unit 108 converts the amount of electricity measured by the electricity amount measuring unit 107 into digital data of a communication frame format that can be transmitted to the local area network (process bus).

The data transmitting unit 109 transmits the digital data generated by the data generating unit 108 to the computing device 200 via the local area network (process bus).

The correction value calculation unit 110 calculates a correction value of the count completion value of the sampling period counter 105 based on the clock deviation value held in the clock deviation measurement value holding unit 104. [

The change timing calculation unit 111 calculates the timing of applying the correction value calculated by the correction value calculation unit 110 to the sampling period counter 105 and changes the count completion value to the correction value at the calculated timing.

The correction value calculation unit 110 and the change timing calculation unit 111 change the count completion value of any one of the rounds based on the clock deviation measured by the clock deviation measurement unit 103, The output timing of the sampling signal by the sampling circuit 106 is adjusted.

More specifically, based on the number of rounds occurring in one second, the clock deviation, and the clock period of the operation clock, the correction value calculation unit 110 calculates the rounds to be changed, And determines a correction value which is a count completion value.

Then, the change timing calculation unit 111 changes the count completion value of the round to be changed determined by the correction value calculation unit 110 to the correction value.

The correction value calculation unit 110 and the change timing calculation unit 111 correspond to examples of the count completion value changing unit.

The counter initial value holding unit 112 returns the count completion value of the sampling period counter 105 to the initial value after outputting the sampling signal.

The counter initial value holding unit 112 corresponds to an example of the counted value restoring unit.

Next, an operation example of the data collecting apparatus 100 according to the present embodiment will be described.

To the data acquisition apparatus 100, a 1PPS signal is input from the computing device 200 by using a transmission means such as an optical fiber cable or an electric signal cable.

The 1PPS signal is a pulse signal representing a period of one second of the absolute time.

The 1PPS signal is received by the 1PPS signal receiving unit 101 and transmitted to the clock deviation measuring unit 103 and the sampling period counter 105.

In the operation clock generation unit 102, an operation clock of the data collection device 100 is generated and transmitted to the clock deviation measurement unit 103 and the sampling period counter 105.

The clock deviation measurement unit 103 measures a clock deviation which is a difference between the reception timing of the 1PPS signal and the 1 second counted by the operation clock of the data collection device 100. The measurement result is stored in the clock deviation measurement value holding unit 104 ).

An example of the operation of the clock deviation measuring unit 103 will be described with reference to FIG.

When the 1PPS signal is input to the clock deviation measuring unit 103, a counter of 10 ms is counted to count according to the clock period of the operation clock.

For example, in the case where the operation clock is 80 MHz, since the count is in units of 12.5 ㎱, the count of 800000 is 10 ms.

When the count of the 10 milliseconds is the 99th count, when the counter reaches 800000 counts, the measurement of the operation clock of the data collecting apparatus 100 becomes 1 second.

The difference between the 1 second counted by the operation clock and the reception timing of the 1PPS signal is the measured value of the clock deviation.

2, since 1 PPS signal is being received at the time when the counter of 10 ms count is 798400 counts, the operation clock counts 20 μs ((800000-798400) × 12.5 kPa) per second, ≪ / RTI >

With this operation, the clock deviation measuring unit 103 measures the clock deviation, which is the deviation time per second of the operation clock with respect to the 1PPS signal, and stores the deviation measurement value in the clock deviation measurement value holding unit 104. [

The sampling period counter 105 operates by inputting the 1PPS signal and the operation clock.

For example, when the AC frequency of the power system is 50 Hz and the number of times of sampling per one AC period is 80, the sampling period becomes 250 μs.

When the operation clock is 80 MHz (a count of 12.5 picoseconds), the count number of the sampling period counter 105 becomes 20000 counts and a cycle of 250 picoseconds.

The sampling period counter 105 starts counting at the same time when the 1PPS signal is input and sends a count value indicating the count number to the sampling signal generation unit 106. [

The sampling signal generator 106 outputs a sampling signal when the count value is 20000 (count completed value).

In other words, when the count value reaches 20000, which is the upper limit value, the sampling period counter 105 completes the count of the first round and starts counting the next round, and the sampling signal generator 106 generates the sampling period counter 105 outputs a sampling signal every time the count of the first round is completed.

When there is no deviation in the operation clock, since the sampling signal is outputted at an interval of 250 mu s, 4000 sampling signals are output in 1 second from the reception of the 1PPS signal to the reception of the next 1PPS signal ( In other words, 4000 rounds occur per second).

However, since there is a deviation in the operation clock, it is often the case that 4,000 sampling signals are not output in practice.

For example, when the count for one second by the operation clock is 20 μs slower than the 1PPS signal, as shown in FIG. 3, the sampling signal is output only 3999 times per second, and the sampling signal is output at a cycle of 250 μs Can not.

Therefore, in order to perform correction for 20 μs, it is necessary to change the count completion value of the sampling period counter.

In the correction method, the correction value calculation unit 110 determines the correction value of the count completion value of the sampling period counter 105 from the deviation measurement value held in the clock deviation measurement value holding unit 104 in advance.

When the deviation measurement value is 20 μs, the sampling signal is output at a cycle of 250 μs by shortening the sampling period by 5 μs (20 μs / 4000 times).

However, since the operation clock generally used in the digital circuit is from several MHz to several tens MHz (a count of several tens to several tens of microseconds), the counter can not be adjusted in units of several millimeters, There is a need.

When the correction value is several, the correction value calculation unit 110 determines the correction value of the count completion value and the timing at which the correction is performed, so as to match the count unit of the operation clock.

An operation example of the correction value calculation unit 110 and the change timing calculation unit 111 will be described with reference to FIG.

When the operation clock is 80 MHz, the count of the sampling period counter 105 is 12.5 picoseconds, and if one correction amount of 5 picoseconds is set to the unit of this count, the correction of five times (25 picoseconds) is performed.

In other words, the correction value of the sampling period counter 105 is 25 kPa, and the correction timing is every 5 sampling cycles (every 5 rounds).

The change timing calculation unit 111 counts the number of times of outputting the sampling signal (the number of rounds of the counter 105) and counts four times, thereby making the upper limit value (20000 count) of the sampling period counter 105 shorter by 25 minutes (Two counts short).

As described above, the correction value calculation unit 110 and the change timing calculation unit 111 divide the measured value (20 占 퐏) of the clock deviation by the number of rounds (4000 times) generated in one second, (25 ns) of the clock cycle (5 ns) of the operation clock and the clock period (12.5 ns) of the operation clock.

The sampling signal generator 106 outputs a sampling signal when the counted completion value (19998 count) of the sampling period counter 105 is changed.

When receiving the sampling signal, the counter initial value holding unit 112 returns the count completion value of the sampling period counter 105 to the initial value (20000 counts), and the next four rounds output the sampling signal at a cycle of 20000 counts do.

In the case of five cycles, five sampling signals are output exactly within 1.25 ms (250 μs × 5).

With the above operation, it is possible to output the sampling signal whose deviation is corrected by 20 μs, and it is possible to output the sampling signal an accurate number of times (4000 times) in one second.

The electricity amount measuring unit 107 receives the sampling signal for which the clock deviation is corrected in the above-described order, and the electricity amount measuring unit 107 measures the electricity amount (current value, voltage value) of the power system.

The data generating unit 108 generates the measured electricity amount in the form of a communication frame that can be transmitted to the computing device 200 and the data transmitting unit 109 transmits the generated communication frame to the computing device 200. [

As described above, according to the present embodiment, since the correction value of the sampling period counter is calculated in accordance with the clock deviation and the count completion value of the sampling period counter is dynamically changed based on the calculated correction value, A sampling signal can be output at a precise timing, and the amount of electricity can be measured at the correct timing even if a general-purpose oscillation circuit having about ± 50 ppm is used.

In the above, an example has been described in which the sampling signal generating section 106 detects that the count value of the sampling period counter 105 has reached the count completion value (20000 count or 19998 count) and outputs a sampling signal .

Instead, when the count value of the sampling period counter 105 reaches the count completion value (20000 count or 19998 count), the sampling period counter 105 outputs the pulse signal to the sampling signal generation unit 106 , The sampling signal generation section 106 may output the sample signal at the timing when the pulse signal from the sampling period counter 105 is input.

Although the example in which the operation clock is slow relative to the 1PPS signal has been described above, the sampling signal can be output at the correct timing by changing the count completion value in the same manner even when the operation clock is fast for 1PPS signal .

When the operation clock is faster than the 1PPS signal, the count completion value is set to a value larger than the initial value in any one round.

In the above description, the sampling period counter 105 counts by an increment. Therefore, the count completed value is the upper limit value of the sampling period counter 105. However, The count completion value becomes the lower limit value of the sampling period counter 105. In the case of counting by the decrement,

As described above, in this embodiment, the data collecting apparatus having the following means for collecting the electricity amount of the power system and transmitting it to the calculating apparatus has been described.

(a) means for receiving a 1PPS signal,

(b) means for measuring the frequency deviation of the 1PPS signal and the clock in the apparatus,

(c) means for maintaining the measured value of the frequency deviation of the 1PPS signal and the clock in the apparatus,

(d) means for changing the count range of the sampling period counter from the frequency deviation of the 1PPS signal and the clock in the apparatus,

(e) means for measuring the timing of changing the count range of the sampling period counter,

(f) means for generating a sampling signal from the count value of the sampling period counter,

(g) means for holding the initial value of the count value of the sampling period counter and returning the count value of the sampling period counter to the initial value,

(h) means for measuring the electrical quantity of the power system at the timing of the sampling signal,

(i) means for digitizing the electricity quantity and configuring it in a communication frame,

(j) means for transmitting a communication frame to the computing device.

Embodiment 2:

In the present embodiment, a description will be given of a configuration for changing the correction value of the count completion value of the sampling period counter 105 and the timing for correcting it to within one second.

Fig. 5 shows a configuration example of the data collection device 100 according to the present embodiment.

In FIG. 5, the counter changing section 113 changes the upper limit value of the sampling period counter 105.

The counter changing section 113 corresponds to an example of the count completed value changing section together with the correction value calculating section 110 and the change timing calculating section 111. [

The counter change completion notification unit 114 notifies the change timing calculation unit 111 and the counter initial value holding unit 112 that the upper limit value of the sampling period counter 105 has been changed.

Elements other than the counter changing unit 113 and the counter changing completion notifying unit 114 are the same as those shown in Fig. 1, and therefore, the description is omitted.

Next, an operation example of the data collecting apparatus 100 according to the present embodiment will be described.

As in Embodiment 1, the clock deviation measuring unit 103 measures the clock deviation, and the deviation measurement value is stored in the clock deviation measurement value holding unit 104. [

The correction value calculation unit 110 calculates the correction value of the sampling period counter 105 from the clock deviation value in the same manner as in the first embodiment.

Here, in the present embodiment, the change timing calculation unit 111 determines the timing of changing the counter based on the counter change completion notification from the counter change completion notification unit 114. [

The change timing calculation unit 111 sets the correction value of the count completion value of the sampling period counter 105 in the counter changing unit 113 and the counter changing unit 113 changes the sampling period counter 105 Change the count completion value.

For example, the correction value calculation unit 110 and the change timing calculation unit 111 are constituted by software processing by a CPU (Central Processing Unit), and the counter changing unit 113 is constituted by a register for setting a correction value .

The counter change completion notification from the counter change completion notification unit 114 is realized by an interrupt to the software or a polling process from the software.

Specifically, the counter changing section 113 is composed of 8-bit registers as shown in FIG.

For example, the most significant bit (bit 7) of FIG. 6 is a bit to which a positive or negative bit is set, and bit 6-bit 0 is a bit to which a correction value is set.

If positive is set in the most significant bit (bit 7), if the correction value set in bit 6-bit 0 is added to the count completed value in the sampling period counter 105 and minus is set in the most significant bit (bit 7) Is subtracted from the count completion value of the sampling period counter 105. [

By doing this, the upper limit value of the sampling period counter 105 can be changed up to a maximum of ± 127 counts (bit 6-bit 0 are all "1", and decimal number becomes 127).

When the operation clock is 80 MHz (a count of 12.5 picoseconds), correction from 12.5 picoseconds to about 1.5 mu s can be performed.

The counter change completion notifying section 114 receives the sampling signal generated by the sampling signal generating section 106 and the correction timing of the sampling period counter 105 so that the count completion value It is possible to measure the sampled signal outputted after the correction.

Therefore, the counter change completion notification section 114 can notify the change timing calculation section 111 and the counter initial value holding section 112 of the completion of the counter change.

The counter change completion notification section 114 is configured as a 1-bit register as shown in Fig. 7, for example.

When this register is "1 ", the set value of the counter changing section 113 is reflected in the sampling period counter 105 to indicate that the correction has been completed. When the value is" 0 & .

The change timing calculation unit 111 and the counter initial value holding unit 112 can determine whether the correction is completed or not by referring to the register in Fig.

The change timing calculation unit 111 sets the correction value in the counter changing unit 113 when the correction is completed and the timing of the next correction is performed.

The counter initial value holding unit 112 returns the count completion value of the sampling period counter 105 to the initial value (20000 counts) when the correction is completed.

The sampling signal is output at the cycle of the initial value of the count completion value until the next count completion value is changed.

By the above operation, the correction value of the sampling period counter 105 can be set to be variable, and as a result of calculating the correction value from the clock deviation, the amount corresponding to the odd number can be adjusted even if there is a fraction.

For example, when the correction value calculated from the clock deviation is 23 mu s, the amount of correction once is 5.75 kPa.

In the case of 5.75 kPa, if a count of 12.5 kPa is met, the odd number appears. (If you apply a correction of 25 kPa in 5 times, you will find a total corresponding to 3 μs.)

In order to apply the correction to this difference (3 μs), it is necessary to perform a correction of 25 μV at 33 times in addition to the correction of 25 μV at 5 times.

In this example, the correction value once every five times is also common to one time of the correction value of 25 times for 33 times, but the correction value for one time may be different from the correction value for one time for 33 times .

As in the present embodiment, by having a structure in which the correction value and the timing for correction are variable, it is possible to perform correction even when there is a difference in the correction value.

In other words, in the present embodiment, the correction value calculation unit 110 determines a plurality of sets of rounds to be changed and a count completion value after the change of the count completion value, and supplies the change timing calculation unit 111 and the counter The changing unit 113 changes the count completion value of the round to be changed to the count completion value (correction value) after the change determined for the round to be changed.

In this way, the output timing of the sampling signal can be controlled with high accuracy.

As described above, in this embodiment, the data collecting apparatus having the following means for collecting the electricity amount of the power system and transmitting it to the calculating apparatus has been described.

(a) means for receiving a 1PPS signal,

(b) means for measuring the frequency deviation of the 1PPS signal and the clock in the apparatus,

(c) means for maintaining the measured value of the frequency deviation of the 1PPS signal and the clock in the apparatus,

(d) means for setting a change value of the count range of the sampling period counter from the frequency deviation of the 1PPS signal and the clock in the apparatus,

(e) means for changing the count range in accordance with setting of the change value of the count range of the sampling period counter,

(f) means for measuring the timing of changing the count range of the sampling period counter,

(g) means for generating a sampling signal from the count value of the sampling period counter,

(h) means for holding the initial value of the count value of the sampling period counter and returning the count value of the sampling period counter to the initial value,

(i) means for notifying that a sampling signal is generated at a value whose count range of the sampling period counter is changed,

(j) means for measuring the electrical quantity of the power system at the timing of the sampling signal,

(k) means for digitizing the electricity quantity and constructing it in a communication frame,

(l) means for transmitting a communication frame to the computing device.

Finally, a hardware configuration example of the data collecting apparatus 100 shown in the first and second embodiments will be described with reference to FIG.

The data collecting apparatus 100 is a computer, and each element of the data collecting apparatus 100 can be realized by a program.

The hardware configuration of the data collecting apparatus 100 includes a control apparatus 901, an external storage apparatus 902, a main storage apparatus 903, a communication apparatus 904, an input / output apparatus 905, a clock generating circuit 906, and a counter 907 are connected.

The control device 901 is a CPU that executes a program.

The external storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, or a hard disk device.

The main storage device 903 is a RAM (Random Access Memory).

The clock deviation measurement value holding unit 104 is implemented by, for example, a main memory device 903.

The communication device 904 corresponds to the physical layers of the 1PPS signal receiving unit 101 and the data transmitting unit 109. [

The input / output device 905 is, for example, a mouse, a keyboard, a display device, or the like.

The clock generation circuit 906 includes a crystal oscillator and generates an operation clock signal of the data collection device 100. [

The operation clock generation unit 102 is realized by a clock generation circuit 906. [

Further, the sampling period counter 105 is realized by the counter 907.

The program is usually stored in the external storage device 902 and loaded into the main storage device 903 and sequentially read and executed by the control device 901. [

The program includes a "to" section (the operation clock generation section 102, the clock deviation measurement value holding section 104, the counter change section 113, the counter change completion notification section 114) shown in FIGS. 1 and 5, , The same applies to the following description).

An operating system (OS) is also stored in the external storage device 902 and at least a part of the OS is loaded into the main storage device 903. The control device 901 executes the OS Quot; to ".

In the description of Embodiments 1 and 2, the "measurement of", "count of", "change of", "determination of", "setting of", "designation of", " Quot ;, " calculation of ", " judgment of, judgment of ", selection of ", generation of ", input of ", reception of & Information and data, signal values, and variable values are stored as a file in the main storage device 903.

8 shows an example of the hardware configuration of the data collecting apparatus 100. The hardware configuration of the data collecting apparatus 100 is not limited to that shown in Fig. 8, and may be any other configuration.

100: Data collection device
101: 1PPS signal receiver
102: Operation clock generating unit
103: clock deviation measuring unit
104: Clock deviation measurement value holding unit
105: Sampling cycle counter
106: Sampling signal generation unit
107:
108:
109: Data transmission unit
110: correction value calculation unit
111: Change timing calculation unit
112: counter initial value holding unit
113: counter changing section
114: counter change completion notification section

Claims (8)

A pulse signal receiving unit for receiving a pulse signal every unit time,
An operation clock generating unit for generating an operation clock signal with a small clock period compared with the unit time;
Wherein the control unit receives the pulse signal from the pulse signal receiving unit, inputs the operation clock signal from the operation clock generating unit, starts counting according to the clock cycle of the operation clock signal upon inputting the pulse signal, A counter that completes the count of the first round when the count to the completion value is finished, and starts the count of the next round,
A control signal output section for outputting a control signal every time the counter completes the count of the first round,
A clock deviation measurer for inputting the pulse signal from the pulse signal receiver, inputting the operation clock signal from the operation clock generator, and measuring a clock deviation which is a frequency deviation of the operation clock signal with respect to the pulse signal,
A count completion value changing unit for changing the count completion value of any one round based on the clock deviation measured by the clock deviation measuring unit,
Lt; / RTI &
When the count completion value of one round is changed by the count completion value changing unit, the counter finishes counting the round until the count completion value after the change, and starts counting the next round doing
And the signal processing apparatus.
The method according to claim 1,
Wherein the signal processing apparatus further comprises a count completion value restoring section for returning the count completion value of the next round of the round in which the count completion value is changed by the count completion value changing section to the predetermined count completion value Processing device.
The method according to claim 1,
Wherein the count completion value changing unit changes the count completion value at a rate of n once (n is an integer of 2 or more) rounds.
The method according to claim 1,
Wherein the count completion value changing unit changes the count completion value based on the number of rounds generated in the unit time, the clock deviation measured by the clock deviation measuring unit, And a count completion value after the change, and changes the count completion value of the determined round to the determined count completion value.
5. The method of claim 4,
Wherein the count completion value changing section divides the clock deviation measured by the clock deviation measuring section by the number of rounds generated in the unit time and calculates a count value based on a common value of a divided value and a clock period of the operating clock signal, A round for changing the completion value and a count completion value after the change are determined.
The method according to claim 1,
Wherein the count completion value changing unit determines a plurality of sets of rounds to be changed and a count completion value after the change of the count completion value and sets the count completion value of the round to be changed to the round To the count completion value.
The method according to claim 1,
Wherein the control signal output unit outputs a sampling signal as the control signal every time the counter completes the count of one round,
The signal processing apparatus further includes an electricity quantity measuring section for inputting the sampling signal outputted from the control signal output section and measuring the electricity quantity at the timing of inputting the sampling signal
And the signal processing apparatus.
8. The method of claim 7,
The pulse signal receiving unit receives 1 PPS (1 Pulse Per Second) signal from an external device,
The signal processing apparatus further includes a data transmitting unit for transmitting data notifying the amount of electricity measured by the electricity amount measuring unit to the computing device
And the signal processing apparatus.

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