CN103309397A - Synchronous sampling method of data acquisition device based on USB - Google Patents
Synchronous sampling method of data acquisition device based on USB Download PDFInfo
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Abstract
The invention relates to synchronous sampling of a data acquisition device, and discloses a synchronous sampling method of a data acquisition device based on a USB. The data acquisition device based on the USB comprises a USB protocol analysis module, a time interval measuring module, a delay phase module, a synchronous trigger module, a clock management frequency division module and a voltage-controlled constant-temperature crystal oscillator. The synchronous sampling method of the data acquisition device based on the USB has the advantages that high speed and flexibility of an FPGA (field programmable gate array) can be fully used, the analysis real time performance is guaranteed, a high-stable clock is provided, the efficiency is high, and a higher application value is provided.
Description
Technical field
The present invention relates to the synchronized sampling of data acquisition equipment, particularly a kind of synchronous sampling method of the data acquisition equipment based on USB.
Background technology
Data acquisition is after the various parameters of measurand (physical quantity, chemistry amount, biomass etc.) are suitably changed by various sensor elements, pass through steps such as signal condition, sampling, quantification, coding, transmission again, deliver to the process that controller carries out data processing or stored record at last.
Nowadays, along with fast development of information technology, the real-time collection of various data and processing have become requisite in present Industry Control.There are various data collecting cards or acquisition system available at present, satisfy producing and the different needs of each side such as scientific research and testing, but owing to the diversity of data source and user's request, can not meet the demands sometimes.Particularly in some applications, need the data of a plurality of passages of high speed acquisition simultaneously, and in order to analyze the mutual relationship between each channel signal of comparison, usually require the collection of all passages synchronously necessary.Existing data acquisition system (DAS) can satisfy the fewer of above-mentioned requirements, and price is very expensive, and volume is bigger, and component is heavier, and it is very inconvenient to use.
The data transmission interface of traditional data acquisition system (DAS) adopts standard serial port or parallel port often at low speed, the general pci bus interface that adopts during high speed.There is following shortcoming in they: though standard serial mouth or parallel port application are fairly simple, message transmission rate was lower at that time; Although pci bus message transmission rate comparison block, hardware design and driving development difficulty were bigger at that time, and this three does not support the function of plug and play.Form the distributed synchronization test macro, this three's hardware development difficulty is very big, the line complexity.And that the usb bus interface has is easy for installation, high bandwidth, be easy to expand, provide the advantages such as power supply up to 5v/500mA, becomes the development trend of modern data transmission gradually.USB1.1 standard interface transfer rate 12Mbps can support 127 devices in theory, is that the USB extender connects a plurality of peripheral equipments by USB HUB, and the maximum length of connection cable is 5 meters (time delay that the cable of transmission signal allows among the USB is 26ns).
How the data sampling engineering of each sampling channel synchronously the realization of a key in the number extraction system is.Synchronous several aspects have been comprised, the firstth, the A-D converter of each sampling channel, need under same clock frequency, move, this clock that is called sampling is synchronous, second, not only the clock of these samplings needs same frequency, and their phase place also needs identical, and this is called the same-phase of sampling clock; The 3rd, synchronous even the sampling clock of different A/D is same frequency, the counting of all A/D also needs same starting point as a reference, and this is called the starting point setting of A/D.
The data acquisition equipment that uses USB to connect is widely used already at industrial circle, but the number that nearly all USB connects is adopted equipment, it all is single casing structure, that is to say, between the number of a plurality of passages is adopted synchronously, depend on the synchronization mechanism of several extraction systems inside, and less relate to simultaneously the sample-synchronous problem between a plurality of USB system that inserts.USB interface-based testing apparatus does not all solve at present the stationary problem that HUB connects many peripheral equipments, Given this, designs and aly can satisfy the synchronous acquisition equipment that is connected on the same HUB.
Summary of the invention
The present invention is directed to the prior art synchronous shortcoming of unresolved many peripheral equipments that connect by USB interface still, the synchronous sampling method of the novel data acquisition equipment based on USB that a kind of synchronous collection that can realize many USB device is provided.
For achieving the above object, the present invention can take following technical proposals:
Synchronous sampling method based on the data acquisition equipment of USB, described data acquisition equipment based on USB comprises usb protocol parsing module, time interval measurement module, time-delay phase module, synchronous trigger module, Clock management frequency division module, voltage-controlled constant-temperature crystal oscillator, wherein
Usb protocol parsing module: receive the USB device signal by the USB port input, parse the first synchronous pulse signal of ms for the reference data to voltage-controlled constant-temperature crystal oscillator compensation;
Time interval measurement module: second pulse signal that first pulse signal of reception usb protocol parsing module output and the process frequency division of voltage-controlled constant-temperature crystal oscillator output obtain, with the rising edge of a pulse of first pulse signal commencing signal as counter, to follow the rising edge of a pulse of second pulse signal of pulse of first pulse signal closely as the end signal of counter, mistiming between calculating commencing signal and the end signal and the pulse number of count pulse calculate time interval Δ t to be measured by mistiming and pulse number;
Time-delay phase module: converse the corresponding delay time that is adjusted frequency signal according to the time interval to be measured, the phase place of the sampling clock on the different USB device is carried out the synchronizing relay adjustment;
The Clock management frequency division module: the frequency signal frequency division that utilizes voltage-controlled constant-temperature crystal oscillator to import obtains second pulse signal, the 3rd pulse signal and is used for the high frequency clock signal of time-delay, and produces count pulse;
Synchronous trigger module: to the frame number code value of SOF bag with trigger synchronously and constantly compare, if identical then produce synchronous triggering signal and realize synchronous triggering to the A/D sampling;
Voltage-controlled constant-temperature crystal oscillator: produce original frequency signal, and as outside input clock.
As preferably, described data acquisition equipment based on USB also comprises CPU processing module, D/A signal conditioning circuit, ADC signal conditioning circuit, wherein,
The CPU processing module: CPU processing module and usb protocol parsing module receive the SOF bag in the USB device signal simultaneously, the CPU processing module triggers constantly synchronously according to frame number code value and trigger request signal deciding in the SOF bag of current reception, and should trigger synchronously and constantly be set to synchronous trigger module, triggering ADC signal conditioning circuit carried out synchronous working after trigger module produced synchronous triggering signal synchronously, after synchronous triggering signal produces, the synchronous trigger module of CPU processing module is set to unactivated state, and synchronous trigger module is set to state of activation again when triggering synchronously next time; Data to the input of time interval measurement module are carried out periodic interval sampling, and carry out kalman filtering and handle to eliminate stochastic error, use time difference method and will be carried out the comparison of the time difference by frequency division or digital clock the 4th pulse signal that obtains and first pulse signal that from the USB device signal, parses generation by measured frequency, average relative frequency difference during twice measurement is Δ f/f=(Δ t2-Δ t1)/(t2-t1), wherein, t1, t2 is the time of twice measurement, Δ t1, Δ t2 for first pulse signal that from the USB device signal, parses generation and the 4th pulse signal that is obtained by frequency division or digital clock by measured frequency at t1, the mistiming that t2 measures constantly is with the Δ f value input D/A signal conditioning circuit that obtains;
The D/A signal conditioning circuit: the Δ f value according to CPU processing module input is adjusted mode of operation, the simulating signal that is converted to is transformed in the input control voltage scope of voltage-controlled constant-temperature crystal oscillator realization to the adjustment of voltage-controlled constant-temperature crystal oscillator output frequency;
The ADC signal conditioning circuit: input single channel/3 road signals are converted into to single channel/3 tunnel simulating signals of CPU processing module output.
As preferably, described usb protocol parsing module, time interval measurement module, time-delay phase module, trigger module, Clock management frequency division module are realized by FPGA synchronously.
As preferably, the mistiming in the described time interval measurement module between commencing signal and the end signal is realized by delay cell and the D-latch of FPGA inside.
The present invention has significant technique effect owing to adopted above technical scheme:
This design solved between the different USB devices the same frequency same-phase and with reference to the sampling problem of starting point, the number that has solved between the different USB device is adopted stationary problem.
Description of drawings
Fig. 1 is the time interval measurement schematic diagram.
Fig. 2 is the structural representation of embodiment 1 described data acquisition equipment.
Fig. 3 is the data structure synoptic diagram of SOF bag.
Embodiment
The present invention is described in further detail below in conjunction with embodiment.
Synchronous sampling method based on the data acquisition equipment of USB, wherein, the structure of data acquisition equipment is as shown in Figure 2: mainly by usb protocol parsing module (producing the ms synchronizing pulse), time interval measurement module, D/A modulate circuit, voltage-controlled constant-temperature crystal oscillator, ADC modulate circuit, CPU processing module, 9 parts such as trigger module, Clock management frequency division module, time-delay phase module are formed synchronously, comprise power management module in addition.
Usb protocol analytical capabilities: receive usb signal, produce the synchronous 1ppms signal of (1.00 ± 0.0005) ms, through the reference data of subsequent treatment conduct to the constant-temperature crystal oscillator compensation.
Time interval measurement function: respectively the time interval of the rising edge of the frequency division 1KHz signal of the 1ppms signal of usb protocol parsing module output and constant-temperature crystal oscillator output is measured, comprise the time interval bigness scale amount of carrying out with the pulse direct count method and utilize and quantize delay method count pulse and 1ppms signal and the nonsynchronous part of constant-temperature crystal oscillator 1KHz signal rising edge are carried out precision measurement, both measure the mistiming that sum is 1ppms signal and constant-temperature crystal oscillator frequency division 1KHz signal rising edge thick essence, and measurement data is delivered to the CPU processing module.
The ms pulse signal rising edge that produces with the usb protocol parsing module is as the counter commencing signal, in one-period, follow the rising edge of VCXO frequency division 1KHz pulse of 1ppms signal closely as the counter end signal, pulse-width is counted, and count results is bigness scale amount data.T1 and T2 are the mistiming that counting clock rising edge and beginning and end signal rising edge do not line up part, this part is the accurate measurement amount, be to realize by delay cell and the D-latch of FPGA inside, as shown in Figure 1, Δ t is the time interval to be measured, the cycle of supposing count pulse is T0, and the step-by-step counting number is n, and then the time interval to be measured can be obtained by following formula: Δ t=n0*T0+T1 – T2.
Under the prerequisite of clock frequency calibration, also need the phase place of clock is adjusted, because the constant back of frequency Δ T fixes, adjust phase place by the time-delay phase shift, principle uses high-frequency signal to being adjusted the frequency signal sampling, converse the delay time that correspondence is adjusted frequency signal according to Δ T, thereby synchronizing relay is adjusted phase place.More than realize, solved same frequency and the same-phase problem of the sampling clock on the different USB devices.
Synchronous trigger module: this part has solved the problem of unified reference point of the sampling of different A/D.Realization is to the synchronous triggering of ADC sampling.
Utilize FPGA high speed and dirigibility, to the usb protocol real time parsing, guaranteed to wrap from SOF the real-time of the millisecond pulse (1ppms) that parses.When the usb protocol frame begins SOF(Start-of-Fram) bag by main frame with every 1.00(± 0.0005) ms(bus at full speed) once standard speed sends.The usb protocol frame begins SOF and comprises a pid field of pointing out to wrap type, and as shown in Figure 3, one 11 frame number field is closelyed follow in the back.USB host connects USB device every 1ms to it and sends the SOF package, and frame number is by 0 beginning, and every SOF bag frame number just increases 1, reaches 2047 and just restarts; CPU processing module and usb protocol parsing module are monitored the SOF bag on the usb bus simultaneously, the CPU processing module can be according to frame number code value in the current SOF bag that monitors when needs trigger synchronously, determine to trigger synchronously and take place constantly (producing AD Reset signal during subsequently how many frame number code values), and this value is set to synchronous trigger module, synchronous trigger module begins the frame number code value of the SOF bag that receives and the value of setting are compared, if the identical synchronous triggering signal that just produces, in case synchronous triggering signal is effective, the CPU processing module is the synchronous trigger module of disable just, and having only needs the just synchronous trigger module of enable again of synchronous triggering signal CPU processing module next time again.
The USB Root Hub can be sent the SOF package when every 1ms.This time between 2 SOF packages, namely be called frame (frame).Though the SOF package is belong to the token package a kind of, has PID form title SOF alone.Usually target device all utilizes the SOF package to come the starting point of identification frame.Transmission when this package is usually used in waiting.Just when the frame of 1ms began, transmission can utilize SOF to activate the effect of transmitting and reaching synchronous transmission when waiting.And when each frame began, SOF can pass to all full speed equipment that connect up.Comprise a frame sign indicating number in this package, it can constantly increase progressively, and is reversed to 0 up to maximal value the time, counts once more again.This frame sign indicating number is the count value of representing frame.End points can be by SOF package in addition synchronously (Sync-pulse), or is used as the reference frame of time with the frame code value.
The synchronous trigger process of AD: PC sends to USB HUB and wants synchronous trigger request, USB HUB can (for example send subsequently at first SOF package (the frame number code value is 100)) in two SOF packet interval to all several device for picking of the present invention and send this request (according to the requirement of usb protocol regulation to transmission delay, before second SOF package sends, all several device for picking of the present invention all should be subjected to the synchronization request that USB HUB sends), several device for picking program of the present invention is defined in advance adds n(as 10 etc. on the frame number code value when receiving synchronization request) as the synchronous trigger condition of AD, next FPGA understands real time parsing SOF package, compare frame number code value and set trigger condition value trigger AD Reset immediately in case satisfy.
CPU processing module: by ARM(Cortex-M4) finishes.The data that the time interval measurement module that receives is sent here are carried out some cycles sampling at interval, and will import data and in ARM, realize kalman filtering processing, eliminate stochastic error, utilize time difference method to record Δ f, to control the voltage digital amount then accurately and send into D/A, also control the working method of D/A simultaneously.Utilize the complementary high stable clock of realizing of 1ppms signal and voltage-controlled constant-temperature crystal oscillator, constant-temperature crystal oscillator has the high characteristics of short-term stability, but grows with time, and frequency and phase place all can produce drift.When it is used for the strict occasion of time synchronized, must timing calibrate it.1ppms parses from the SOF package of USB host-host protocol, has long-time stability, and with both combinations, it is low to produce cost, the clock signal that degree of stability is good.Stable clock signal after the use calibration is realized the synchronous collection clock of all passages, and Sync-pulse is used for the synchronous collection enabling signal of all passages.
CPU also is responsible for the collection of single channel/3 road analog input signals, utilizes synchronous trigger module to start ADC and samples simultaneously; In system when operation,, CPU can arrange the triggering output condition to synchronous trigger module according to customer requirements, satisfies in the time of the synchronous trigger condition of trigger module monitoring in real time synchronously, is exportable ADC starting impulse in case satisfy, thereby realizes the system synchronization collection.
DAC signal conditioning circuit: under the control of synchronizing pulse, 12 bit data are sent into D/A, realize control and write operation to D/A; D/A adjusts mode of operation according to the steering order that ARM sends here, and the analog quantity that is converted to is transformed in the constant-temperature crystal oscillator voltage controling end input control voltage scope through signal conditioning circuit, realizes the adjustment to output frequency.
Voltage-controlled constant-temperature crystal oscillator: have the constant-temperature crystal oscillator of voltage-controlled end, produce original frequency signal.This frequency signal can be exported more high-precision frequency signal through after system compensation, and itself is also as the outside input clock of FPGA.
Clock management frequency division module: utilize the constant-temperature crystal oscillator clock of outside input, produce count pulse and the constant-temperature crystal oscillator frequency division obtains 1KHz signal, 8MHz signal, is used for the high frequency clock of time-delay by FPGA.
Electric power management circuit: produce the required voltage of each module operate as normal.
Data acquisition equipment of the present invention utilize the frame number code value in the SOF package realize between the different data acquisition equipment synchronously.The device that the every ms of USB HUB connects to all sends a SOF package, comprise a pid field of pointing out to wrap type in the SOF bag, one 11 frame number code value is closelyed follow in the back, the frame number code value is stored counts (from 0～2047 variation, and this value is being identical with once sending to each device).
CPU processing module and usb protocol parsing module are monitored the SOF bag on the usb bus simultaneously, the CPU processing module can be according to frame number code value and trigger request signal in the current SOF bag that monitors when main frame will trigger synchronously, determine to trigger synchronously and take place constantly (producing AD Reset signal during subsequently how many frame number code values), and this value is set to synchronous trigger module, trigger module begins to compare to the SOF bag real time parsing of reception and to frame number code value wherein and the value of setting in advance synchronously, if the identical synchronous triggering signal that just produces triggers the ADC synchronous working, after in case synchronous triggering signal produces, the CPU processing module is the synchronous trigger module of disable just, and having only needs the just synchronous trigger module of enable again of synchronous triggering signal CPU processing module next time again.
Several device for picking of the present invention is to carry out calibrating frequency by time difference method.To be obtained the 1ppms signal by frequency division or digital clock by measured frequency, carry out time difference contrast with the 1ppms signal of from the SOF frame bag of usb protocol, resolving generation by counter then, the relative frequency difference of measuring period average for twice is Δ f/f=(Δ t2 – Δ t1)/(t2 – t1), t1 wherein, t2 is the moment of twice measurement; Δ t1, Δ t2 are that t1 constantly, the time difference that t2 surveys are being measured in 1ppms signal and tested (local clock frequency division) the 1ppms pulse of resolving SOF frame packet generation.
Wherein can there be error in Δ t '=Δ t2 – Δ t1 because the SOF frame is resolved the signal jitter that produces, need through optimal estimation Kalman wave filter signal to be carried out the filtering smoothing processing, the Δ t ' that disposes is converted into Δ f value by top formula again and sends into high resolving power D/A transducer, convert the voltage-controlled end of aanalogvoltage control constant voltage temperature control crystal oscillator to, export the stable high frequency stabilization rate that is calibrated.
It is high and resolve the characteristics of long-time stability of the 1ppms signal of SOF packet generation to have taken full advantage of the short-time stability of constant-temperature crystal oscillator, and the two combines and realizes high stable clock with it.
After frequency calibration (Δ T ' is fixing), expect that the synchronized sampling clock also needs the phase place of clock is adjusted, several device for picking of the present invention is adjusted phase place by the time-delay phase shift, principle uses high-frequency signal to being adjusted the frequency signal sampling, converse the delay time that correspondence is adjusted frequency signal according to Δ T, thereby synchronizing relay is adjusted phase place.
Several device for picking of the present invention is designed to a low rate, uses the data collection station of Sigma-Delt ADC, because the maximum 20K of sampling rate does not consider USB circuit delay (time delay that the cable of USB standard code transmission signal allows is 26ns to the maximum) temporarily when calibration synchronized sampling clock;
In a word, the above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (4)
1. synchronous sampling method based on the data acquisition equipment of USB, it is characterized in that, described data acquisition equipment based on USB comprises usb protocol parsing module, time interval measurement module, time-delay phase module, synchronous trigger module, Clock management frequency division module, voltage-controlled constant-temperature crystal oscillator, wherein
Usb protocol parsing module: receive the USB device signal by the USB port input, parse the first synchronous pulse signal of ms for the reference data to voltage-controlled constant-temperature crystal oscillator compensation;
Time interval measurement module: second pulse signal that first pulse signal of reception usb protocol parsing module output and the process frequency division of voltage-controlled constant-temperature crystal oscillator output obtain, with the rising edge of a pulse of first pulse signal commencing signal as counter, to follow the rising edge of a pulse of second pulse signal of pulse of first pulse signal closely as the end signal of counter, mistiming between calculating commencing signal and the end signal and the pulse number of count pulse calculate time interval Δ t to be measured by mistiming and pulse number;
Time-delay phase module: converse the corresponding delay time that is adjusted frequency signal according to the time interval to be measured, the phase place of the sampling clock on the different USB device is carried out the synchronizing relay adjustment;
The Clock management frequency division module: the frequency signal frequency division that utilizes voltage-controlled constant-temperature crystal oscillator to import obtains second pulse signal, the 3rd pulse signal and is used for the high frequency clock signal of time-delay, and produces count pulse;
Synchronous trigger module: to the frame number code value of SOF bag with trigger synchronously and constantly compare, if identical then produce synchronous triggering signal and realize synchronous triggering to the A/D sampling;
Voltage-controlled constant-temperature crystal oscillator: produce original frequency signal, and as outside input clock.
2. the synchronous sampling method of the data acquisition equipment based on USB according to claim 1 is characterized in that described data acquisition equipment based on USB also comprises CPU processing module, D/A signal conditioning circuit, ADC signal conditioning circuit, wherein,
The CPU processing module: CPU processing module and usb protocol parsing module receive the SOF bag in the USB device signal simultaneously, the CPU processing module triggers constantly synchronously according to frame number code value and trigger request signal deciding in the SOF bag of current reception, and should trigger synchronously and constantly be set to synchronous trigger module, triggering ADC signal conditioning circuit carried out synchronous working after trigger module produced synchronous triggering signal synchronously, after synchronous triggering signal produces, the synchronous trigger module of CPU processing module is set to unactivated state, and synchronous trigger module is set to state of activation again when triggering synchronously next time; Data to the input of time interval measurement module are carried out periodic interval sampling, and carry out kalman filtering and handle to eliminate stochastic error, use time difference method and will be carried out the comparison of the time difference by frequency division or digital clock the 4th pulse signal that obtains and first pulse signal that from the USB device signal, parses generation by measured frequency, average relative frequency difference during twice measurement is Δ f/f=(Δ t2-Δ t1)/(t2-t1), wherein, t1, t2 is the time of twice measurement, Δ t1, Δ t2 for first pulse signal that from the USB device signal, parses generation and the 4th pulse signal that is obtained by frequency division or digital clock by measured frequency at t1, the mistiming that t2 measures constantly is with the Δ f value input D/A signal conditioning circuit that obtains;
The D/A signal conditioning circuit: the Δ f value according to CPU processing module input is adjusted mode of operation, the simulating signal that is converted to is transformed in the input control voltage scope of voltage-controlled constant-temperature crystal oscillator realization to the adjustment of voltage-controlled constant-temperature crystal oscillator output frequency;
The ADC signal conditioning circuit: input single channel/3 road signals are converted into to single channel/3 tunnel simulating signals of CPU processing module output.
3. the synchronous sampling method of the data acquisition equipment based on USB according to claim 1, it is characterized in that described usb protocol parsing module, time interval measurement module, time-delay phase module, synchronous trigger module, Clock management frequency division module are realized by FPGA.
4. the synchronous sampling method of the data acquisition equipment based on USB according to claim 3 is characterized in that, the mistiming in the described time interval measurement module between commencing signal and the end signal is realized by delay cell and the D-latch of FPGA inside.
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| CN110492964A (en) * | 2019-08-29 | 2019-11-22 | 广东博智林机器人有限公司 | One kind being based on CLOCK BUFF clock source synchronizing device and method |
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| CN113515107A (en) * | 2021-07-22 | 2021-10-19 | 广州致远电子有限公司 | Acquisition equipment and trigger synchronization method |
| CN113515107B (en) * | 2021-07-22 | 2022-07-08 | 广州致远电子有限公司 | Acquisition equipment and trigger synchronization method |
| CN116578166A (en) * | 2023-07-12 | 2023-08-11 | 国仪量子(合肥)技术有限公司 | Synchronous trigger data acquisition method, storage medium and acquisition equipment |
| CN116578166B (en) * | 2023-07-12 | 2023-09-22 | 国仪量子(合肥)技术有限公司 | Synchronous trigger data acquisition method, storage medium and acquisition equipment |
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