CN109814835A - A kind of interval equipartition device and IP kernel based on FPGA - Google Patents
A kind of interval equipartition device and IP kernel based on FPGA Download PDFInfo
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Abstract
This application discloses a kind of interval equipartition device and IP kernel based on FPGA, comprising: gap count module carries out counting output for treating respectively spacing value；What is connect with gap count module divides equally computing module, for determining equal score value and correction value；It is being connect with respectively computing module and using correction value as the amendment counting module of mould, counting output is carried out for generating corrected impulse, and to corrected impulse, to realize that the deviation generated to respectively process is modified；It is connect with respectively computing module and amendment counting module and divide equally counting module using equal score value as mould, for generating respectively pulse, and counting output is carried out to respectively pulse；Wherein, gap count module, amendment counting module and respectively counting module is what the counter based on FPGA construct, respectively computing module is what the divider based on FPGA constructed.The application can effectively improve the time and divide equally precision, and without occupying excess resource.
Description
Technical field
The present invention relates to simultaneous techniques field, in particular to a kind of interval equipartition device and IP kernel based on FPGA.
Background technique
With the development of computer and smart machine, the rate of network communication is getting faster, equipment in many application scenarios
Between group-net communication, clock synchronization it is synchronous required precision it is higher and higher, especially measuring and controlling the fields such as application.Interval is divided equally
It is real-time pulse spacing value to be divided into D parts, and guarantee stable and precision, is common function in the fields such as observing and controlling, communication.
Interval equal distribution function mostly uses greatly hardware resource or hardware resource is needed to participate in realizing at present, but its implementation,
It is difficult to ensure that precision respectively or implementation are excessively complicated, resource occupation is more.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of interval equipartition device and IP kernel based on FPGA, Neng Gouyou
Effect improves the time and divides equally precision, and without occupying excess resource.Its concrete scheme is as follows:
In a first aspect, this application discloses a kind of interval equipartition device based on FPGA, comprising:
Gap count module carries out counting output for treating respectively spacing value；
What is connect with the gap count module divides equally computing module, for determining equal score value and correction value；
With it is described divide equally computing module connect and using the correction value as the amendment counting module of mould, for generate correct
Pulse, and counting output is carried out to the corrected impulse, to realize that the deviation generated to respectively process is modified；
Connect with the respectively computing module and the amendment counting module and respectively counting using the equal score value as mould
Digital-to-analogue block divides equally pulse for generating, and carries out counting output to the respectively pulse；
Wherein, the gap count module, the amendment counting module and the counting module of dividing equally are based on FPGA
Counter building, it is described divide equally computing module be based on FPGA divider building.
Optionally, the gap count module is specifically used for when second pulse signal arrives, by itself count value at this time
It is determined as the spacing value to be divided equally of current second, then exports the spacing value to be divided equally, and be zeroed out and count again.
Optionally, it is described divide equally computing module, specifically for by the gap count module output described in wait divide equally between
Divide equally number divided by preset every value, obtains the first remainder and the first quotient as equal score value；By the spacing value to be divided equally
Divided by first remainder, the second remainder and the second quotient as correction value are obtained.
Optionally, the amendment counting module, is specifically used in clock increasing process, be greater than when the count value of itself or
Equal to the correction value, then New count of laying equal stress on is reset, and export corrected impulse.
Optionally, described to divide equally counting module, in clock increasing process, when getting the amendment counting module
When the corrected impulse of output, then stop counting within a corresponding clock cycle；When the count value of itself is greater than or waits
In the equal score value, then New count of laying equal stress on is reset, and export and divide equally pulse.
Optionally, described to divide equally counting module, it is also used to reset New count of laying equal stress on, simultaneously when second pulse signal arrives
Pulse is divided equally in output.
Optionally, the interval equipartition device, further includes:
Parameter updating unit, for being updated to the number of dividing equally.
Optionally, the parameter updating unit is specifically used for through preset parameter input interface, and get parms update letter
Breath is updated the number of dividing equally using the parameter more new information.
Second aspect, this application discloses a kind of IP kernel, the IP kernel is to carry out to aforementioned disclosed interval equipartition device
It is obtained after encapsulation.
As it can be seen that the application introduces amendment counting module, for generating corrected impulse, and corrected impulse count defeated
Out, to realize that the deviation generated to respectively process is modified, so that improving the time divides equally precision, also, divide equally interval dress
Set be based in FPGA counter and divider construct, be both easily achieved in this way, need not also occupy excessive resource.It is comprehensive
On, the application can effectively improve the time and divide equally precision, and without occupying excess resource.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of interval equipartition device structural schematic diagram based on FPGA disclosed by the invention；
Fig. 2 is a kind of specifically interval equipartition device structural schematic diagram based on FPGA disclosed by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Currently, with the development of computer and smart machine, the rate of network communication is getting faster, in many application scenarios
The synchronous required precision of group-net communication, clock synchronization is higher and higher between equipment, is especially measuring and controlling the fields such as application.Interval
It is respectively real-time pulse spacing value to be divided into D parts, and guarantee stable and precision, is common in the fields such as observing and controlling, communication
Function.At present interval equal distribution function mostly use hardware resource greatly or need hardware resource participate in realize, but its implementation or
It is difficult to ensure that precision respectively or implementation are excessively complicated, resource occupation is more.For this purpose, this application provides a kind of bases
In the interval equipartition device of FPGA, can either effectively improve the time divides equally precision, without occupying excess resource.
It is shown in Figure 1, the embodiment of the invention discloses a kind of interval equipartition device based on FPGA, comprising:
Gap count module 11 carries out counting output for treating respectively spacing value；
What is connect with the gap count module 11 divides equally computing module 12, for determining equal score value and correction value；
With it is described divide equally computing module 12 connect and using the correction value as the amendment counting module 13 of mould, for generating
Corrected impulse, and counting output is carried out to the corrected impulse, to realize that the deviation generated to respectively process is modified；
With it is described divide equally computing module 12 and it is described amendment counting module 13 connect and using the equal score value as the equal of mould
Divide counting module 14, divide equally pulse for generating, and counting output is carried out to the respectively pulse；
Wherein, the gap count module 11, the amendment counting module 13 and the counting module 14 of dividing equally are base
It is constructed in the counter of FPGA, the computing module 12 of dividing equally is the divider building based on FPGA.
As it can be seen that the embodiment of the present application introduces amendment counting module, carried out for generating corrected impulse, and to corrected impulse
Output is counted, to realize that the deviation generated to respectively process is modified, so that improving the time divides equally precision, also, is divided equally
Escapement be based in FPGA counter and divider construct, be both easily achieved, need not also occupy excessive in this way
Resource.To sum up, the embodiment of the present application can effectively improve the time and divide equally precision, and without occupying excess resource.
It should be pointed out that the interval equipartition device in the present embodiment can be applied to TT&C system or communication system etc. pair
In the more demanding system of timing tracking accuracy.
In the following, being dispensed so that GPS second interval common in TT&C system is divided equally in real time as an example to the interval in the present embodiment
It sets and is specifically described.
Shown in Figure 2, in the present embodiment, the gap count module 11 specifically can be used for as second pulse signal s_
When pulse arrives, itself count value at this time is determined as to the spacing value S to be divided equally of current second, then output is described wait divide equally
Spacing value, and be zeroed out and count again.Thus start next second gap count, so recycle, to realize the reality at interval
Shi Tongji output.
It is described divide equally computing module 12, specifically can be used for exporting the gap count module 11 described in wait divide equally between
Divide equally number D divided by preset every value S, obtains the first remainder R and the first quotient Q as equal score value；Will it is described wait divide equally between
Every value S divided by first remainder R, the second remainder C and the second quotient M as correction value are obtained.Formula includes: accordingly
S=D*Q+R； (1)
S=R*M+C； (2)
In formula, S indicates that the spacing value to be divided equally of the gap count module output, D indicate described and divide equally number, Q
Indicate that first quotient for being used as equal score value, R indicate that first remainder, M indicate the second quotient for being used as correction value, C table
Show second remainder.
As it can be seen that dividing equally computing module in the present embodiment has carried out two-wheeled division arithmetic, why two-wheeled division fortune is carried out
Calculate, be since it is considered that if using Q be the counting interval carry out count output respectively pulse, the error of R clock cycle can be generated,
In order to reduce error, the present embodiment has carried out the second wheel division arithmetic, to realize that remainder compensates, to reduce error, increases
Divide equally precision.
The amendment counting module 13 is specifically used in clock increasing process, when the count value of itself is greater than or equal to
The correction value M then resets New count of laying equal stress on, and exports corrected impulse m_pulse.
It is described to divide equally counting module 14, in clock increasing process, when getting, the amendment counting module 13 to be defeated
When the corrected impulse m_pulse out, then stop counting within a corresponding clock cycle；When the count value of itself is greater than
Or be equal to the equal score value Q, then New count of laying equal stress on is reset, and export and divide equally pulse a_pulse.
In order to guarantee precision, prevent error accumulation, it is necessary to for it is per second the last one divide equally pulse carry out specially treated,
Specifically, described divide equally counting module 14, it is also used to reset New count of laying equal stress on when second pulse signal arrives, while exporting equal
Sectors punching.
Further, the interval equipartition device in the present embodiment can also include:
Parameter updating unit, for being updated to the number D that divides equally.
Wherein, the parameter updating unit specifically can be used for through preset parameter input interface, and get parms update
Information is updated the number of dividing equally using the parameter more new information.
It should be pointed out that the update needs of D value are uniformly processed at pulse per second (PPS) in the present embodiment.
, can according to demand and actual conditions in addition, the update for Q value and M value, first within the current second is divided equally
It updates before pulse, or is updated at next pulse per second (PPS).
Above-mentioned technical proposal in through this embodiment can will divide equally the first remainder R calculated and balancedly be inserted into
During point, to ensure that at interval of the interior precision divided equally, and error does not add up.
Error analysis is carried out to above-mentioned result of dividing equally below:
Interval divides equally process and resets counting at each pulse per second (PPS), if opening to pulse number is divided equally from initial pulse per second (PPS)
Begin to be 0,1,2,3 ..., D-1, D divides equally pulse in total, then ideally divides equally position of the pulse in second interval n-th
Are as follows:
And press above-mentioned interval equal division methodology, n-th divide equally position of the pulse in second interval are as follows:
Correspondingly, its deviation is: Deviation=Pos2-Pos1；
By by the S in formula (1) alternate form (3), by the S in formula (2) alternate form (4), by Deviation abbreviation at:
It can be obtained by further analyzing: whenWhen greater than 0,When its etc.
When 0,
It can be seen that error corresponding with the equal offshoot program in above-mentioned interval, is no more than a clock cycle in a negative direction,
It is no more than in positive directionIn actual use, relevant parameter can be designed according to the actual situation.
Further, disclosed herein as well is a kind of IP kernel, the IP kernel is to divide equally to interval disclosed in previous embodiment
Device obtains after being packaged.Wherein, it can refer in previous embodiment and disclose about the specific configuration of the interval equipartition device
Corresponding contents, no longer repeated herein.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
A kind of interval equipartition device and IP kernel based on FPGA provided by the present invention is described in detail above, this
Apply that a specific example illustrates the principle and implementation of the invention in text, the explanation of above example is only intended to
It facilitates the understanding of the method and its core concept of the invention；At the same time, for those skilled in the art, think of according to the present invention
Think, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as pair
Limitation of the invention.
Claims (9)
1. a kind of interval equipartition device based on FPGA characterized by comprising
Gap count module carries out counting output for treating respectively spacing value；
What is connect with the gap count module divides equally computing module, for determining equal score value and correction value；
With it is described divide equally computing module connect and using the correction value as the amendment counting module of mould, for generate correct arteries and veins
Punching, and counting output is carried out to the corrected impulse, to realize that the deviation generated to respectively process is modified；
With it is described divide equally computing module and it is described amendment counting module connect and using the equal score value as mould respectively count module
Block divides equally pulse for generating, and carries out counting output to the respectively pulse；
Wherein, the gap count module, the amendment counting module and the counting module of dividing equally are based on FPGA
Number device building, the computing module of dividing equally is the divider building based on FPGA.
2. the interval equipartition device according to claim 1 based on FPGA, which is characterized in that
The gap count module is specifically used for being determined as itself count value at this time currently when second pulse signal arrives
Then the spacing value to be divided equally of second exports the spacing value to be divided equally, and is zeroed out and counts again.
3. the interval equipartition device according to claim 2 based on FPGA, which is characterized in that
It is described to divide equally computing module, specifically for by spacing value to be divided equally described in gap count module output divided by default
Divide equally number, obtain the first remainder and the first quotient as equal score value；By the spacing value to be divided equally divided by described first
Remainder obtains the second remainder and the second quotient as correction value.
4. the interval equipartition device according to claim 3 based on FPGA, which is characterized in that
The amendment counting module is specifically used in clock increasing process, when the count value of itself is greater than or equal to described repair
Positive value then resets New count of laying equal stress on, and exports corrected impulse.
5. the interval equipartition device according to claim 4 based on FPGA, which is characterized in that
It is described to divide equally counting module, in clock increasing process, when getting described in the amendment counting module exports
When corrected impulse, then stop counting within a corresponding clock cycle；When the count value of itself is greater than or equal to described divide equally
Value then resets New count of laying equal stress on, and exports and divide equally pulse.
6. the interval equipartition device according to claim 5 based on FPGA, which is characterized in that it is described to divide equally counting module,
It is also used to reset New count of laying equal stress on, while exporting and dividing equally pulse when second pulse signal arrives.
7. according to the described in any item interval equipartition devices based on FPGA of claim 3 to 6, which is characterized in that further include:
Parameter updating unit, for being updated to the number of dividing equally.
8. the interval equipartition device according to claim 7 based on FPGA, which is characterized in that
The parameter updating unit is specifically used for through preset parameter input interface, and get parms more new information, using described
Parameter more new information is updated the number of dividing equally.
9. a kind of IP kernel, which is characterized in that the IP kernel is to interval equipartition device as claimed in any one of claims 1 to 8
It is obtained after being packaged.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492966A (en) * | 2019-09-12 | 2019-11-22 | 积成电子股份有限公司 | A kind of method for synchronizing time of distribution protective relaying device |
| CN111211779A (en) * | 2019-12-31 | 2020-05-29 | 苏州浪潮智能科技有限公司 | FPGA-based interval uniform design method and device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4442547A (en) * | 1982-09-01 | 1984-04-10 | Rca Corporation | Counter arrangement useful in a frequency locked loop tuning system for measuring the frequency of a local oscillator signal |
| CN102035472A (en) * | 2010-10-29 | 2011-04-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable digital frequency multiplier |
| CN103713552A (en) * | 2013-12-23 | 2014-04-09 | 国电南瑞科技股份有限公司 | Self-adaptive dynamic synchronous sampling control device and method based on pulse per second |
| CN104991441A (en) * | 2015-07-22 | 2015-10-21 | 广州供电局有限公司 | GPS synchronous time giving circuit |
| US20160112034A1 (en) * | 2012-06-29 | 2016-04-21 | Renesas Electronics Corporation | Clock correction circuit and clock correction method |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
| CN107577140A (en) * | 2017-09-14 | 2018-01-12 | 国电南瑞科技股份有限公司 | A kind of synchronised clock management module based on FPGA |
-
2019
- 2019-01-30 CN CN201910092904.4A patent/CN109814835B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4442547A (en) * | 1982-09-01 | 1984-04-10 | Rca Corporation | Counter arrangement useful in a frequency locked loop tuning system for measuring the frequency of a local oscillator signal |
| CN102035472A (en) * | 2010-10-29 | 2011-04-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable digital frequency multiplier |
| US20160112034A1 (en) * | 2012-06-29 | 2016-04-21 | Renesas Electronics Corporation | Clock correction circuit and clock correction method |
| CN103713552A (en) * | 2013-12-23 | 2014-04-09 | 国电南瑞科技股份有限公司 | Self-adaptive dynamic synchronous sampling control device and method based on pulse per second |
| CN104991441A (en) * | 2015-07-22 | 2015-10-21 | 广州供电局有限公司 | GPS synchronous time giving circuit |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
| CN107577140A (en) * | 2017-09-14 | 2018-01-12 | 国电南瑞科技股份有限公司 | A kind of synchronised clock management module based on FPGA |
Non-Patent Citations (2)
| Title |
|---|
| 于洋: "基于FPGA高速时间交织ADC校准与研究", 《中国优秀硕士学位论文全文数据库-信息科技辑》 * |
| 高嵩: "基于FPGA的多道脉冲幅度分析器研究", 《中国优秀硕士学位论文全文数据库-信息科技辑》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492966A (en) * | 2019-09-12 | 2019-11-22 | 积成电子股份有限公司 | A kind of method for synchronizing time of distribution protective relaying device |
| CN111211779A (en) * | 2019-12-31 | 2020-05-29 | 苏州浪潮智能科技有限公司 | FPGA-based interval uniform design method and device |
| WO2021135303A1 (en) * | 2019-12-31 | 2021-07-08 | 苏州浪潮智能科技有限公司 | Fpga-based design method and device for equally dividing interval |
| CN111211779B (en) * | 2019-12-31 | 2023-01-06 | 苏州浪潮智能科技有限公司 | FPGA-based interval uniform design method and device |
| US11923863B2 (en) | 2019-12-31 | 2024-03-05 | Inspur Suzhou Intelligent Technology Co., Ltd. | FPGA-based design method and device for equally dividing interval |
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