CN109814835B - FPGA-based interval uniform distribution device and IP core - Google Patents
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- 238000012935 Averaging Methods 0.000 description 23
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Abstract
The application discloses interval equipartition device and IP core based on FPGA includes: the interval counting module is used for counting and outputting the interval values to be averaged; the average calculating module is connected with the interval counting module and is used for determining an average value and a correction value; the correction counting module is connected with the equipartition calculating module and takes the correction value as a module and is used for generating correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the equipartition process; the equipartition counting module is connected with the equipartition calculating module and the correction counting module and takes the equipartition value as a module and is used for generating equipartition pulses and counting and outputting the equipartition pulses; the interval counting module, the correction counting module and the equipartition counting module are all constructed by counters based on an FPGA, and the equipartition calculating module is constructed by dividers based on the FPGA. The time sharing precision can be effectively improved, and excessive resources do not need to be occupied.
Description
Technical Field
The invention relates to the technical field of synchronization, in particular to an interval equalizing device based on an FPGA and an IP core.
Background
With the development of computers and intelligent devices, the speed of network communication is faster and faster, and the precision requirements of networking communication and time synchronization among devices in many application scenarios are higher and higher, especially in the fields of measurement and control application and the like. The interval equalization is to equalize the real-time pulse interval value into D parts, and ensure the stability and precision, and is a common function in the fields of measurement and control, communication and the like.
At present, most of the interval sharing functions are realized by adopting hardware resources or needing the hardware resources to participate, but the realization mode of the interval sharing functions is difficult to ensure the sharing precision or too complex and occupies more resources.
Disclosure of Invention
In view of this, the present invention provides an interval averaging device and an IP core based on an FPGA, which can effectively improve the time averaging precision without occupying too many resources. The specific scheme is as follows:
in a first aspect, the present application discloses an interval equalizing device based on an FPGA, comprising:
the interval counting module is used for counting and outputting the interval values to be averaged;
the average calculating module is connected with the interval counting module and is used for determining an average value and a correction value;
the correction counting module is connected with the equipartition calculating module and takes the correction value as a module and is used for generating a correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the equipartition process;
the equipartition counting module is connected with the equipartition calculating module and the correction counting module and takes the equipartition value as a module and is used for generating equipartition pulses and counting and outputting the equipartition pulses;
the interval counting module, the correction counting module and the equipartition counting module are all constructed by counters based on an FPGA, and the equipartition calculating module is constructed by dividers based on the FPGA.
Optionally, the interval counting module is specifically configured to, when the pulse signal of a second arrives, determine a count value of the interval counting module at this time as an interval value to be averaged of the current second, then output the interval value to be averaged, and perform zero clearing and recounting.
Optionally, the average calculating module is specifically configured to divide the interval value to be averaged output by the interval counting module by a preset number of average portions to obtain a first remainder and a first quotient value serving as an average value; and dividing the interval value to be averaged by the first remainder to obtain a second remainder and a second quotient value used as a correction value.
Optionally, the modified counting module is specifically configured to clear and recount the clock pulse when the count value of the modified counting module is greater than or equal to the modified value in the clock incrementing process, and output the modified pulse.
Optionally, the even counting module is configured to, in a clock incrementing process, stop counting within a corresponding clock period when the correction pulse output by the correction counting module is obtained; and when the self count value is larger than or equal to the average value, resetting and recounting, and outputting an average pulse.
Optionally, the averaging counting module is further configured to clear and recount when the pulse per second signal arrives, and output an averaging pulse at the same time.
Optionally, the interval equalizing device further includes:
and the parameter updating unit is used for updating the share number.
Optionally, the parameter updating unit is specifically configured to obtain parameter updating information through a preset parameter input interface, and update the number of equal shares by using the parameter updating information.
In a second aspect, the present application discloses an IP core obtained by encapsulating the interval equalization apparatus disclosed above.
Therefore, the correction counting module is introduced for generating the correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the equipartition process, so that the time equipartition precision is improved, and the equipartition spacing device is constructed based on a counter and a divider in an FPGA (field programmable gate array), so that the time equipartition spacing device is easy to realize and does not occupy too much resources. In conclusion, the time sharing precision can be effectively improved, and excessive resources do not need to be occupied.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an interval equalizing device based on an FPGA according to the present invention;
fig. 2 is a schematic structural diagram of a specific interval equalizing device based on an FPGA.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Currently, with the development of computers and intelligent devices, the speed of network communication is faster and faster, and the precision requirements of networking communication and time synchronization between devices in many application scenarios are higher and higher, especially in the fields of measurement and control application. The interval equalization is to equalize the real-time pulse interval value into D parts, and ensure the stability and precision, and is a common function in the fields of measurement and control, communication and the like. At present, most of the interval sharing functions are realized by adopting hardware resources or needing the hardware resources to participate, but the realization mode of the interval sharing functions is difficult to ensure the sharing precision or too complex and occupies more resources. Therefore, the interval equally-dividing device based on the FPGA can effectively improve time equally-dividing precision and does not need to occupy excessive resources.
Referring to fig. 1, an embodiment of the present invention discloses an interval equalizing device based on an FPGA, including:
the interval counting module 11 is used for counting and outputting the interval values to be averaged;
the average calculating module 12 is connected with the interval counting module 11 and is used for determining an average value and a correction value;
the correction counting module 13 is connected with the equipartition calculating module 12 and takes the correction value as a module and is used for generating a correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the equipartition process;
the equipartition counting module 14 is connected with the equipartition calculating module 12 and the correction counting module 13 and takes the equipartition value as a module and is used for generating equipartition pulses and counting and outputting the equipartition pulses;
the interval counting module 11, the correction counting module 13 and the division counting module 14 are all constructed by counters based on an FPGA, and the division calculating module 12 is constructed by dividers based on the FPGA.
Therefore, the correction counting module is introduced in the embodiment of the application and used for generating the correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the averaging process, so that the time averaging precision is improved, and the averaging interval device is constructed based on the counter and the divider in the FPGA, so that the time averaging interval device is easy to implement and does not occupy too much resources. In conclusion, the time sharing precision can be effectively improved, and excessive resources do not need to be occupied.
It should be noted that the interval equalizing device in this embodiment may be applied to a measurement and control system or a communication system, etc. which has a high requirement on the time synchronization accuracy.
Next, taking the GPS second interval real-time averaging commonly used in the measurement and control system as an example, the interval averaging device in this embodiment is specifically described.
Referring to fig. 2, in this embodiment, the interval counting module 11 may be specifically configured to, when the pulse signal S _ pulse of a second arrives, determine a count value of the interval counting module at this time as an interval value S to be averaged of a current second, then output the interval value to be averaged, and perform zero clearing and recounting. Thereby starting the interval count for the next second and so forth, to achieve a real-time statistical output of the intervals.
The average calculating module 12 is specifically configured to divide the interval value S to be averaged output by the interval counting module 11 by a preset number of average portions D to obtain a first remainder R and a first quotient Q serving as an average value; and dividing the interval value S to be averaged by the first remainder R to obtain a second remainder C and a second quotient value M serving as a correction value. The corresponding formula includes:
S＝D*Q+R； (1)
S＝R*M+C； (2)
wherein S represents the interval value to be averaged output by the interval counting module, D represents the number of averaging copies, Q represents the first quotient value used as an averaging value, R represents the first remainder, M represents a second quotient value used as a correction value, and C represents the second remainder.
It can be seen that, in the present embodiment, the two-round division operation is performed by the averaging calculation module, because it is considered that if the averaging pulse is counted and output with Q as the counting interval, an error of R clock cycles is generated, and in order to reduce the error, the second round of division operation is performed in the present embodiment to implement remainder compensation, thereby reducing the error and increasing the averaging precision.
The correction counting module 13 is specifically configured to clear and count again when the count value of the correction counting module is greater than or equal to the correction value M in the clock increment process, and output a correction pulse M _ pulse.
The equipartition counting module 14 is configured to, in a clock incrementing process, stop counting in a corresponding clock cycle when the correction pulse m _ pulse output by the correction counting module 13 is acquired; and when the self count value is larger than or equal to the average value Q, clearing and recounting, and outputting an average pulse a _ pulse.
In order to ensure the precision and prevent the accumulation of errors, it is necessary to perform special processing on the last equipartition pulse per second, and specifically, the equipartition counting module 14 is further configured to zero and recount the last equipartition pulse per second when the pulse per second signal arrives, and output the equipartition pulse at the same time.
Further, the interval equalizing device in this embodiment may further include:
and the parameter updating unit is used for updating the division number D.
The parameter updating unit may be specifically configured to acquire parameter updating information through a preset parameter input interface, and update the number of equal shares by using the parameter updating information.
It should be noted that, in this embodiment, the update of the D value needs to be uniformly processed at the pulse of second.
In addition, the Q value and the M value can be updated before the first equipartition pulse in the current second or at the next second pulse according to requirements and actual conditions.
Through the technical scheme in the embodiment, the first remainder R of the equipartition calculation can be uniformly inserted into the equipartition process, so that the equipartition precision in each interval is ensured, and errors are not accumulated.
The above-described averaging results were subjected to error analysis as follows:
the interval averaging process clears the count at each pulse per second, and if the averaging pulses are numbered, the number is 0,1,2,3, …, D-1 from the initial pulse per second, and a total of D averaging pulses, then ideally the position of the nth averaging pulse in the second interval is:
according to the interval averaging method, the position of the nth averaging pulse in the second interval is as follows:
accordingly, the deviation is: development is Pos2-Pos 1;
replacing S in formula (3) by formula (1), replacing S in formula (4) by formula (2) to simplify development:
by further analysis it can be found that: when in use
When the concentration of the carbon dioxide is more than 0,
when it is equal to 0, the first,
it follows that the error corresponding to the above described interval-averaging scheme does not exceed one clock cycle in the negative direction and does not exceed one clock cycle in the positive directionExceed
In actual use, corresponding parameters can be designed according to actual conditions.
Further, the application also discloses an IP core obtained by encapsulating the interval equalization device disclosed in the foregoing embodiment. For the specific structure of the interval equalizing device, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The interval equalizing device based on the FPGA and the IP core provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. An interval equalizing device based on an FPGA is characterized by comprising:
the interval counting module is used for counting and outputting the interval values to be averaged;
the average calculating module is connected with the interval counting module and is used for determining an average value and a correction value;
the correction counting module is connected with the equipartition calculating module and takes the correction value as a module and is used for generating a correction pulse and counting and outputting the correction pulse so as to correct the deviation generated in the equipartition process;
the equipartition counting module is connected with the equipartition calculating module and the correction counting module and takes the equipartition value as a module and is used for generating equipartition pulses and counting and outputting the equipartition pulses;
the interval counting module, the correction counting module and the equipartition counting module are all constructed by counters based on an FPGA, and the equipartition calculating module is constructed by dividers based on the FPGA.
2. The FPGA-based interval equalizing device of claim 1,
the interval counting module is specifically used for determining the counting value of the interval counting module at the moment as the interval value to be averaged of the current second when the pulse signal of the second arrives, then outputting the interval value to be averaged, and performing zero clearing and recounting.
3. The FPGA-based interval equalizing device of claim 2,
the equipartition calculating module is specifically configured to divide the interval value to be equipartition output by the interval counting module by a preset number of equipartitions to obtain a first remainder and a first quotient value used as an equipartition value; and dividing the interval value to be averaged by the first remainder to obtain a second remainder and a second quotient value used as a correction value.
4. The FPGA-based interval equalizing device of claim 3,
the correction counting module is specifically used for clearing and recounting when the self counting value is greater than or equal to the correction value in the clock increasing process, and outputting the correction pulse.
5. The FPGA-based interval equalizing device of claim 4,
the equipartition counting module is used for stopping counting in a corresponding clock period when the correction pulse output by the correction counting module is acquired in the clock increasing process; and when the self count value is larger than or equal to the average value, resetting and recounting, and outputting an average pulse.
6. The FPGA-based interval equally dividing device of claim 5, wherein the equally dividing and counting module is further configured to clear and recount the second pulse signal when the second pulse signal arrives, and output equally dividing pulses at the same time.
7. The FPGA-based interval equally dividing device of any one of claims 3 to 6, further comprising:
and the parameter updating unit is used for updating the share number.
8. The FPGA-based interval equalizing device of claim 7,
the parameter updating unit is specifically configured to obtain parameter updating information through a preset parameter input interface, and update the number of equally divided parts by using the parameter updating information.
9. An IP core obtained by encapsulating the interval equalizing device according to any one of claims 1 to 8.
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