GB2403581A

GB2403581A - A substrate and a display device incorporating the same

Info

Publication number: GB2403581A
Application number: GB0315330A
Authority: GB
Inventors: Christopher James Brown
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2003-07-01
Filing date: 2003-07-01
Publication date: 2005-01-05
Also published as: KR20050004080A; GB0315330D0; KR100697130B1; TWI296791B; TW200506805A; JP2005024558A

Abstract

A substrate (1) comprises a switching element (8) having a first terminal for connection to a picture element electrode (11), a second terminal connected to a data line (Si), and a third terminal for receiving an enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal. The substrate (1) is further provided with test means (18) integrated on the substrate, for obtaining information about the operation of the switching element. The test means may make two measurements of the capacitance of the data line, with the switching element being in supposedly different states for each measurement. The invention may particularly be employed in an active matrix substrate. It enables faulty switching elements to be detected at an early stage in the fabrication of the substrate.

Description

Substrate and a Display Device incorporating the same This invention

relates to substrates, for example for active matrix display devices, such as Active Matrix Liquid Crystal Displays (AMLCDs), in which each picture element is provided with a switching element such as a polysilicon thin film transistors (TFTs).

More specifically, this invention relates to a substrate with test means provided on the substrate for determining whether switching elements are operating correctly. It also relates to a display device incorporating such a substrate.

Figure 1 illustrates a typical active matrix liquid crystal display device. The device is formed on a display substrate illustrated diagrammatically at 1 and comprises a timing and control circuit 2 connected to an input 3 for receiving timing and control signals together with image data to be displayed. The circuit 2 supplies the appropriate signals to a data signal generator in the form of a display source driver 4 and to a scan signal generator in the form of a gate driver 5.

The display source driver 4 has a plurality of outputs which are connected to a plurality of column electrodes S', S2...Sm which act as column data lines (or "source lines") for the active matrix of picture elements (pixels) indicated at 6. The column electrodes extend throughout the height of the active matrix 6 and each is connected to data inputs of a respective column of pixels. Similarly, the driver 5 has a plurality of outputs connected to row electrodes Gil, G2...Gn which extend throughout the width of the matrix 6. Each row electrode acts as a row scan line (or "gate line") and is connected to scan inputs of the pixels of the respective row.

One of the pixels is illustrated in more detail at 7 and is of a standard active matrix liquid crystal type. A pixel comprises an electronic switch 8 in the form of, for example, a poly-silicon thin film transistor whose source is connected to the ith column electrode Sj, and whose gate is connected to the JO row electrode Gj,. The pixel is therefore labelled as Pjj. The drain of the switch 8 is connected to a pixel electrode 11 forming part of a liquid crystal pixel image generating element 9 and is also connected to a parallel storage capacitor 1(). The image display element 9 is formed of a pixel electrotic 11, a counter-eJcctTodc 13 disposed opposite the pixel cicctrodc, and a liquid crystal layer 12 disposed between the pixel electrode 11 and the counter-electrode 13.

The references to rows and columns are not intended to be limited to horizontal rows and vertical columns but, instead, refer to the standard well-known way in which image data are entered row by row. Although pixel rows are normally arranged horizontally and pixel columns vertically in displays, this is not essential and the rows could, for example, equally well be arranged vertically with the columns then being arranged horizontally.

In use, image data for display are supplied by any suitable source to the input 3 of the arrangement and are displayed by the pixels active matrix 6 in accordance with the operation of the drivers 4 and 5. To write data to a particular pixel, an "enable" voltage is applied to the row scan line connected to the switching element of that pixel - so to write data to the pixel Pij the "enable" voltage would be applied to the row scan line G to turn the switching element 8 ON and thereby allow electrical conduction between the source and the drain of the switching element 8. (Applying the enable voltage to the row scan line Gj will also turn ON all other switching elements connected to the row scan line Gj.) As a result the pixel electrode and storage capacitor are electrically connected to the column electrode Sj and a voltage applied to the column electrode S' is written to the pixel electrode 11 of the liquid crystal pixel image generating element 9 and is also written to the storage capacitor 10. The enable voltage is then removed from the row scan line Gj thereby turning the switching element OFF. This electrically disconnects the pixel t'rom the column electrode Sj so that subsequent changes in the voltage of the column electrode Sj do not affect the voltage stored in the pixel Pjj.

In general, a display of the type shown in Figure I is rel'reshed row-byrow. Pixel image data are supplied serially as image frames with a frame synchronization pulse indicating the start of each Frame refresh cycle. lkows of pixel image data are entered one at'tcr the other in the display source driver 4 and a enable signal is supplied to the appropriate row scan line for enabling the image data to be stored in the appropriate row of pixels. Thus, the pixel rows of the matrix 6 are refreshed a row at a time with the gate drivers usually supplying enable signal.) a row at a time starting at the lop row and finishing al the bottom row when a frame ret'rcsh cycle has been completed.

As may be seen from the above, the correct operation of an active matrix display device depends on the switching elements functioning correctly so as to either isolate a pixel electrode from, or connect the pixel electrode to, the column electrode associated with that pixel electrode as desired. If a switching element should not function correctly it is not possible to address the associated pixel in the desired manner. The two most common failure modes of a switching element are for it (a) to go permanently open- circuit so that the pixel electrode is permanently isolated from the associated column electrode regardless of whether or not an enable voltage is applied to the associated row scan line or (b) to go permanently short-circuit so that the pixel electrode is permanently connected to the associated column electrode regardless of whether or not an enable voltage is applied to the associated row scan line. In case (a) it is impossible to write fresh data to the pixel, whereas in case (b) data stored on the pixel change every time that the voltage of the associated column data line changes.

Faults in switching elements may arise during the fabrication of the active matrix display device. It is desirable to detecting faulty switching elements at an early stage of fabrication of a display device, since this allows for corrective action to be taken or even for the display to be discarded if too many faults exist. Cost savings are made in the former case by repairing otherwise faulty displays and in the latter by eliminating further fabrication steps on faulty displays.

The conventional method of detecting faulty switching elements during fabrication of an active matrix display device is to use external testing equipment to write a fixed charge to each of the pixels. This charge is stored on the pixel storage capacitor and, after a set period of time, is read back. By comparing the amount of charge read back to that written, the integrity of each pixel switch in the active matrix may be ascertained.

The external equipment used to detect t:aults is expensive and time consuming to use and must be re-configured t'or each different design of display.

A first aspect of the present invention provides a substrate composing: a display picture; element electrodes a switching element, the switching clement having a first terminal connected to the picture element electrode, a second terminal connected to a data line, and a third terminal for receiving an enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; and test means for obtaining information about the operation of the switching element.

Expensive external testing equipment is not required, since the test means is integrated I on the substrate. The correct operation of the switching elements may be checked at an early stage in the fabrication of the substrate, for example immediately after the switching elements have been fabricated. It is not necessary to incorporate the substrate into a complete device before testing the switching elements.

The substrate may further comprise control means, the control means, in use, controlling the test means to obtain information about the operation of the switching I element.

The control means may, in use control the test means to obtain information about the capacitance of the data line.

The control means may, in use, control the test means to obtain information about the capacitance of the data line for two supposedly different states of the switching element.

The control means may, in a first time period, inhibit application of the enable signal to] the second terminal of the switching element whereby the test means obtains first information about the value of the capacitance of the data line while application of the enable signal is inhibited.

The control means may, in a second time period, allow application of the enable signal I to the second terminal of the switching element whereby the test means obtains second information about the value of the capacitance of the data line while the enable signal is applied to the second terminal of the switching element.

The test means may be adapted to determine the difference between the capacitance of the data line and the capacitance of a reference capacitor.

The test means may comprise a sense amplifier.

The test means may further comprise analysis means for obtaining information about I the operation of the switching element from the obtained information about the capacitance of the data line.

The analysis means may be adapted to compare the first information about the value of the capacitance of the data line with the second information about the value of the capacitance of the data line.

The analysis means may be adapted to compare the first and/or second information about the value of the capacitance of the data line with a predetermined threshold.

The substrate may comprise: a plurality of display picture element electrodes arrayed in rows and columns; a plurality of data lines, each data line being associated with a respective column of picture element electrodes; and a plurality of switching elements, each switching element having a first terminal connected to a respective one of the picture element electrodes, a second terminal connected to the data line associated with] the respective one of the picture element electrodes, and a third terminal for receiving an enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; and the control means may be adapted, in use, to control the test means to obtain information about the operation of each of the switching elements. I The invention also provides a combination comprising: a substrate as defined above; and an analysis means for rcceiving an output from the test means and f'o'- obtaining information about the or each switching clement from the output loom the test means.

The output from the test means is passed to an analysis means that is separate from the substrate, so that it is not necessary for an analysis means to be integrated on the substrate.

A second aspect of the invention provides a display device comprising a substrate as defined in the first aspect of the invention.

The display device may comprise: a substrate as defined in the first aspect of the invention; a counter substrate disposed opposite the substrate; and a liquid crystal material disposed between the substrate and the counter substrate.

A third aspect of the invention provides a method of testing a switching element of an substrate, the switching element having a first terminal connected to a picture element electrode, a second terminal connected to a data line, and a third terminal for receiving a enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; wherein the method of testing the switching element comprises obtaining information about the capacitance of the data line.

The principle of the testing method of the invention is that applying an enable signal to the switching element should, if the switching element is operating correctly, change the capacitance of the column electrode (data line). When all switching elements connected to a column electrode are open, a measurement of the capacitance of the column electrode will measure just the capacitance of the column electrode. However, when a switching element of a pixel associated with that column electrode is closed a measurement of the capacitance of' the column electrode will measure not only the capacitance of the column electrode but will also measure the pixel capacitance (that is, the capacitance of the storage capacitor and pixel electrode). Measuring the capacitance of the column electrode thus provides a quick and simple method of checking whether a switching element of, for example, an active matrix substrate is operating correctly.

The method may comprise obtaining information about the capacitance of the data line for two supposedly different states of the switching element.

The method may comprise obtaining first information about the value of the capacitance of the data line when no enable voltage is applied to the second terminal of the switching element.

The method may comprise obtaining second information about the value of the capacitance of the data line when an enable voltage is applied to the second terminal of the switching element.

The method may comprise comparing the first information about the value of the capacitance of the data line with the second information about the value of the capacitance of the data line.

The method may comprise comparing the first and/or second information about the value of the capacitance of the data line with a pre-set threshold.

The method may comprise the further step of, if the first information about the value of the capacitance of the data line is substantially similar to the second information about the value of the capacitance of the data line, comparing the first and second information about the value of the capacitance of the data line with a pre-determined threshold.

The method may comprise determining, as the information about the value of the capacitance of the data line, the difference between the capacitance of the data line and the capacitance of a reference capacitor.

The method may comprise generating a voltage having a magnitude proportional to the difference between the capacitance ol the data line and the capacitance of the reference capacitor.

A fourth aspect of the present invention provides a method of testing an active matrix substrate, the active matrix substrate comprising: a plurality oi display picture element electrodes arrayed in rows and columns; a plurality ol data lines, each data line being associated with a respective column of picture element electrodes; and a plurality of switching elements, each switching element having a first terminal connected to a respective one of the picture element electrodes, a second terminal connected to the data line associated with the respective one of the picture element electrodes, and a third terminal for receiving a enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; wherein the method comprises the steps of: obtaining first information about the respective capacitance of each data line when no enable signal is applied to any of the switching elements; applying an enable signal to each switching element in a selected first row while not applying an enable signal to switching elements in other rows; obtaining second information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected first row; and obtaining information about the switching elements in the selected first row from the first and second information about the respective capacitance of each data line.

The method may further comprise: applying an enable signal to each switching element in a selected second row while not applying an enable signal to switching elements in other rows; obtaining third information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected second row; and obtaining information about the switching elements in the selected second row from the first and third information about the respective eapaeitanee of each data line.

Alternatively, the method may further comprise: obtaining third information about the respective capacitance of each data line when no enable signal is applied to any of the switching elements; applying an enable signal to each switching element in a selected second row while not applying an enable signal to switching elements in other rows; obtaining fourth information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected second row; and obtaining information about the switching elements in the selected second row from the third and fourth information about the respeclive capacitance of each data line.

The invention will be further described, by way of illustrative example, with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of an active matrix display; Figure 2 is a block schematic diagram of an active matrix substrate according to an embodiment of the invention; Figure 3(a) is a diagram of the active matrix substrate of Figure 2; Figure 3(b) is a schematic diagram of a liquid crystal display device incorporating the active matrix substrate of Figure 3(a); Figure 4 is a block flow diagram illustrating a first method of the invention; and Figure 5 is a block flow diagram illustrating a second method of the invention.

Like reference numerals represent like components throughout the drawings.

The invention will be described with particular reference to an active matrix substrate comprising a matrix of picture element electrodes.

Figure 2 is a block schematic diagram of an active matrix substrate 14 of the present invention. The active matrix substrate 14 comprises a source driver 4, a gate driver 5, and an active matrix 6 of picture element electrodes formed on a substrate 1. When the substrate is incorporated into a complete display device, each picture element electrode will correspond to a pixel (picture element) of the device.

The active matrix substrate 14 of Figure 2 further comprises test means 18 for testing whether the switching elements of the active matrix (I operate correctly. The test means 18 arc provided on the substrate l and may for example comprise circuits integrated on the substrate 1.

Figure 3(a) shows the components of the active matrix substrate 14 of Figure 2 in more detail. The components of the active matrix substrate 14 are formed on a substrate indicated as 1, and comprise a timing and control circuit 2 connected to an input 3 for receiving timing and control signals (and also for receiving image data to be displayed once the active matrix substrate 14 has been incorporated into a finished display device). The timing and control circuit 2 supplies the appropriate signals to a data signal generator in the form of a display source driver 4 and a scan signal generator in the form of a gate driver 5. The source driver 4 and the scan driver 5 may be of any suitable type, such as of a standard or conventional type, and will not be described further. The display source driver 4 has a plurality of outputs which are connectable to a plurality of column electrodes Sit, S2...Sm which act as column data lines for the matrix of picture elements (pixels) indicated at 6. The timing and control circuit 2 controls whether the outputs of the display source driver 4 are electrically connected to or isolated from the data lines. The display source driver outputs may, for example, I only be connected to the data lines when the display source driver 4 is enabled by the control circuit 2. The data lines extend throughout the height of the active matrix 6, and each data line is connected to data inputs of a respective column of pixels. Similarly, the gate driver 5 has a plurality of outputs connected to row electrodes Gil, G2...Gn which extend throughout the width of the matrix 6. Each row electrode acts as a row scan line and is connected to scan inputs of the pixels of the respective row.

One of the pixels is illustrated in more detail at 7. It will be seen that the pixel 7 of Figure 3 corresponds generally to the pixel 7 of Figure 1, and the description will not be repeated here. It should, however, be noted that since Figure 3(a) shows an active matrix substrate 14 rather than a complete display device, the liquid crystal layer 12 and counter electrode 13 of Figure 1 are not present and so are not shown in Figure 3(a).

In the embodiment of Figure 3(a), the test means 18 are disposed along the bottom edge ol the matrix 6 ol pixels. The test means l8 comprises a plurality oi sense amplifiers 15 whose inputs are connected to respective ones ol the column electrodes. The sense amplifiers are controlled, for example enabled, by a control signal from the timing and control circuit 2. The outputs of the sense amplifiers are supplied to an analogue-to digital conversion block 16, which converts the analogue values sensed by the sense amplifiers 15 to parallel digital outputs. The outputs of the conversion block 16 are connected to read-out shift registers 17, which convert the parallel output data from the conversion block 16 to serial output data and supply this to output line 19.

The test means 18 is able to obtain information about the capacitance of the data lines S', S2. Sn. information as to whether the switching elements 8 are operating correctly may be derived from the measured capacitance of the data lines. In a particularly preferred embodiment, information about the operation of the switching elements may be obtained by making two measurements of the capacitance of the data line, with a switching element connected to that data line being in two supposedly different states The principle of the test method will now be described with reference to the pixel P associated with data line Sj and row electrode Gj.

Initially, the timing and control circuit enables the sense amplifer IS in a first time period so that the sense amplifer 15 may make a measurement of the capacitance of the data line Sj. During this first time period, the timing and control circuit ensures that the F data line Sj is electrically isolated from the display source driver 4. The timing of control circuit 2 also inhibits the gate driver 5 from applying an enable voltage to the row scan line Gj. Indeed, the timing and control circuit 2 inhibits the gate driver 5 from applying an enable voltage to any of the row scan lines Gj. The measurement of capacitance during the first time period is therefore made with every switching element 8 connected to the i'i' column data line supposedly open circuit - that is, the switching; element will be open circuit if it is operating correctly - so that the data line Sj is supposedly isolated from the storage capacitance 10 and the pixel electrode 11 of every pixel of the Ah pixel column. The data line Sj is also isolated from the display source driver 4. As a result, the capacitance measured in the first time period should, if the switching elements connected to the data line are operating correctly, be the intrinsic capacitance of the data line Sj.

In a second time period, the timing and control circuits instructs the gate driver 5 to apply an enable voltage to the row scan line Gj, while not applying the enable voltage to any other row scan line. The timing and control circuit continues to maintain the display source driver 4 isolated from the source line S, and also continues to enable the sense amplifier 15 to measure the capacitance of the source line S. Since the switching element of pixel Pjj is now supposedly closed - that is, the switching element of pixel Pjj will be closed if it is operating correctly - so that the source line Sj is supposedly connected to the pixel Pjj, the capacitance measured in the second time period should be the sum of the capacitance of the pixel Pjj and the intrinsic capacitance of the source line Sj. The predominant contribution to the pixel capacitance will be the storage capacitance. Thus, if the switching element is tested at a point in the fabrication processes after, for example, the storage capacitance 10 has been fabricated, the capacitance measured in the second time period should be the sum of the storage capacitance 10 and the intrinsic capacitance of the source line Sj.

Information about the operation of the switching element in the pixel may be obtained by comparing the capacitance obtained in the first time period and the capacitance measured in the second time period. Since the capacitance measured in the second time period should include the storage capacitance as well as the intrinsic capacitance of the data line Sj, the capacitance measured in the second time period should be greater than the capacitance measured in the first time period. Thus, if the comparison shows that the capacitance measured in the second time period is indeed greater than the capacitance measured in the first time period, this suggests that the switching element is operating correctly. Il however the comparison shows that the capacitance measured in the first time period is approximately equal to the capacitance measured in the second time period, this indicates that the switching element is faulty. It suggests that either the switching element is permanently open circuit (so that both measurements are measurements just of the intrinsic capacitance of the data line Sj), or that the switching element is permanently closed (so that the measurement in the first time period is a measurement of the overall capacitance of the storage capacitor 1() in addition to the capacitance of the data line Sj). These two fault situations may be distinguished from one another by comparing the capacitances measured in the first and second time periods with a pre-set threshold. The threshold is set at a level that is greater than the expected capacitance of the data line Sj but that is below the capacitance of the storage capacitor 10. Thus, if the capacitance measured in the first time period is substantially equal to the capacitance measured in the second time period, and is below the pre-set threshold, this indicates that neither measurement of capacitance included the storage capacitor so that the switching element is permanently open. Conversely, if the capacitance measured in the first time period is substantially equal to the capacitance measured in the second time period, and both are greater than the threshold, this indicates that both measurements of capacitance included the storage capacitor- so that the switching element is permanently closed.

Measurement of capacitance in this way thus provides a straightforward technique for determining whether a switching element is operating correctly. Furthermore, it not only provides information as to whether a switching element is operating correctly but also provides information as to the nature of the fault if it is found that a switching element is faulty.

The test technique of the present invention may be performed on the active matrix substrate during manufacture of the substrate. The method does not require the liquid crystal layer to be present, and so the substrate can be tested before it is incorporated into a complete display device. The test method of the invention may be carTied out at any stage in manuf;acture of the active matrix substrate after the switching elements and the storage capacitors have been fabricated on the substrate. Thus, faults may be detected at a relatively early stage in the fabrication process - and this allows faults to be coTccted or, alternatively, allows a substrate to be discarded it too many t;aulty switching elements exists.

The testing method of the present invention does not require significantequipment external to the active matrix substrate. The only external eluipmcnt required is means (denoted as 44 in Figure 3(a)) for receiving the output fi-oTn the shift register 17 and converting the output from the shift register to provide a useful output such as a "pass/fail" indication or the location of any faulty switching elements. (In principle the means for generating a "pass/fail" indication or the location of any faulty switching elements from the output of the shift register 17 could be integrated on the substrate, although this is currently less efficient than using external means owing to the area of the substrate that would be taken up.) In principle, the analogue-to- digital conversion block 16 and the shift register 17 could be incorporated in external testing equipment rather than be integrated onto the active matrix substrate 14. This would reduce the space taken up by the testing equipment on the active matrix substrate, although it does have a disadvantage that it would require as many extra connections between the external testing equipment and the panel as there arc columns in the pixel matrix.

The above description refers to a sense amplifier measuring the capacitance of the source line in the first and second time periods. While this may be done in principle, in a preferred embodiment the sense amplifer measures the difference between the capacitance of the source line and the capacitance of a reference capacitor integrated on the active matrix substrate. In this embodiment the sense amplifier outputs a voltage signal that is proportional to the difference between the capacitance of the reference capacitor and the capacitance of the source line. The analogue-to-digital conversion block generates a binary word that is proportional to this voltage signal. The reference capacitor is fabricated to have a capacitance that is equal to the intrinsic capacitance of the source line. Thus, in the first period the output binary word from the analogue-to- digital conversion block is (assuming that no switching element connected to the source line is permanently closed) zero.

The above description has referred lo testing the switching element of a single pixel of the active matrix substrate. In practice, of course, it will be desirable to test all switching elements on an active matrix substrate and Figure 4 illustrates one method of doing this.

Initially, at step 20, the capacitance of each source line is measured. For each source line, its capacitance is measured with all switching elements connected to that source line in the nominally OFF state. Step 20 may, for example, comprise the timing and control circuit 2 isolating every source line from the display source driver 4, inhibiting the gate driver from applying the enable voltage to any row scan line, and enabling the sense amplifiers 15 to measure the capacitance of their respective source line.

In step 20, each sense amplifier will generate a voltage signal that is proportional to the difference between the capacitance of the associated data line and the reference capacitor. In a preferred embodiment of the substrate of the invention a plurality of reference capacitors are integrated on the substrate, one for each sense amplifier. In this case, each sense amplifier generates at step 20 a voltage signal that is proportional to the difference between the capacitance of the associated data line and the respective reference capacitor. In principle, however, the substrate could be provided with a single reference capacitor. The first voltage signal produced by each sense amplifer is stored at step 21 in a calibration data file indicated at 22. In principle, the method could comprise measuring the capacitance of each data line in sequence, with the measurement obtained from one data line being stored before the capacitance of the next data line is measured. In practice, however, it may be desirable to measure the capacitance of each data line simultaneously at step 20 and simultaneously store each measurement at step 21, as this may reduce the time taken. The value for the capacitance of a data line obtained in step 20 should, if all switching elements connected to the data line are operating correctly, be equal to the intrinsic capacitance of the data line and may be considered as a calibration value for the data line.

At step 23 a first row scan line is made active. This is done by the timing and control circuit 2 instructing the gate driver to apply the "enable" voltage to the first row scan line, for example to the row scan line G'. The "enable" voltage is therefore applied to the gate electrode of every switching element connected to the first row scan line, so that each switching element in the first row is turned ON (assuming that it is operating con-ectly). The other row scan lines remain inactive at step 23, and the timing and control circuit inhibits the gate driver S from applying the "enable" voltage to the other row scan lines.

At step 24, the capacitance of each source line is again measured by the sense amplifiers IS. Step 24 provides the second capacitance measurement for each source line. Step 24 may comprise measuring the capacitance of each source line in sequence, or it may comprise simultaneously measuring the capacitance of each source line.

At step 25, the values of the first capacitance for each data line are retrieved from the calibration data file 22. For each source line, the capacitance measured at step 21 and retrieved from the calibration data file is subtracted from the capacitance measured at step 24. The result of each subtraction is stored at step 26 in a pixel state map file 27.

Each subtraction is stored against the respective row scan line (in this example G') and against the respective data line.

As explained above, if a switching element is functioning correctly the result of the subtraction at step 25 should be a positive value, since the capacitance measured at step 24 should include the storage capacitance whereas the capacitance measured at step 20 should not. The result obtained at step 26 thus provides an immediate indication as to whether a switching element (in the first row) is operating correctly (a positive value is obtained) or whether a switching element is not operating correctly (a value close to zero will be obtained).

At step 28 it is determined whether the test procedure has been carried out for all row scan lines. If step 28 yields a "no" determination, the currently active row scan line is made inactive and the next row scan line is made active at step 29. For example, if the gate line Gil is the currently active row scan line, step 29 would comprise the timing and control circuit 2 instructing the gate driver 5 to remove the "enable" voltage from the row scan line G' and to apply the "enable" voltage to the row scan line G2. Step 24, 25 and 26 are then repeated for the next row scan line. If a "no" determination is still obtained at step 28, steps 29, 24, 25 and 26 are repeated until a "yes" determination is obtained at step 28.

The pixel state file map 27 produced by the method of Figure 4 contains, for each pixel of the active matrix substrate 14, an indication as to whether the switching element is operating correctly or is faulty. If is desired to obtain more information about a faulty pixel, this may be done by, for example, retrieving the capacitance measured at step 20 for the associated source line and comparing it with a threshold as explained above. (It should be noted that comparing the capacitance with a threshold is effective only if a substrate has a small number of faulty switching elements. For example, comparison with a threshold may not be effective if a source line has more than one permanently closed switching element or has at least one permanently closed switching element and at least one permanently open switching element. However, where a substrate has a large number of faulty switching elements it is generally not cost- effective to repair the switching elements and in this case the substrate would simply be discarded.) In the method of Figure 4, the capacitance of each data line measured at step 20 is used each time that step 25 is performed in the testing procedure. Testing a practical active matrix substrate will typically take approximately lOms, and is possible that the accuracy of the test process could be affected by, for example, variations in temperature or fluctuations in the supply voltages during the test process. Figure 5 of the present invention therefore shows a second method of testing an active matrix substrate, in which this disadvantage is overcome.

In Figure 5, a counter is initialised to N = 1 at step 30. As will be described below, this counter represents the index of the row scan line.

At step 31, the capacitance of each source line is measured with every row scan line inactive. The results are stored at step 32 in a calibration data file 33. Steps 31 and 32 of Figure 5 correspond to steps 20 and 21 of Figure 4, and will not be further described.

At step 34, the N'h row scan line is made active. Since N is currently 1, step 34 comprises the timing and control circuit 2 instructing the gate driver 5 to apply the "enable" voltage to the row scan line G' while not applying the "enable" voltage to the other row scan lines.

At step 35 the capacitance of each column data line is again measured. At step 36, for each data line, the value of the capacitance measured at step 31 is retrieved and is subtracted from the value obtained at step 35, and at step 37 the results are stored in a pixel state map file 38. Steps 35, 36 and 37 of Figure 5 correspond to steps 24, 25 and 26 of Figure 4 and will not be described further.

At step 39 it is determined whether the test process has been carried out for every row scan line. If a '$no" determination is obtained, the currently active row scan line is made inactive at step 40. In the present example, step 40 would comprise the timing and control circuit instructing the gate driver 5 to cease application of the "enable" voltage to the row scan line G'.

At step 41, the counter N is incremented by l. In the present case, the new value of the counter will be N = 2.

Steps 31-37 are then repeated for the row scan line G2. The step of incrementing the counter N and repeating steps 31-37 for each value of N are then repeated until a "yes" determination is obtained at step 39.

In the embodiment of Figure 5, step 31 is repeated for each row scan line. The "calibration data" used in step 36 are therefore data that were obtained immediately before step 35 was carried out. This minimises errors arising from variations in quantities such as temperature or the supply voltage.

An active matrix substrate ol the invention may be incorporated into a liquid crystal display device if it is determined that the number of faulty switching elements is sufficiently small, or if switching elements that are found to be l;aulty are repaired or replaced. Fig 3(b) is a schematic cross-section through a liquid crystal display device incorporating an active matrix substrate 14 of Figure 3(a), and it will be seen that the structure of the liquid crystal display device is, apart from the use of an active matrix substrate of the invention, entirely conventional. A counter substrate 42 is disposed opposite to the active matrix substrate 14. As is well-known, one or more counter electrodesl3 are provided on the counter substrate (only one counter electrode 13 is shown in Figure 3(b)). A liquid crystal layer 12 is disposed between the counter substrate and the active matrix substrate and is sealed in by sealing means 43. The counter substrate, sealing means and the liquid crystal layer may be of any suitable type, such as a standard or conventional type, and will not be described here. The substrates are arranged such that the pixel electrodes 11 of the active matrix substrate and the counter electrode of the counter substrate are adjacent the liquid crystal layer. (In practice, layers (not shown in Figure 3(b)), such alignment layers for aligning the liquid crystal layer, will be provided over the pixel electrodes l l of the active matrix substrate and the counter electrode of the counter substrate.) The invention has been described above with reference to an active matrix substrate comprising picture element electrodes arranged in a matrix of rows and columns. The invention is not, however, limited to this.

Claims

CLAIMS: 1. A substrate comprising: a switching element, the switching

element having a first terminal for connection to a picture element electrode, a second terminal connected to a data line, and a third terminal for receiving an enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; and test means for obtaining information about the operation of the switching element.
2. A substrate as claimed in claim 1 and further comprising control means, the control means, in use, controlling the test means to obtain information about the operation of the switching element.
3. A substrate as claimed in claim 2 wherein the control means, in use, controls the test means to obtain information about the capacitance of the data line.
4. A substrate as claimed in claim 3 wherein the control means, in use, controls the test means to obtain information about the capacitance of the data line for two supposedly different states of the switching element.
5. A substrate as claimed in claim 4 wherein, in a first time period, the control means inhibits application of the enable signal to the second terminal of the switching element whereby the test means obtains first information about the value of the capacitance of the data line while application of the enable signal is inhibited.
6. A substrate as claimed in claim 5 wherein, in a second time period, the control means allows application of the enable signal to the second terminal of the switching element whereby the test means obtains second information about the value of the capacitance of the data line while the enable signal is applied to the second terminal of the switching element.
7. A substrate as claimed in any of claims 3 to 6 wherein the test means is adapted lo determine the difference between the capacitance of the dale line and the capacitance ol a reference capacitor.
8. A substrate as claimed in any of claims 1 to 7, wherein the test means comprises a sense amplifier.
9. A substrate as claimed in any of claims 3 to 8 wherein the test means further comprises analysis means for obtaining information about the operation of the switching element from the obtained information about the capacitance of the data line.
1(). A substrate as claimed in claim 9 when dependent from claim 6 wherein the analysis means is adapted to compare the first information about the value of the capacitance of the data line with the second information about the value of the capacitance of the data line.
11. A substrate as claimed in claim 9 when dependent from claim 5 or 6 wherein the analysis means is adapted to compare the first and/or second information about the value of the capacitance of the data line with a predetermined threshold.
12. A substrate as claimed in any preceding claim and comprising: a plurality of display picture element electrodes arrayed in rows and columns; a plurality of data lines, each data line being associated with a respective column of picture element electrodes; and a plurality of switching elements, each switching element having a first terminal connected to a respective one of the picture element electrodes, a second terminal connected to the data line associated with the respective one of the picture element electrodes, and a third terminal for receiving an enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; and wherein the control means is adapted, in use, to control the test means to obtain hlormation about the operation ot each of the switching elements.

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13. A combination comprising: a substrate as claimed in any of claims I to 8; and an analysi.s means t'or receiving an output l'rom the test means and for obtahing inl'ormation about the or each switching element from the output from the test means.
14. A display device comprising a substrate as det'ined in any of claims 1 to 12.
15. A display device comprising: a substrate as defined in any of claims 1 to 12; a counter substrate disposed opposite the substrate; and a liquid crystal material disposed between the substrate and the counter substrate.
16. A method of testing a switching element of a substrate, the switching element having a t'irst terminal for connection to a picture element electrode, a second terminal connected to a data line, and a third terminal for receiving a enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; wherein the method of testing the switching element comprises obtaining int'ormation about the capacitance of the data line.
17. A method as claimed in claim 16 and comprising obtaining information about the capacitance of the data line for two supposedly different states of the switching element.
18. A method as claimed in claim 17 and comprising obtaining first information about the value of the capacitance of the data line when no enable voltage is applied to the second terminal of the switching element.
19. A method as claimed in claim 16 or 17 and comprising obtaining second information about the value of the capacitance of the data line when an enable voltage is applied to the second terminal of the switching element.
20. A method as claimed in claim 19 when dependent from claim 18 and further comprising comparing the t'irst information about the value of the capacitance of the data line with the second information about the value of the capacitance of the data line. 23
21. A method as claimed in claim 18 or 19 and comprising comparing the first and/or second information about the value oi the capacitance oi the data line with a pre- set threshold.
22. A method as claimed in claim 20 and comprising the further step of, if the first information about the value of the capacitance of the data line is substantially similar to the second information about the value of the capacitance of the data line, comparing the first and second information about the value of the capacitance of the data line with a pre-determined threshold.
23. A method as claimed in any of claims 16 to 22 and comprising determining, as the information about the value of the capacitance of the data line, the difference between the capacitance of the data line and the capacitance of a reference Capacitor.
24. A method as claimed in claim 23 and comprising generating a voltage having a magnitude proportional to the difference between the capacitance of the data line and the capacitance of the reference capacitor.
25. A method of testing an active matrix substrate, the active matrix substrate comprising: a plurality of display picture element electrodes arrayed in rows and columns; a plurality of data lines, each data line being associated with a respective column of picture element electrodes; and a plurality of switching elements, each switching element having a first terminal connected to a respective one of the picture element electrodes, a second terminal connected to the data line associated with the respective one of the picture element electrodes, and a third terminal tor receiving a enable signal for selectively enabling the switching element and thereby connecting the first terminal to the second terminal; wherein the method comprises the steps of: obtaining first information about the respective capacitance of each data line when no I enable signal is applied to any of the switching elements; applying an enable signal to each switching element in a selected first row while not applying an enable signal to switching elements in other rows; obtaining second information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected first row; and obtaining information about the switching elements in the selectecl first row from the first and second formation shout the respective capacitance of each data line.
26. A method as claimed in claim 25 and further comprising: applying an enable signal to each switching element in a selected second row while not applying an enable signal to switching elements in other rows; obtaining third information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected second row; and obtaining information about the switching elements in the selected second row from the first and third information about the respective capacitance of each data line.
27. A method as claimed in claim 25 and further comprising: obtaining third information about the respective capacitance of each data line when no enable signal is applied to any of the switching elements; applying an enable signal to each switching element in a selected second row while not applying an enable signal to switching elements in other rows; obtaining fourth information about the respective capacitance of each data line when the enable signal is applied to the switching elements in the selected second row; and obtaining information about the switching elements in the selected second row from the third and fourth information about the respective capacitance of each data line.