GB2371408B - Structure with tapered landing and method of fabrication - Google Patents

Structure with tapered landing and method of fabrication

Info

Publication number
GB2371408B
GB2371408B GB0121205A GB0121205A GB2371408B GB 2371408 B GB2371408 B GB 2371408B GB 0121205 A GB0121205 A GB 0121205A GB 0121205 A GB0121205 A GB 0121205A GB 2371408 B GB2371408 B GB 2371408B
Authority
GB
United Kingdom
Prior art keywords
fabrication
tapered landing
landing
tapered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0121205A
Other languages
English (en)
Other versions
GB2371408A (en
GB0121205D0 (en
Inventor
Stephen Ward Downey
Edward Belden Harris
Sailesh Mansinh Merchant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0121205D0 publication Critical patent/GB0121205D0/en
Publication of GB2371408A publication Critical patent/GB2371408A/en
Application granted granted Critical
Publication of GB2371408B publication Critical patent/GB2371408B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
GB0121205A 2000-08-31 2001-08-31 Structure with tapered landing and method of fabrication Expired - Fee Related GB2371408B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65349200A 2000-08-31 2000-08-31

Publications (3)

Publication Number Publication Date
GB0121205D0 GB0121205D0 (en) 2001-10-24
GB2371408A GB2371408A (en) 2002-07-24
GB2371408B true GB2371408B (en) 2004-12-22

Family

ID=24621097

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0121205A Expired - Fee Related GB2371408B (en) 2000-08-31 2001-08-31 Structure with tapered landing and method of fabrication

Country Status (4)

Country Link
JP (1) JP2002124576A (enrdf_load_stackoverflow)
KR (1) KR20020018606A (enrdf_load_stackoverflow)
GB (1) GB2371408B (enrdf_load_stackoverflow)
TW (1) TW582090B (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4949656B2 (ja) * 2005-08-12 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11869725B2 (en) 2021-11-30 2024-01-09 Texas Instruments Incorporated Multi-stacked capacitor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838605A (en) * 1996-03-20 1998-11-17 Ramtron International Corporation Iridium oxide local interconnect
US6114766A (en) * 1997-12-18 2000-09-05 Advanced Micro Devices, Inc. Integrated circuit with metal features presenting a larger landing area for vias

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838605A (en) * 1996-03-20 1998-11-17 Ramtron International Corporation Iridium oxide local interconnect
US6114766A (en) * 1997-12-18 2000-09-05 Advanced Micro Devices, Inc. Integrated circuit with metal features presenting a larger landing area for vias

Also Published As

Publication number Publication date
KR20020018606A (ko) 2002-03-08
TW582090B (en) 2004-04-01
GB2371408A (en) 2002-07-24
JP2002124576A (ja) 2002-04-26
GB0121205D0 (en) 2001-10-24

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20150831