GB2345189A - Process for forming dual damascene wiring - Google Patents

Process for forming dual damascene wiring Download PDF

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Publication number
GB2345189A
GB2345189A GB9930205A GB9930205A GB2345189A GB 2345189 A GB2345189 A GB 2345189A GB 9930205 A GB9930205 A GB 9930205A GB 9930205 A GB9930205 A GB 9930205A GB 2345189 A GB2345189 A GB 2345189A
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Prior art keywords
film
inter
layer insulation
hole
insulation film
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GB9930205A
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GB9930205D0 (en
Inventor
Masayoshi Ikeda
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

An inter-layer insulation film 22 is formed on a lower conductive layer 21, and a resist film having an opening for a via-hole pattern is formed in the inter-layer insulation film. Using the resist film as a mask, the inter-layer insulation film is etched to form a via-hole, and the via-hole is filled with a sacrificial material 24 having a higher etching rate than the inter-layer insulation film to form a buried film. Thereafter, a resist film 25 having an opening 33 for a wiring groove pattern is formed on the buried film, and the buried film and the inter-layer insulation film are etched using the resist film as a mask to form a wiring groove on the inter-layer insulation film. The process ensures than any unacceptable substance caused by an etching residue of an inter-layer insulation film does not remain in an etching step; thus wiring can be produced which is not inferior.

Description

PROCESS FOR FORMING DUAL DAMASCENE WIRING BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a process for forming a dual damascene wiring used in multilayer interconnection techniques.
Description of the Related Art Effective methods for forming a multilayer interconnection of semiconductor integrated circuit include damascene techniques. Among these techniques, dual damascene techniques have the advantage that they simplify a process and expedite a process to decrease a TAT (Turn-and Around-Time) leading to a remarkable reduction in production cost. In the dual damascene technique, a wiring groove in which an upper wiring is formed and a via-hole or a contact hole (both holes are hereinafter collectively called"via-hole") which connects the upper layer wiring to a lower layer wiring or to a substrate are formed in an insulated layer and thereafter a metal film is filled in the wiring groove and the via-hole simultaneously to form a wiring and a via at the same time.
FIG. 1A to FIG. 1C are sectional views showing a method for forming a wiring by using a conventional dual damascene techniques in step order. Firstly, as shown FIG. 1A, a silicon oxide (Sio2) film 2 is formed as an inter-layer insulation film on a silicon substrate 1. On the silicon oxide film 2, a silicon nitride (SiN) film 3 is formed and on the silicon nitride film 3, a resist film 4 is further formed. Using photolithography, the resist film 4 is patterned to a form of a via-hole.
Thereafter, the silicon nitride film 3 is plasma-etched using the resist film 4 as a mask to form a via-hole pattern 5 on the silicon nitride film 3.
Thereafter, as shown in FIG. 1B, a silicon oxide film 6 is formed on the entire surface. Then, the surface of the silicon oxide film 6 is subjected to CMP (Chemical Mechanical Polishing) to flatten the surface.
Next, as shown in FIG. 1C, a resist film 7 is formed on the silicon oxide film 6 and patterned in a form 9 of a wiring groove. After that, etching is carried out using the resist film 7 and the silicon nitride film 3 as a mask to open a via-hole in the silicon oxide film 2 and to form a wiring groove on the silicon oxide film 6. in this case, etching is carried out using an etching method in which the selective etching ratio in terms of the ratio of the etching rate of a silicon oxide film to that of a silicon nitride film (etching rate of a silicon oxide film/etching rate of a silicon nitride film) is high, whereby the silicon nitride film 3 is left as a mask until the via-hole is opened.
After that, the resist film 7 is removed and a conductive material is filled in a via-hole and the wiring groove to form a via and a wiring.
In this conventional method for forming a dual damascene wiring, as shown in FIG. 1C, when a misregistration occurs between the via-hole pattern 5 and the wiring groove pattern 9, the contact area between the wiring and the via becomes small, giving rise to the drawback that the contact resistance is increased. Also, the aspect ratio of the via-hole is high, specifically, the ratio of the depth to width of the via-hole is large; it is necessary to remarkably increase the selective etching ratio in terms of the ratio of the etching rate of the silicon oxide film 2 to that of the silicon nitride film 3 used as a stopper. However, it is difficult from the operational point of view to adopt such an etching condition. Moreover, as shown in FIG. 1C, the upper side edge portion of the via-hole is greatly removed after being etched.
As another conventional method for forming a dual damascene wiringwhich method can remedy the drawback of the above conventional art technology shown in FIG. 1A to FIG. 1C, that shown in FIG. 2A to FIG. 2D has been proposed (Japanese Patent Application Laid-Open (JP-A) Nos. H8-335634 and H10-223755). FIG. 2A to FIG. 2D are sectional views showing a method for forming another conventional dual damascene wiring in step order. As shown in FIG. 2A, a silicon oxide film 12 is formed on a silicon substrate 11 and the silicon oxide film 12 is etched using photolithography to form a via-hole 13.
Then, as shown in FIG. 2B, an organic compound is applied to the entire surface to fill the via-hole 13 with an organic compound film 14 and a resist film 15 is formed on the silicon oxide film 12 and the organic compound film 14. A pattern 16 of a wiring groove is formed in the resist film 15 by patterning it using photolithography. The etching rate of this organic compound is lower than one-half that of the silicon oxide film used as an inter-layer insulation film.
Next, as shown FIG. 2C, using the wiring pattern of the resist film 15 as a mask, the organic compound film 14 and the silicon oxide film 12 are plasma-etched to form a wiring groove 16. In this case, the etching rate of the silicon oxide film 12 is higher than that of the organic compound film 14 filled in the via-hole 13 and hence the organic compound film 14 remains in the viahole 13 unremoved while the wiring groove 16 is etched.
Thereafter the resist film 15 and the organic compound film 14 are removed to thereby form the via-hole 13 together with the wiring groove 16. Then, these wiring groove 16 and the via-hole 13 are filled to form a wiring and a via.
In this conventional method constituted in the above manner, even when a misregistration occurs between the via-hole and the wiring groove as shown in FIG. 2C, the contact area between the via filled in the via-hole 13 and the wiring filled in the wiring groove 16 is not decreased. The contact resistance between the both is sufficiently low accordingly. Also, in the conventional art technology shown in FIG. 1A to FIG. 1C, when the aspect ratio of the via-hole is increased, it is necessary to remarkably increase the ratio of the etching rate of the silicon oxide film to that of the silicon nitride film 3. However, in the conventional art technology shown in FIG. 2A to FIG. 2D, it is unnecessary to adopt such an etching condition.
However, in the conventional method for forming a dual damascene, there are the following problems.
Specifically, as shown in FIG. 2A, when the via-hole 13 is formed by etching, the via-hole 13 has a large crosssectional area on the side of the upper opening portion thereof and a narrow cross-sectional area on the bottom side on account of the marked characteristic of the etching. Accordingly, the side of the via-hole 13 is slightly inclined with the upper portion being warped backwards.
The side of the via-hole 13 is inclined like this.
Therefore, when it is intended to form the wiring groove 16 by etching in the step of FIG. 2C, a portion projecting from the side edge of the upper portion of the organic compound film 14 serves as an etching mask for the silicon oxide film 12, allowing an etching residue of the silicon oxide film 12 to remain unremoved just under the projecting portion because the selective etching ratio for the organic compound film 14 is smaller than that for the silicon oxide film 12. For this, as shown in FIG. 2D, a projection material 17 of a silicon oxide film remains on the upper end portion of the via-hole 13 after the organic compound film 14 has been removed. The projection material 17 is intermingled in wirings, causing, for instance, inferior conduction of the wirings.
SUMMARY OF THE INVENTION It is an object of the preferred embodiments of the present invention to provide a process for forming a dual damascene wiring ensuring that any unacceptable substance caused by an etching residue of an inter-layer insulation film does not remain in an etching step to produce inferior wiring.
A process for forming a dual damascene wiring according to a first aspect of the present invention comprises the steps of forming an inter-layer insulation film on a lower conductive layer; forming, on the interlayer insulation film, a first resist film provided with an opening for a hole pattern ; etching the inter-layer insulation film by using the first resist film as a mask to form a hole ; filling the hole with a material having a higher etching rate than the inter-layer insulation film to form a buried film; forming, on the buried film, a second resist film having an opening for a wiring groove pattern; and etching the buried film and the inter-layer insulation film by using the second resist film as a mask to form a wiring groove in the inter-layer insulation film.
A process for forming a dual damascene wiring according to a second aspect of the present invention comprises the steps of forming an inter-layer insulation film on a lower conductive layer; forming, on the interlayer insulation film, a first resist film provided with an opening for a wiring groove pattern; etching the inter-layer insulation film by using the first resist film as a mask to form a wiring groove; filling the wiring groove with a material having a higher etching rate than the inter-layer insulation film to form a buried film; forming, on the buried film, a second resist film having an opening for a hole pattern; and etching the buried film and the inter-layer insulation film by using the second resist film as a mask to form a hole in the inter-layer insulation film.
A process for forming a dual damascene wiring according to a third aspect of the present invention comprises the steps of forming a first inter-layer insulation film on a lower conductive layer; forming, on the first inter-layer insulation film, a first resist film provided with an opening for a hole pattern; etching the first inter-layer insulation film by using the first resist film as a mask to form a hole; filling the hole with a material having a higher etching rate than the first inter-layer insulation film to form a buried film; forming a second inter-layer insulation film on the entire surface; forming, on the second inter-layer insulation film, a second resist film having an opening for a wiring groove pattern ; and etching the second inter-layer insulation film by using the second resist film as a mask to form a wiring groove.
In the first and third aspects of the present invention, the etching for forming the wiring groove is carried out after the buried film is filled in the hole.
In this case, the buried film uses a material having a higher etching rate than the inter-layer insulation film and hence the etching rate of the buried film is higher than that of the inter-layer insulation film. After the wiring groove is formed, the level of the surface of the buried film left in the hole is lower than the upper edge of the hole. Consequentially, in the step of etching the inter-layer insulation film for the purpose of the formation of the wiring groove, such a phenomenon that the buried film serves as an etching mask to leave an etching residue of the inter-layer insulation film never occurs thereby avoiding the residual of such a projection substance as found in the conventional art technology.
In the second aspect of the present invention, after the wiring groove is formed on the inter-layer insulation film, the wiring groove is filled with the buried film having a higher etching rate than the interlayer insulation film and thereafter etching is carried out to form a hole. No etching residue of the interlayer insulation film is left on the side of the hole accordingly. Other kinds of cavities may be formed in the interlayer insulation film and subsequently filled in like manner.
BRIEF DESCRIPTION OF THE DRAWINGS Preferred features of the present inven'rion wSll now be described, by way of example only, with reference to the accompanying drawings, in which: FIG. 1A to FIG. 1C are sectional views showing a process for forming a conventional dual damascene wiring in step order.
FIG. 2A to FIG. 2D are sectional views showing a process for forming another conventional dual damascene wiring in step order.
FIG. 3A to FIG. 3F are sectional views showing a process for forming a dual damascene wiring according to a first embodiment of the present invention in step order.
FIG. 4A to FIG. 4C are sectional views showing a process for forming a dual damascene wiring according to a second embodiment of the present invention in step order.
FIG. 5A to FIG. 5F are sectional views showing a process for forming a dual damascene wiring according to a third embodiment of the present invention in step order.
FIG. 6A to FIG. 6C are sectional views showing a process for forming a dual damascene wiring according to a fourth embodiment of the present invention in step order.
FIG. 7A to FIG. 7F are sectional views showing a process for forming a dual damascene wiring according to a fifth embodiment of the present invention in step order.
FIG. 8A to FIG. 8F are sectional views showing a process for forming a dual damascene wiring according to a sixth embodiment of the present invention in step order.
FIG. 9A to FIG. 9F are sectional views showing a process for forming a dual damascene wiring according to a seventh embodiment of the present invention in step order.
FIG. 10A to FIG. lOF are sectional views showing a process for forming a dual damascene wiring according to an eighth embodiment of the present invention in step order.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be hereinafter explained in detail with reference to the appended drawings. FIG. 3A to FIG. 3F are sectional views showing a process for forming a dual damascene wiring according to a first embodiment of the present invention in step order. As shown in FIG. 3A, an interlayer insulation film 22 such as a silicon oxide film is formed on a conductive layer 21 and a resist film 23 is applied to the inter-layer insulation film 22.
Thereafter, the resist film 23 is exposed and developed to form an opening pattern 31 for forming a via-hole.
The conductive layer 21 is a substrate formed with a lower wiring of multilayer interconnection structure or with a semiconductor device. The inter-layer insulation film 22 has a thickness sufficient to form a wiring groove and a via-hole (hereinafter a contact hole is also called via-hole"). The resist film 23 is a photosensitive organic film used for forming a via-hole.
Incidentally, in the case where the conductive layer 21 is a lower wiring of a multilayer interconnection, a hole formed in an inter-layer insulation film above the conductive layer is called a through-hole, and in the case where the conductive layer 21 is a semiconductor substrate, a hole formed in an inter-layer insulation film above the conductive layer is called a contact hole.
However, such holes including the through-hole and the contact hole are called a via-hole in the present invention.
Then, using the resist film 23 as a mask, the inter-layer insulation film 22 is etched to form a viahole 32 in the inter-layer insulation film 22. In this case, a small part of the inter-layer insulation film 22 remains within the via-hole 32.
Next, as shown in FIG. 3B, the resist film 23 is removed and a material differing from the inter-layer insulation film 22 is filled in the via-hole 32 to form a buried film 24. Examples of the buried film 24 include inorganic films such as Si, N, SiON (SiOyN,), oxide films (Sio2) and SiOF (SiXOyFz) or polysilicons, organic oxides (coating film) and inorganic oxides (coating film). Each etching rate of these materials is higher than that of the material constituting the inter-layer insulation film 22 such as a silicon oxide. The ratio of the etching rate of the inter-layer insulation film 22 to that of the buried film 24 is less than 1. Because each of usual inorganic materials has a higher etching rate than an oxide, various materials may be used as the buried film 24. This buried film 24 may be formed by, for example, CvD (a chemical vapor deposition method) or application.
The buried layer 24 is, for example, a CVDSi, N, film.
Then, a resist film 25 made of a photosensitive organic film is applied to the buried film 24 and the resist film 25 is patterned using photolithography to form a pattern 33 of a wiring groove. The ratio of the etching rate of the inter-layer insulation film (silicon oxide film) 22 to that of the resist film (sensitive organic film) 25 is 5 or more, for example.
After that, as shown in FIG. 3C, the buried film 24 and the inter-layer insulation film 22 are etched using the resist film 25 as a mask to form a wiring groove 34.
In this case, the inter-layer insulation film 22 has a higher etching rate than the resist film 25 as aforementioned (the ratio of etching rates is 5 or more).
Hence, the inter-layer insulation film 22 is etched into the form of a wiring groove by using the resist film 25 as a mask. Also, since the ratio of the etching rate of the inter-layer insulation film 22 to that of the buried film 24 is less than 1 and hence the etching rate of the buried film 24 is higher than that of the inter-layer insulation film 22, the buried film 24 is etched faster than the inter-layer insulation film 22. For this, as shown in FIG. 3C, the upper surface of the buried film 24 within the via-hole 32 is positioned at lower level than the top edge of the via-hole 32. As the etching method, plasma etching using a mixture gas of CBF3 gas, 02 gas and Ar gas may be used. The ratio of the etching rate of the inter-layer insulation film to that of the buried film in this case is 1 or less.
After that, as shown in FIG. 3D, the resist film 25 which is a photosensitive organic film for forming a wiring grooveand the buried film 24 are. removed in a manner that the inter-layer insulating film 22 is only slightly eroded. For the removal of the buried film 24, plasma etching using a mixture gas of C12 gas and HBr gas may be used. The ratio of the etching rate of the buried film 24 to that of the inter-layer insulation film 22 is 10 or more in this case. Also, any of wet etching, isotropic dry etching, anisotropic dry etching and the like may be used to remove the buried film 24. in this case, for example, CFyH, gas, 2 gas, C12 gas, EBr gas or SF6 gas may be used as a process gas for the isotropic dry etching. As a process gas of the anisotropic dry etching, for example, CxFyH= gas, 02 gas, C12 gas, HBr gas or SF6 gas may also be used.
Further, the inter-layer insulation film 22 left on the bottom of the via-hole 23 is removed at the same time as, or after, the buried film 24 is removed. This renders a via-hole 32 and a wiring groove 34 to be formed.
After that, as shown in FIG. 3E, a wiring material 26 (conductive material) is filled in the via-hole 32 and the wiring groove 34.
Then, as shown in FIG. 3F, the surface of the wiring material 26 is polished by CMP to expose the surface of the inter-layer insulation film 22. This results in the formation of a via 35 in the via-hole 32 and in the formation of a wiring 36 in the wiring groove 34.
In this embodiment structured in the above manner, even if the side wall of the via-hole 32 is inclined with the upper opening thereof being spread, the buried film 24 does not serve as a mask which prevents the etching of the inter-layer insulation film 22 when the inter-layer insulation film is etchedsince the buried film 24 is etched faster than the inter-layer insulation film 22 in the step of forming the wiring groove 34. pence, no etching residue of the inter-layer insulation film is left and unlike the conventional art technology, no projecting substances are intermingled in the wiring.
Also, in the etching step for forming the via-hole 32 in this embodiment, as shown in FIG. 3A, the etching is stopped on the way to leave a small part of the interlayer insulation film 22 on the bottom of the via-hole 32.
Specifically, for the etching of a large part of the inter-layer insulation film 22 and for the etching of the residual buried film 24 left in the via-hole 32, dry etching with high energy is adopted to shorten the treating time and thereafter wet etching or an etching method using low energy is adopted, whereby, for instance, damages to a diffused layer in the case where the conductive layer 21 is a substrate can be prevented.
Next, a second embodiment of the process according to the present invention will be explained with reference to FIG. 4A to FIG. 4C. Firstly, as shown in FIG. 4A, a first inter-layer insulation film 22a made of a material having a lower etching rate than a material to be buried is formed on a silicon substrate 21. Then, a second inter-layer insulation film 22b, made of a material having a higher etching rate than the material to be buried, is formed on the first inter-layer insulation film 22a. In this embodiment, as stated above, the inter-layer insulation film is a laminate of different materials.
Thereafter, a resist film 23 is applied to the second inter-layer insulation film 22b. A pattern 31 of a viahole is formed on the resist film 23 by patterning.
After that, using the resist film 23 as a mask, the first and second inter-layer insulation films 22a, 22b are etched to form a via-hole 32.
Next, as shown in FIG. 4B, the resist film 23 is removed and in succession a material differing from the inter-layer insulation films is filled in the via-hole 32 to form a buried film 24. Thereafter, a resist film 25 is formed on the buried film 24 to form a wiring groove pattern 33 on the resist film 25.
After that, as shown in FIG. 4C, the buried film 24 and the second inter-layer insulation film 22b are etched using the resist film 25 as a mask. The etching in this case is carried out in the condition that the etching rate of the second inter-layer insulation film 22b becomes higher than that of the buried film 24 and the etching rate of the first inter-layer insulation film 22a becomes lower than that of the buried film 24. Therefore, in this etching step, the part of the buried film 24 on the second inter-layer insulation film 22b is etched and thereafter the second inter-layer insulation film 22b and the buried film are etched and removed based on the wiring groove pattern 33 of the resist film 25. Then the etching extends to the first inter-layer insulation film 22a. In the first inter-layer insulation film 22a, the etching rate of the buried film 24 is larger than that of the inter-layer insulation film 22a. Hence the first inter-layer insulation film 22a is only slightly etched, and the buried film 24 within the via-hole 32 is etched preferentially. When the buried film 24 within the viahole 32 is slightly etched, the etching is stopped.
The subsequent steps are the same as those of the first embodiment shown in FIG. 3D to FIG. 3F.
Specifically, the resist film 25 and the buried film 24 are removed to form a wiring groove 34 and a via-hole 32.
Thereafter, a conductive material is filled in the wiring groove 34 and the via-hole 32 and the surface of the conductive material is polished by CEP to form a wiring and a via-hole like those shown in FIG. 3F.
In this embodiment, the laminate film consisting of materials having different etching rates is used as the inter-layer insulation filmland etching is terminated based on a change in etching rate when the etching of the second inter-layer insulation film is shifted to the etching of the first inter-layer insulation film, making it possible to discriminate the wiring groove from the via-hole clearly. In this embodiment, therefore, each depth of the wiring groove and the via-hole can be controlled by each thickness of the first and second inter-layer insulation films 22a, 22b. In contrast with the case of controlling each depth of a wiring groove and a via-hole on the basis of etching time and the like as in the first embodiment, the depth of a wiring groove and the like can be controlled more exactly.
Next, a third embodiment of the present invention will be explained with reference to FIG. 5A to FIG. 5F.
In this embodiment, as shown in FIG. 5A, a material differing from the inter-layer insulation film 22 is formed as an etching stopper layer 27 on a silicon substrate 21. On the etching stopper layer 27, an interlayer insulation film and a resist film 23 are formed.
Thereafter, a via-hole pattern 31 is formed on the resist film and the inter-layer insulation film 22 is etched using the resist film 23 as a mask. In this case, etching is stopped by the stopper layer 27 under the inter-layer insulation film 22. via-hole 32 is thereby formed without damaging the surface of the conductive layer 21 by etching.
Next, as shown in FIG. 5B, a material differing from the inter-layer insulation film is filled in the via-hole 32 to form a buried film 24. Thereafter, as shown in FIG. 5C, the buried film 24 and the inter-layer insulation film 22 are etched to a predetermined depth by using, as a mask, a resist film 25 formed with a wiring groove pattern 33. A wiring groove 34 is thus formed.
After that, as shown in FIG. 5D, the resist film 25 and the buried film 24 are removed. The etching stopper layer 27 within the via-hole 32 is removed at the same time when or after the buried film 24 is removed.
Thereafter, as shown in FIG. 5E, a wiring material 26 is filled in the via-hole 32 and the wiring groove 34.
In succession, as shown in FIG. 5F, the surface of the wiring material 26 is polished by CMP to form a wiring 36 and a via 35.
In this embodiment, since the etching stopper layer 27 is formed on a lowermost conductive layer 1, there is no feax that the conductive layer 1 is damaged by etching.
Hence, when the conductive layer 1 is a silicon substrate, devices incorporated in the substrate are prevented from being damaged.
Next, a fourth embodiment of the present invention will be explained with reference to FIG. 6A to FIG. 6C.
In this embodiment, as shown in FIG. 6A, an inter-layer insulation film 22 is etched using the resist film 23 to form a via-hole 32 in the inter-layer insulation film 22 in the same manner as in the first embodiment illustrated by FIG. 3A to FIG. 3F.
In succession, as shown in FIG. 6B, a material differing from an inter-layer insulation film is filled in the via-hole 32 to form a buried film 24. Generally, when the buried film 24 is filled in the via-hole 32, the buried film 24 is also formed on the inter-layer insulation film 22 as shown in FIG. 3B. However, in this embodiment, the buried film 24 is allowed to remain only in the via-hole 32 and the buried film 24 on the interlayer insulation film 22 is all removed.
After that, a resist film 25 is applied to the inter-layer insulation film 22 to form a pattern 33 of a wiring groove on the resist film 25.
In succession, as shown in FIG. 6C, the inter-layer insulation film 22 is etched using the resist film 25 as a mask to form a wiring groove 34. The etching is stopped after the etching is extended to the depth of the wiring groove 34. After that, the resist film 25 and the buried film 24 are removed and thereafter a wiring and a via are formed in the same steps that are shown in FIG.
3D to FIG. 3F.
In this embodiment, since the wiring groove is etched after the buried film, which has a high etching rate and is formed on the inter-layer insulation film, is removed, no etching progresses in a lateral direction between the resist film 25 and the inter-layer insulation film 22. This ensures that the corners of the upper edge of the wiring groove 34 are not dulledoand the wirinq groove 34shaving a shape which accords highly accurately with the thape defined by the wiring pattern 33 of the resist film 25 is formed.
Next, a fifth embodiment of the present invention will be explained with reference to FIG. 7A to FIG. 7F.
Firstly, as shown in FIG. 7A, an inter-layer insulation film 22 is formed on a conductive layer 21, and on the inter-layer insulation film 22 a resist film 25 is then formed. A wiring groove pattern 33 is formed on the resist film 25. Thereafter, a part in the direction of the thickness of the inter-layer insulation film 22 is etched using the resist film 25 as a mask to thereby form a wiring groove 34 above the inter-layer insulation film 22. The etching is stopped when the etching is extended to the depth of the wiring groove 34.
Then, as shown in FIG. 7B, the wiring groove 34 is filled with a buryi resist film 23 is the lowest.
Next, as shown in FIG. 7D, the resist film 23 and the buried film 24 are removed to form a wiring groove 34 and a via-hole 32.
After that, as shown in FIG. 7E, the wiring groove 34 and the via-hole 32 are filled with a wiring material 26. As shown FIG. 7F, the surface of the wiring material 26 is polished by CMP to expose the inter-layer insulation film 22. A wiring 36 and a via 35 are thus formed.
In this embodiment, the same effect that is obtained in the first embodiment illustrated by FIG. 3A to FIG. 3F is produced. Because the buried film 24 having a high etching rate is formed on the upper edge of the via-hole 32 in the inter-layer insulation film 22, a part of the buried film 24 is slightly removed in a lateral direction by etching. So, no projection is left on the upper side edge of the via-hole.
Next, a sixth embodiment of the present invention will be explained with reference to FIG. 8A to FIG. 8F.
This embodiment is different from the embodiment shown in FIG. 7A to FIG. 7F only in the point that an etching stopper 27 is formed. In this embodiment, as shown in FIG. 8A, the etching stopper layer 27 is formed on a conductive layer 21 and thereafter a wiring groove 34 is formed on an inter-layer insulation film 22 by using a resist film 25 as a mask. As shown in FIG. 8B, a buried film 24 is filled in the wiring groove 34 and, as shown in FIG. 8C, the buried film 24 and the inter-layer insulation film 22 are etched using the resist film 23 as a mask. The etching is stopped when it is extended to the etching stopper layer 27.
Next, as shown in FIG. 8D, the etching stopper layer 27 left in the via-hole 32 is removed by etching, a wiring material 26 is filled as shown in FIG. 8E, and the wiring material 26 is polished by CMP to form a wiring 36 and a via-hole 35 as shown in FIG. 8F.
In this embodiment, in addition to the same effect that is obtained in the embodiment explained by FIG. 7A to FIG. 7F, there is the effect that, in the case where the conductive layer 21 is a substrate, any damages to the substrate can be prevented} as in the embodiment explained by FIG. 5A to FIG. 5F.
In a modification of the embodiment shown in FIG.
7A to FIG. 7F, etching may be stopped early and the inter-layer insulation film left unremoved may be removed at the same time when or after the buried film is removed in the step of forming a via-hole by etching like the embodiment shown in FIG. 3A to FIG. 3F. Also, a laminate consisting of different materials may be used as the inter-layer insulation film as in the embodiment shown in FIG. 4A to FIG. 4C. Moreover, after a buried film is filled in a via-hole, the buried film may be allowed to be left only in the via-hole and the remainder portion may be entirely removed in the same manner as in the embodiment shown in FIG. 6A to FIG. 6c.
Next, a seventh embodiment of the present invention will be explained with reference to FIG. 9A to FIG. 9F.
In this embodiment, firstly as shown in FIG. 9A, a first inter-layer insulation film 22 having a thickness enough to form a via-hole is formed on a conductive layer 21, a resist film 23 is formed on the first inter-layer insulation film 22. and a via-hole pattern 31 is formed on the resist film 23. Then, the first inter-layer insulation film 22 is etched using the resist film 23 as a mask to form a via-hole 32.
Thereafter, as shown in FIG. 9B, the via-hole 32 is filled with a buried film 24 and a second inter-layer insulation film 28 having a thickness sufficient to form a wiring groove on the buried film 24 is formed.
Then, as shown in FIG. 9C, a resist film 25 is formed on the second inter-layer insulation film 28 and a wiring groove pattern 33 is formed on the resist film 25.
Using this wiring groove pattern 33, the second interlayer insulation film 28 is etched to form a wiring groove 34. The etching in this case is carried out in the condition that the etching rate of the buried film 24 is higher than those of the first inter-layer insulation film 22 and second inter-layer insulation film 28, and the etching rate of the inter-layer insulation film 28 is higher than that of the resist film 25. In addition, the etching is stopped when the first inter-layer insulation film 22 is exposed.
After that, as shown in FIG. 9D, the resist film 25 and the buried film 24 in the via-hole 32 are removed in a manner that the first inter-layer insulation film 22 and the second inter-layer insulation film 28 are only slightly eroded.
Then, as shown in FIG. 9E, a wiring material 26 is filled in the wiring groove 34 and the via-hole 32 and polished by CMP to form a wiring 36 and a via 35 shown in FIG. 9F.
In this embodiment, as shown in FIG. 9C, since the etching rate of the buried film 24 is higher than that of the first inter-layer insulation film 22, the level of the buried film 24 left unremoved in the via-hole 32 is lower than the surface of the first inter-layer insulation film 22. Hence, the upper edge of the buried film 24 does not serve as a mask in the etching of the first inter-layer insulation film 22. No etching residue of the first inter-layer insulation film 22 is left accordingly.
Next, an eighth embodiment of the present invention will be explained with reference to FIG. 10A to FIG. IOF.
This embodiment is different from the embodiment shown in FIG. 9A to FIG. 9F in the point that a buried film 24 is allowed to remain only in a via-hole 32 and the remainder portion of the buried film 24 is removed as shown in FIG. lOB.
As is clear from the comparison of FIG. 9C to FIG.
9F with FIG. 10C to FIG. 10F, this embodiment has the advantage that no residual buried film 24 is left between a first inter-layer insulation film 22 and a second inter-layer insulation film 28and hence a material of the buried film is selected from a wide range of materials.
In a modification of the embodiment shown in FIG.
9A to 9F, an etching stopper layer may be formed between the conductive layer 21 and the first inter-layer insulation film 22 as in the embodiment shown in FIG.
5A to FIG. 5F. Also, as shown in FIG. 3A to FIG. 3F, a small part of the inter-layer insulation film 22 is allowed to remain in the formation of the via-hole 32, and the inter-layer insulation film 22 left unremoved may be removed at the same time when and after the buried film 24 is removed.
As is described in detail, according to the present invention, no etching residue of an inter-layer insulation film is left in an etching step of forming a wiring groove and a hole in the inter-layer insulation film, and hence no residual projection material of the inter-layer insulation film is intermingled in a wiring with the result that the quality of wiring can be improved.
While the present invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation, and that changes may be made to the invention without departing from its scope as defined by the appended claims.
Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
The text of the abstract filed herewith is repeated here as part of the specification.
In a process for forming a dual damascene wiring, an inter-layer insulation film is formed on a lower conductive layer, and a resist film having an opening for a via-hole pattern is formed in the inter-layer insulation film.
Using the resist film as a mask, the inter-layer insulation film is etched to form a via-hole, and the via-hole is filled with a material having a higher etching rate than the inter-layer insulation film to form a buried film.
Thereafter, a resist film having an opening for a wiring groove pattern is formed on the buried film, and the buried film and the inter-layer insulation film are etched using the resist film as a mask to form a wiring groove on the inter-layer insulation film. The process ensures than any unacceptable substance caused by an etching residue of an inter-layer insulation film does not remain in an etching step; thus wiring can be produced which is not inferior.

Claims (15)

  1. CLAIMS: 1. A process for forming a dual damascene wiring, the process comprising the steps of: forming a hole or groove in an inter-layer insulation film formed on a conductive layer, filling the hole or groove with a buried film having a higher etching rate than the inter-layer insulation film, and etching the buried film and the interlayer insulation film.
  2. 2. A process for forming a dual damascene wiring comprising the steps of: forming an inter-layer insulation film on a lower conductive layer; forming, on the inter-layer insulation film, a first resist film provided with an opening for a hole pattern; etching the inter-layer insulation film by using the first resist film as a mask to form a hole; filling the hole with a material having a higher etching rate than the inter-layer insulation film to form a buried film; forming, on the buried film, a second resist film having an opening for a wiring groove pattern; and, etching the buried film and the inter-layer insulation film by using the second resist film as a mask to form a wiring groove in the inter-layer insulation film.
  3. 3. A process for forming a dual damascene wiring comprising the steps of: forming an inter-layer insulation film on a lower conductive layer; forming, on the inter-layer insulation film, a first resist film provided with an opening for a wiring groove pattern; etching the inter-layer insulation film by using the first resist film as a mask to form a wiring groove; filling the wiring groove with a material having a higher etching rate than the inter-layer insulation film to form a buried film; forming, on the buried film, a second resist film having an opening for a hole pattern; etching the buried film and the inter-layer insulation film by using the second resist film as a mask to form a hole in the inter-layer insulation film.
  4. 4. A process for forming a dual damascene wiring comprising the steps of: forming a first inter-layer insulation film on a lower conductive layer; forming, on the first inter-layer insulation film, a first resist film provided with an opening for a hole pattern; etching the first inter-layer insulation film by using the first resist film as a mask to form a hole; filling the hole with a material having a higher etching rate than the first inter-layer insulation film to form a buried film; forming a second inter-layer insulation film on the entire surface; forming, on the second inter-layer insulation film, a second resist film having an opening for a wiring groove pattern; and, etching the second inter-layer insulation film by using the second resist film as a mask to form a wiring groove.
  5. 5. A process for forming a dual damascene wiring according to claim 2 or claim 4, further comprising the steps of: removing the buried film in the hole; and, filling the wiring groove and hole with a conductive material to form a wiring and a contact or a via at the same time.
  6. 6. A process for forming a dual damascene wiring according to claim 3, further comprising, after etching said hole, the steps of: removing the buried film on the inter-layer insulation film; and, filling the wiring groove and hole with a conductive material to form a wiring and a contact or a via at the same time.
  7. 7. A process for forming a dual damascene wiring according to any one of claims 2 to 4, wherein said etching to form a hole is performed by stopping the etching with a part of the inter-layer insulation film being left.
  8. 8. A process for forming a dual damascene wiring according to claim 7, wherein the inter-layer insulation film left in the hole is removed at the same time as, or after, the buried film is removed.
  9. 9. A process for forming a dual damascene wiring according to claim 2 or claim 3, wherein the inter-layer insulation film is a laminate film consisting of two materials which differ from each other in selective etching ratio, wherein the etching rate of the upper film is higher than that of the lower film.
  10. 10. A process for forming a dual damascene wiring according to any one of claims 2 to 4, further comprising forming an etching stopper layer between the lower conductive layer and the inter-layer insulation layer, wherein the etching in the etching to form a hole is stopped when the etching is extended to the etching stopper layer.
  11. 11. A process for forming a dual damascene wiring according to claim 2 or claim 3, further comprising, after forming a buried film, removing the buried film on the inter-layer insulation film with a part of the buried film being left only in the hole.
  12. 12. A process for forming a dual damascene wiring according to claim 4, further comprising, after forming a buried film, removing the buried film on the inter-layer insulation film.
  13. 13. A process for forming a dual damascene wiring according to any one of claim 2 to claim 13, wherein the lower conductive layer is a lower wiring and the hole is a via-hole.
  14. 14. A process for forming a dual damascene wiring according to any one of claim 2 to claim 13, wherein the lower conductive layer is a semiconductor substrate and the hole is a via-hole.
  15. 15. A process for forming a dual damascene wiring, substantially as herein described with reference to or as illustrated in Figures 3A to lOF.
GB9930205A 1998-12-21 1999-12-21 Process for forming dual damascene wiring Withdrawn GB2345189A (en)

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GB9930205D0 (en) 2000-02-09
KR20000048294A (en) 2000-07-25
JP3214475B2 (en) 2001-10-02
CN1258097A (en) 2000-06-28

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