JP2009111134A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing TDDB or a short-circuit between adjacent wiring even when the arrangement of via wiring is shifted in an interface direction. <P>SOLUTION: The semiconductor device includes, inside an insulating layer (part composed of 5, 11, 13 and 21) formed on a semiconductor substrate 1, first wiring 7, second wiring 15a disposed above the first wiring 7 and the via wiring 17 connecting the first wiring 7 and the second wiring 15a, and the upper surface S1 of the via wiring 17 is disposed lower than the upper surface S2 of the second wiring 15a. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having excellent TDDB (oxide film aging breakdown) characteristics and a method for manufacturing the same.

  In general, a semiconductor device includes a multilayer wiring on a semiconductor substrate. In a multilayer wiring (for example, in the case of a two-layer wiring) of a conventional semiconductor device, a first insulating layer 100 is formed on a semiconductor substrate 109 as shown in FIG. 10, and a first insulating layer 100 made of, for example, copper is formed in the first insulating layer 100. One wiring 101 is formed, a barrier metal film 102 is formed between the first insulating layer 100 and the first wiring 101, and a first liner film is formed so as to cover the entire upper surface of the first insulating layer 100 from above. 103 is formed. Then, the second insulating layer 104 is formed on the first liner film 103, the second wirings 105a and 105b are formed in the second insulating layer 104, and the second wiring 105a and the first wiring 101 are connected. A via wiring 106 made of, for example, copper is formed, and a barrier metal film 107 is formed between the second insulating layer 104, the second wiring 105a, 105b, and the via wiring 106, and the second insulating layer 104 is formed thereon. A second liner film 108 is formed so as to cover the entire upper surface.

  In recent years, TDDB (oxide film aging breakdown) between the via wiring 106 and the second wiring 105b has become severer over time. This TDDB greatly depends on the distance L1 on the interface between the via wiring 106 and the second wiring 105b. That is, as the distance L1 between the via wiring 106 and the second wiring 106b decreases, the electric field between the via wiring 106 and the second wiring 105b increases, and this electric field causes the second wiring 105a, 105b or the via wiring 106 to Metal ions ooze out from between the barrier metal film 108 and the second liner layer 107 and diffuse between the via wiring 106 and the second wiring 105b, causing the TDDB.

  In the conventional semiconductor device, since the upper surface of the via wiring 106 and the upper surface of the second wiring 105a are arranged on the same interface, the arrangement of the via wiring 106 is shifted in the interface direction (that is, the upper surface of the via wiring 106 is When the second wiring 105a is arranged so as to protrude laterally from the upper surface), the distance L1 between the via wiring 106 and the adjacent second wiring 105b is reduced, and the via wiring 106 and the second wiring 105b are reduced. TDDB and short circuit may occur between the two.

  Therefore, the present invention has been made to solve the above-described problems, and can prevent TDDB and a short circuit from occurring between adjacent wirings even when the via wirings are displaced in the interface direction. A semiconductor device and a manufacturing method thereof are provided.

  In order to solve the above-described problem, a first aspect of the present invention includes a first wiring, a second wiring disposed above the first wiring, and an insulating layer formed on a semiconductor substrate. A via wiring that connects the first wiring and the second wiring is provided, and an upper surface of the via wiring is disposed lower than an upper surface of the second wiring.

  According to the first aspect of the present invention, since the upper surface of the via wiring is arranged lower than the upper surface of the second wiring, the arrangement of the via wiring is shifted in the interface direction (that is, the upper surface of the via wiring is second. Even when the wiring is arranged so as to protrude laterally from the upper surface of the wiring), between the second wiring connected to the via wiring and another second wiring arranged adjacent to the second wiring. A sufficient distance on the interface can be secured, thereby preventing a TDDB or short circuit between adjacent wirings.

  As shown in FIG. 1, the semiconductor device according to this embodiment includes a multilayer wiring (for example, two-layer wiring in FIG. 1) 3 on a semiconductor substrate 1. In the multilayer wiring 3, a first insulating layer 5 made of, for example, SiOC is formed on the semiconductor substrate 1, and a first wiring 7 made of, for example, copper is formed in the first insulating layer 5, and these first insulating layers 5 are formed. A barrier metal film 9 is formed between the first wiring 7 and a first liner film 11 made of, for example, SiCN so as to cover the entire upper surface of the first insulating layer 5.

  Then, a second insulating layer 13 is formed on the first liner film 11, and second wirings 15a and 15b made of, for example, copper are formed in the second insulating layer 13, and the second wiring 15a and the first wiring 7 are formed. Via wiring 17 made of copper, for example, is formed, and a barrier metal film 19a is formed between the second insulating layer 13, the second wiring 15a, and the via wiring 17, and the second insulating layer 13 A barrier metal film 19b is formed between the second wiring 15b and a second liner film 21 made of, for example, SiCN is formed so as to cover the entire upper surface of the second insulating layer 13 from above.

  Each of the wirings 7, 15a, and 15b has, for example, an inverted cross-sectional shape (that is, a shape in which the lateral width becomes tapered from the upper surface to the lower surface (hereinafter the same)). The via wiring 17 is also formed as an inverted trapezoidal cross section as an example.

  The second wiring 15 a is disposed directly above the first wiring 7.

  The via wiring 17 is integrally connected to the second wiring 15a at the upper portion thereof, and is connected to the upper surface of the first wiring 17 through the barrier metal film 19a at the lower portion thereof.

  The via wiring 17 is arranged such that the upper surface S1 thereof is lower than the upper surface S2 of the second wiring 15a. Here, the via wiring 17 is further shifted so that the upper surface S1 projects laterally from the upper surface S2 of the second wiring 15a. Are arranged.

  For convenience of manufacturing, the second insulating layer 13 includes a second insulating layer upper layer (cap layer) 13a positioned above the upper surface S1 of the via wiring 17 and below the upper surface S2 of the second wiring 15a, and an upper surface S1 of the via wiring 17. It is comprised from the 2nd insulating layer main body layer 13b located below. Here, the second insulating layer body layer 13b is made of, for example, SiOC, and the second insulating layer upper layer 13a is made of the same material as the second insulating layer body layer 13b or a material having higher etching resistance (for example, TEOS).

  The numbers of the wirings 7, 15a, 15b and the via wirings 17 are not limited as described above.

  In this embodiment, the first insulating layer 13, the second insulating layer 5, the first liner film 11 and the second liner film 21 form an insulating layer.

  Next, a method for manufacturing this semiconductor device will be described.

  First, as shown in FIG. 2, a first insulating layer 5 made of, for example, SiOC is formed on the semiconductor substrate 1. Then, a first wiring groove 19 is formed on the upper surface of the first insulating layer 5, a barrier metal film 9 is formed on the inner surface of the first insulating layer 5, and the first wiring 7 made of, for example, copper is formed in the first wiring groove 19 from above. Form. In this state, the upper surface of the first insulating layer 5 and the upper surface of the first wiring 7 are flat.

  Then, as shown in FIG. 3, a first liner film 11 made of, for example, SiCN is formed to a thickness of several tens of nanometers by, for example, a CVD method so as to cover the entire upper surface of the first insulating layer 5. Then, a second insulating layer main body layer 13b made of, for example, SiOC is formed thereon with a thickness of, for example, several hundred nm.

  Then, as shown in FIG. 4, a via wiring hole 23 is formed on the upper surface of the second insulating layer body layer 13b. That is, a resist film for the via wiring hole 23 is patterned on the upper surface of the second insulating layer body layer 13b by physography, and the second insulating layer body layer 13b is partially etched away using the first liner film 11 as a stopper. Then, a via wiring hole 23 is formed, and the resist film is removed. In FIG. 4, the via wiring holes 23 are arranged so as to be shifted laterally from directly above the first wiring 7.

  Then, as shown in FIG. 5, the filling material 25 is buried in the via wiring hole 23, and the upper surface of the filling material 23 and the upper surface of the second insulating layer main body layer 13b are flattened by etch back or the like. As the filling material 23, a material having a faster etching rate than the second insulating layer main body layer 13b and the second insulating layer upper layer 13a described later is used. As such a material, here, a coating-type oxide film-based inorganic material (for example, SOG (Spin on Glass)) is used.

  Then, a second insulating layer upper layer (cap layer) 13a made of, for example, SiOC or TEOS is formed on the entire upper surface of the second insulating layer main body layer 13b by, eg, CVD.

  Then, as shown in FIG. 6, grooves 27a and 27b for the first wiring are formed on the upper surface of the second insulating layer 13 including the second insulating layer main body layer 13b and the second insulating layer upper layer 13a. That is, a resist film for the second wiring grooves 27a and 27b is patterned on the upper surface of the second insulating layer 13 by physography, and the second insulating layer 13 and the filling material 25 are partially etched away to be used for the second wiring. Grooves 27a and 27b are formed, and the resist film is removed. In FIG. 6, the first wiring groove 27 a is disposed directly above the first wiring 7 so as to communicate with the upper portion of the via wiring hole 23. That is, the upper surface S1 of the via wiring hole 25 is arranged so as to be shifted from the upper surface S2 of the first wiring groove 27a so as to protrude laterally.

  Then, as shown in FIG. 7, the filling material 25 in the via wiring hole 23 is removed through the first wiring groove 27a by wet processing (for example, HF cleaning processing).

  Then, as shown in FIG. 8, for example, the bottom of the via wiring hole 23 is removed by etching without a mask (for example, dry etching), so that the bottom of the via wiring hole 23 reaches the upper surface of the first wiring 9. .

  As shown in FIG. 9, barrier metal films 19a and 19b are formed on the inner surfaces of the second wiring grooves 27a and 27b and the inner surfaces of the via wiring holes 23 by, eg, CVD. Then, a plating seed film (not shown) made of, for example, copper is formed on the barrier metal films 19a and 19b by, for example, a CVD method, an electrode is connected to the plating seed film, and electroplating is performed. The second wiring 15a made of, for example, copper and the via wiring 17 are integrally formed inside the groove 27a and the via wiring hole 23, and the second wiring 15b made of, for example, copper is formed in the second wiring groove 27b. .

  Then, as shown in FIG. 1, a second liner film 21 made of, for example, SiCN is formed on the entire upper surface of the second insulating layer upper layer 13a. In this way, the semiconductor device is formed.

  According to the semiconductor device configured as described above, since the upper surface S1 of the via wiring 17 is disposed lower than the upper surface S2 of the second wiring 15a, the arrangement of the via wiring 17 is shifted in the interface direction (that is, Even when the upper surface S1 of the via wiring 17 is shifted so as to protrude laterally from the upper surface S2 of the second wiring 15a), the second wiring 15a connected to the via wiring 17 and the second wiring 15a are adjacent to each other. A sufficient distance L1 on the interface between the second wiring 15b and the second wiring 15b can be secured, thereby preventing a TDDB or short circuit between the adjacent wirings 15a and 15b.

  The second insulating layer 13 includes an insulating layer main body layer 13b positioned below the upper surface S1 of the via wiring 17, and an insulating layer upper layer positioned above the upper surface S1 of the via wiring 17 and below the upper surface S2 of the second wiring 15a. 13a, the upper surface S1 of the via wiring 17 can be easily placed lower than the upper surface S2 of the second wiring 15a during manufacturing.

  Since the barrier metal films 19a and 19b are formed between the second wiring 15a and 15b and the via wiring 17 and the second insulating layer 13, the via wiring 17 is displaced in the interface direction and approaches another adjacent second wiring 15b. Even if the electric field between the wirings 17 and 15b becomes strong, the barrier metal films 19a and 19b can prevent the metal ions from the wirings 17 and 15b from leaking into the second insulating layer 13, and this. Therefore, TDDB can be prevented.

  The via wiring hole 23 is formed in the second insulating layer main body layer 13b, the embedding material 25 is embedded in the via wiring hole 23, and the second insulating layer main body layer 13b is covered with the embedding material 25. The second wiring layer upper layer 13a is formed, and the second wiring groove is formed in the second insulating layer 13 including the second insulating layer main body layer 13b and the second insulating layer upper layer 13a so as to communicate with the via wiring hole 23. 27a is formed, the filling material 25 embedded in the via wiring hole 23 is removed through the second wiring groove 27a, and the via wiring 17 and the second wiring are placed in the via wiring hole 23 and the second wiring groove 27a. 15a is integrally formed, so that the arrangement of the via wiring hole 23 is shifted in the interface direction (that is, the upper surface S1 of the via wiring hole 23 is stretched to the side of the upper surface S2 of the second wiring groove 27a). Even if they are shifted so that they come out) A sufficient distance L1 on the interface between the second wiring 15a connected to the line 17 and another second wiring 15b disposed adjacent to the second wiring 15a can be ensured, whereby the adjacent wirings 15a and 15b are adjacent to each other. TDDB and a short circuit can be prevented from occurring between them.

  Since the filling material 25 is a material (for example, SOG) having a faster etching rate than the second insulating layer main body layer 13b and the second insulating layer upper layer 13a, the arrangement of the via wiring holes 23 is shifted in the interface direction, Even if the eaves structure H (see FIG. 7) occurs in the connection portion between the two wiring grooves 27a and the via wiring holes 23, the filling material 25 in the via wiring holes 23 is replaced with the second wiring grooves 27a and the via wirings. It can be quickly removed without damaging the service hole 23.

  Since the embedding material 25 is removed by the wet process, the embedding material 25 can be quickly removed.

  Further, since the barrier metal films 19a and 19b are formed by the CVD method, the arrangement of the via wiring holes 23 is shifted in the interface direction, and the eaves structure H (in the connecting portion between the second wiring grooves 27a and the via wiring holes 23 is provided. Even if this occurs, the barrier metal film 19a can be appropriately formed on the ridge structure portion.

  Since the plating seed film (not shown) is formed by the CVD method, the arrangement of the via wiring hole 23 is shifted in the interface direction, and the eaves structure H is formed at the connection portion between the second wiring groove 27a and the via wiring hole 23. Even if (see FIG. 7) occurs, the plating seed film can be appropriately formed on the ridge structure portion.

  In this embodiment, when the via wiring 17 is arranged so as to be shifted in the interface direction from right above the first wiring 7 (that is, the upper surface S1 of the via wiring 17 is stretched to the side of the upper surface S2 of the second wiring 15a). However, the present invention is not limited to such a case. For example, the via wiring 17 may be disposed immediately above the first wiring 7.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. 2 is a view showing a state in which a first wiring 7 and a barrier metal film 9 are formed in the first insulating layer 5. FIG. It is a figure which shows the state which formed the 1st liner 11 and the 2nd insulating layer main body layer 13b on the 1st insulating layer 5. FIG. It is a figure which shows the state which formed the hole 23 for via wiring in the 2nd insulating layer main body layer 13b. It is a figure which shows the state which embedded the embedding material 25 in the via | veer wiring hole 23, and formed the 2nd insulating layer upper layer 13a on the 2nd insulating layer main body layer 13b. FIG. 6 is a view showing a state in which second wiring grooves 27a and 17b are formed in the second insulating layer 13. FIG. 6 is a view showing a state where a filling material 25 in a via wiring hole 23 is removed. It is a figure showing the bottom of via wiring hole 23 reaching the upper surface of the first wiring by etching. FIG. 6 is a diagram showing a state in which second wirings 15a, 15b and via wirings 17 are formed in second wiring grooves 27a, 27b and via wiring holes 23; It is a cross-sectional schematic diagram of a conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3 Multilayer wiring, 5 1st insulating layer, 7 1st wiring, 9 Barrier metal film, 11 1st liner film, 13 2nd insulating layer, 13a 2nd insulating layer upper layer, 13b 2nd insulating layer main body Layer, 15a, 15b second wiring, 17 via wiring, 19 first wiring groove, 21 first liner film, 23 via wiring hole, 25 filling material, 27a, 27b second wiring groove, interface between L1 wiring Distance above, H 庇 structure.

Claims (9)

In an insulating layer formed on the semiconductor substrate, a first wiring, a second wiring disposed above the first wiring, and a via wiring that connects the first wiring and the second wiring are provided. ,
The semiconductor device according to claim 1, wherein an upper surface of the via wiring is disposed lower than an upper surface of the second wiring.   The insulating layer includes an insulating layer body layer positioned below the upper surface of the via wiring and an insulating layer upper layer positioned above the upper surface of the via wiring and below the upper surface of the second wiring. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein a barrier metal film is formed between the second wiring and the via wiring and the insulating layer. A first step of forming a first wiring in a first insulating layer formed on a semiconductor substrate;
A second step of forming a second insulating layer body layer on the first insulating layer;
A third step of forming a via wiring hole in the second insulating layer body layer;
A fourth step of embedding a filling material in the via wiring hole;
A fifth step of forming a second insulating layer upper layer on the second insulating layer body layer so as to cover the filling material;
A sixth step of forming a second wiring groove in the second insulating layer comprising the second insulating layer main body layer and the second insulating layer upper layer so as to communicate with the via wiring hole;
A seventh step of removing the filling material embedded in the via wiring hole through the second wiring groove;
An eighth step of integrally forming the via wiring and the second wiring in the via wiring hole and the second wiring groove;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the filling material is a material having an etching rate faster than that of the second insulating layer main body layer and the second insulating layer upper layer.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the filling material is SOG (Spin on Glass).   5. The method of manufacturing a semiconductor device according to claim 4, wherein the removal in the seventh step is removal by wet processing.   9. The eighth step of forming the via wiring and the second wiring after forming a barrier metal film on the inner surface of the via wiring hole and the second wiring groove by a CVD method. 5. A method for manufacturing a semiconductor device according to 4.   In the eighth step, a plating seed film is formed on the barrier metal film by a CVD method, an electrode is connected to the plating seed film, and the via wiring and the second wiring are formed by electroplating. A method for manufacturing a semiconductor device according to claim 8.

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