CN101459123B - Through hole and dual damascene structure forming method - Google Patents
Through hole and dual damascene structure forming method Download PDFInfo
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- CN101459123B CN101459123B CN2007100945398A CN200710094539A CN101459123B CN 101459123 B CN101459123 B CN 101459123B CN 2007100945398 A CN2007100945398 A CN 2007100945398A CN 200710094539 A CN200710094539 A CN 200710094539A CN 101459123 B CN101459123 B CN 101459123B
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Abstract
The invention discloses a method of forming through holes comprises steps of providing a substrate, forming an etch stop layer on the substrate, arranging a dielectric layer on the etch stop layer, detecting the thickness of the dielectric layer, determining processing conditions of the follow-up etching process according to the thickness of the dielectric layer, forming a through hole pattern onthe dielectric layer, and then etching the dielectric layer according to the processing conditions to form a through hole. The invention further correspondingly discloses a method of forming a dual damascene structure. By utilizing the methods of forming the through hole and the dual damascene structure, over-etching or under-etching can be effectively avoided, thereby increasing forming quality of the through hole or the dual damascene structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the formation method of particularly a kind of through hole and dual-damascene structure.
Background technology
Integrated circuit fabrication process is a kind of plane manufacture craft, and it forms a large amount of various types of complex devices in conjunction with kinds of processes such as photoetching, etching, deposition, ion injections on same substrate, and it is connected to each other to have complete electric function.Wherein, deviation appears in any step process, all may cause the performance parameter off-design value of circuit.
Formation method with through hole is an example: often need in the semiconductor fabrication process to make a large amount of through holes, to form interconnection line in the conductive layer more than two-layer.The formation quality of this through hole is very big for the performance impact of circuit, especially for the following technology of 65nm, if deviation appears in its process results, will cause the electrical property variation of circuit, and device is with cisco unity malfunction when serious.
Traditional through hole forms in the technology, and the dielectric layer that is used to insulate between each conductive layer often adopts silica material, and it is still all comparatively ripe in etching technics at depositing operation, thereby stronger to the quality control power of the through hole that utilizes its formation.
Development along with semiconductor integrated circuit, and to the demand of high speed device, after entering the 65nm technology,, need utilize the dielectric layer of copper and low k value (low dielectric constant) to realize the interlayer electrical interconnection usually for further reducing the interconnect delay of metallic resistance and chip.Yet the depositing operation of wherein used low k value dielectric layer is also immature, and unsatisfactory to the control of its growth thickness in the technology at present, this has had influence on the formation quality of through hole.
Fig. 1 to 5 has illustrated a kind of device profile schematic diagram of formation method of traditional through hole; simply introducing the formation method of through hole: Fig. 1 below in conjunction with Fig. 1 to Fig. 5 is the device profile map behind the formation etching stop layer in the existing through hole formation method; as shown in Figure 1; at first on substrate 101, deposit one deck etching stop layer 102; in the following technology of 65nm, this etching stop layer 102 is used the carborundum of nitrating usually.
Fig. 2 is the device profile map behind formation first dielectric layer in the existing through hole formation method, as shown in Figure 2, stopping deposition first dielectric layer 103 on the layer 102, this layer requirement is the layer of dielectric material of low k value, usually can be the silica material that utilizes chemical gaseous phase depositing process to form, as black diamond (BD, black Diamond).
Fig. 3 is for forming the device profile map behind the through hole in the existing through hole formation method in the ideal case, as shown in Figure 3, formed through hole 104 in this first dielectric layer 103, ideally, the etching technics of this step to through hole 104 should stop in the slower etching stop layer of etch rate 102.
Yet because low k value material deposition processes and immature in the prior art, not strong to the control ability of its deposit thickness, bigger fluctuation can take place in thickness usually that deposited between sheet and the sheet.In addition, because the dwindling of clear size of opening, the process window of the etching technics of through hole further reduces, and the accurate control ability of via etch is also become relatively poor.At this moment,, form in the technology of through hole, will occur the phenomenon of over etching or etching deficiency probably in this step etching if or else the fluctuation of thickness of dielectric layers is taken in.
Fig. 4 is the device profile map after forming through hole under the over etching situation in the existing through hole formation method, as shown in Figure 4, the thinner thickness of the first dielectric layer 103-1 deposition of the low k value of cause, the phenomenon of over etching has appearred in the through hole 104-1 that adopts identical etching condition to carry out forming after the etching, the etching stop layer 102 that not only is positioned under the first dielectric layer 103-1 is removed by complete etching, and substrate 101 also has been subjected to damage.
Fig. 5 is the device profile map after forming through hole under the situation of etching deficiency in the existing through hole formation method, as shown in Figure 5, the thickness that deposits because of the first dielectric layer 103-2 that hangs down the k value is thicker, the phenomenon of etching deficiency has appearred in the through hole 104-2 that adopts identical etching condition to carry out forming after the etching, the first dielectric layer 103-2 in the through hole is not removed fully.
At present, along with the device feature size of very lagre scale integrated circuit (VLSIC) scaled down constantly, integrated level constantly improves, and the control of each step process and the accuracy of process results thereof are had higher requirement.The above-mentioned through hole that prior art the forms dual-damascene structure of this through hole (or comprise) that utilizes is second-rate, can have influence on the electrical connection quality in the integrated circuit, can not satisfy the requirement of production, must solve.
The Chinese patent application that disclosed publication number was CN1545726 on November 10th, 2004 discloses the formation method of the copper vias in a kind of low k technology, this method strengthens adhesion between through hole and the copper layer by changing structure at the adhesion layer of through hole, solves the open circuit problem that it occurs after heat treatment.But this method can not solve the above-mentioned through hole that causes because of low k value cvd dielectric layer thickness fluctuation and form second-rate problem.
Summary of the invention
The invention provides the formation method of a kind of through hole and dual-damascene structure, to improve the second-rate problem of formation of through hole in the existing formation method or dual-damascene structure.
The formation method of a kind of through hole provided by the invention comprises step:
Substrate is provided;
On described substrate, form etching stop layer;
On described etching stop layer, form dielectric layer;
Detect the thickness of described dielectric layer;
Determine the process conditions of etching technics subsequently according to the thickness of described dielectric layer;
On described dielectric layer, form via hole image;
According to described process conditions described dielectric layer is carried out etching, to form through hole.
Alternatively, described dielectric layer is the dielectric layer of low k value.
Alternatively, described dielectric layer is the black diamond material layer.
Alternatively, the thickness of described dielectric layer is 3500 to 5000
Between.
Alternatively, described dielectric layer utilizes chemical gaseous phase depositing process to form.
Preferably, described process conditions comprise etch period.
Alternatively, described process conditions comprise operating room's air pressure at least, a kind of in etching gas flow or the etching power.
Alternatively, described etching stop layer is nitrogenous silicon carbide layer.
The present invention has the formation method of a kind of dual-damascene structure of identical or relevant art feature, comprises step:
Substrate is provided;
On described substrate, form etching stop layer;
On described etching stop layer, form first dielectric layer;
Detect the thickness of described first dielectric layer;
Determine the process conditions of etching technics subsequently according to the thickness of described first dielectric layer;
On described first dielectric layer, form via hole image;
According to described process conditions described first dielectric layer is carried out etching, to form through hole;
Form second dielectric layer on described first dielectric layer and in the through hole;
On described second dielectric layer, form groove figure;
Etching forms the groove that links to each other with at least one through hole.
Alternatively, described first dielectric layer is the dielectric layer of low k value.
Alternatively, described first dielectric layer is the black diamond material layer.
Alternatively, the thickness of described first dielectric layer is 3500 to 5000
Between.
Alternatively, described first dielectric layer utilizes chemical gaseous phase depositing process to form.
Alternatively, described etching stop layer is nitrogenous silicon carbide layer.
Preferably, described process conditions comprise etch period.
Alternatively, described process conditions comprise operating room's air pressure at least, a kind of in etching gas flow or the etching power.
Preferably, described second dielectric layer utilizes spin coating method to form.
Compared with prior art, the present invention has the following advantages:
The formation method of through hole of the present invention and dual-damascene structure, the thickness that deposits unsettled dielectric layer is detected, and the process conditions of via etch have been adjusted according to this testing result, avoid the not appearance of foot phenomenon of over etching or etching, improved the formation quality of through hole or dual-damascene structure.
The formation method of through hole of the present invention and dual-damascene structure has adopted detection and the method for adjustment of sheet to sheet, has further improved the control that through hole is formed technology, has improved the formation quality of through hole or dual-damascene structure.
Description of drawings
Fig. 1 is the device profile map behind the formation etching stop layer in the existing through hole formation method;
Fig. 2 is the device profile map behind formation first dielectric layer in the existing through hole formation method;
Fig. 3 is for forming the device profile map behind the through hole in the existing through hole formation method in the ideal case;
Fig. 4 is the device profile map after forming through hole under the over etching situation in the existing through hole formation method;
Fig. 5 is the device profile map after forming through hole under the situation of etching deficiency in the existing through hole formation method;
Fig. 6 is the flow chart of the through hole formation method of first embodiment of the invention;
Fig. 7 is the device profile map behind the formation etching stop layer in the first embodiment of the invention;
Fig. 8 is the device profile map behind the formation dielectric layer in the first embodiment of the invention;
Fig. 9 is the etching depth of first embodiment of the invention medium layer and the graph of a relation between the etch period;
Figure 10 is the device profile map behind the formation via hole image in the first embodiment of the invention;
Figure 11 is the device profile map behind the formation through hole in the first embodiment of the invention;
Figure 12 is the flow chart of the dual-damascene structure formation method of second embodiment of the invention;
Figure 13 is the device profile map behind the formation etching stop layer in the second embodiment of the invention;
Figure 14 is the device profile map behind formation first dielectric layer in the second embodiment of the invention;
Figure 15 is the device profile map behind the formation via hole image in the second embodiment of the invention;
Figure 16 is the device profile map behind the formation through hole in the second embodiment of the invention;
Figure 17 is the device profile map behind formation second dielectric layer in the second embodiment of the invention;
Figure 18 is for illustrating the device profile map after the formation groove figure in the second embodiment of the invention;
Figure 19 is for illustrating the device profile map behind the formation groove in the second embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely used in the every field; and can utilize many suitable material; be to be illustrated below by specific embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Along with the develop rapidly of integrated circuit, semiconductor fabrication process to be had higher requirement, some new materials, new technology are also arisen at the historic moment.
After entering the following technology of 65nm, for satisfying the requirement of conduction fast, traditional utilizes silica material inapplicable as the method for interlayer dielectric layer, the lower Low-K value dielectric material of dielectric constant occurred.As, the Coral material of the black diamond of Applied Materials (BD, Black Diamond) material, Novellus company, and utilize spin coating process to make, Dow Corning Corporation Silk dielectric materials etc.
The appearance of new material has improved the performance of integrated circuit, yet, because its technology is still immature, in actual production, still can exist the not good problem of its manufacture craft control, as its batch with criticize between, bigger fluctuation can appear in deposit thickness between sheet and the sheet, this has brought problem to subsequent technique, as be prone to the phenomenon of over etching or etching deficiency in the making of through hole.
For this reason, the present invention proposes the formation method of new through hole and dual-damascene structure.
First embodiment:
Present embodiment has been introduced the method that forms through hole in the BD dielectric layer of low k value.Fig. 6 is the flow chart of the through hole formation method of first embodiment of the invention, and Fig. 7 to Figure 11 is elaborated to the first embodiment of the present invention below in conjunction with Fig. 6 to Figure 11 for the schematic diagram of explanation first embodiment of the invention.
Step 601: substrate is provided.
Substrate in the present embodiment can be for forming the substrate of metal oxide semiconductor transistor, also can be for forming the substrate of underlying metal connecting line construction.
Step 602: on described substrate, form etching stop layer.
Fig. 7 is the device profile map behind the formation etching stop layer in the first embodiment of the invention, as shown in Figure 7, has formed etching stop layer 702 on substrate 701.
In the present embodiment, this etching stop layer 702 is the nitrogenous silicon carbide layers that utilize PECVD deposition to form, and the etch rate of the dielectric layer of growing thereon in its etch rate and back is compared low, can stop in this layer when guaranteeing via etch.
Used reacting gas is ammonia and methyl-monosilane class gas when forming etching stop layer 702 in the present embodiment, and wherein, methyl-monosilane class gas can be methyl-monosilane (Si (CH
3) H
3), dimethylsilane (Si (CH
3)
2H
2), trimethyl silane (Si (CH
3)
3H), tetramethylsilane (Si (CH
3)
4) in waiting any.
The consideration of need trading off of the thickness of this etching stop layer 702 promptly can not thin excessively (to prevent over etching, guaranteeing that etching stopping is in this layer), can not blocked up (easy damaged substrate when remove the back), its thickness can be arranged on 300 to 500 usually
Between, as be 400
Step 603: on described etching stop layer, form dielectric layer.
Fig. 8 is the device profile map behind the formation dielectric layer in the first embodiment of the invention, as shown in Figure 8, has formed dielectric layer 703 on etching stop layer 702.
In the present embodiment, this dielectric layer 703 is the BD dielectric layer that utilizes the low k value of chemical gaseous phase depositing process formation, and its thickness can be arranged on 3500 to 5000 usually
Between, as be 4000
Because the depositing operation of dielectric material that should low k value is still not really ripe, to its control ability deficiency of growing state, in the actual production, depositing the film thickness that obtains can fluctuate, can be not identical between sheet and sheet.
At this moment; though the protection (its thickness and protective capability are limited) of etching stop layer 702 is arranged; if but the thickness fluctuation of dielectric layer 703 is excessive; especially for the less small size through hole of process window; still adopt identical etching condition when etching forms through hole in the back, still occur the phenomenon of over etching shown in prior figures 4 and Fig. 5 (dielectric layer 703 is thinner) or etching deficiency (dielectric layer 703 is thicker) possibly.
For this reason, present embodiment has added the step that the thickness to dielectric layer 703 detects after this step.
Step 604: the thickness that detects described dielectric layer.
In the present embodiment, after deposition forms dielectric layer 703, utilize the thickness tester that its actual growth thickness is detected.Particularly, can utilize Nano thickness tester, ellipsometer etc.
For improving the accuracy that detects, the detection of this step can be carried out each sheet substrate, and correspondingly, the process conditions that etching technics is adjusted in the back also are to carry out at each sheet substrate.
Step 605: the process conditions of determining etching technics subsequently according to the thickness of described dielectric layer.
Fig. 9 is the etching depth of first embodiment of the invention medium layer and the graph of a relation between the etch period, what wherein abscissa was represented is etch period, what ordinate was represented is etching depth, shown in data fitting curve 901 among Fig. 9, because between the etching depth of the BD dielectric layer in the present embodiment and the etch period is linear relationship, utilize this curve 901 to adjust etching depth by changing etch period easily.
As, the thickness of setting the BD dielectric layer is 4000
, be 3800 but actual detected obtains its thickness
, then can etch period be shortened about 1.5 seconds, to prevent the phenomenon of over etching by the curve among Fig. 9 901.
For another example, the thickness of setting BD dielectric layer is 4000
, be 4200 but actual detected obtains its thickness
, then can be by the curve among Fig. 9 901 with etch period lengthening about 1 second, to prevent the phenomenon of etching deficiency.
Step 606: on described dielectric layer, form via hole image.
Figure 10 is the device profile map behind the formation via hole image in the first embodiment of the invention, as shown in figure 10, utilizes photoresist to define via hole image 704 on dielectric layer 703.
The execution sequence of noting this step and step 605 can exchange.
Step 607: according to described process conditions described dielectric layer is carried out etching, to form through hole.
Figure 11 is the device profile map behind the formation through hole in the first embodiment of the invention, as shown in figure 11, has formed through hole 705 (having removed the photoresist of remained on surface in the device profile map shown in the figure) after this step etching in dielectric layer 703.
The through hole formation method of present embodiment, thickness to the unsettled dielectric layer 703 of growth thickness has carried out prior detection, and etch technological condition is adjusted according to this testing result, thereby guaranteed that this step etching can stop in the etching stop layer 702, the over etching that occurs among Fig. 4 or Fig. 5 or the phenomenon of etching deficiency can not occur.
The through hole formation method of present embodiment utilizes the method for above-mentioned feedback information (APC, Auto PowerControl) to improve the formation quality of through hole, has improved consistency, stability and the reliability of circuit electrical property.
Dielectric layer in the present embodiment is the BD material layer, in other embodiments of the invention, also can be the Coral material of Novellus company, Dow Corning Corporation Silk dielectric materials etc.
Utilize the change of etch period to adjust etching depth in the present embodiment, in other embodiments of the invention, also can adjust etching depth, the air pressure during as etching in the operating room by other parameter that changes etching technics, the flow of etching gas, etching power etc.The extension of this application is easy to understand and realization for those of ordinary skills, does not repeat them here.
Second embodiment:
Present embodiment has been introduced the method for the dual-damascene structure that utilizes the formation of low k dielectric layer.Figure 12 is the flow chart of the dual-damascene structure formation method of second embodiment of the invention, and Figure 13 to Figure 19 is elaborated to the second embodiment of the present invention below in conjunction with Figure 12 to Figure 19 for the device profile map of explanation second embodiment of the invention.
Step 1201: substrate is provided.
Substrate in the present embodiment can be for forming the substrate of metal oxide semiconductor transistor, also can be for forming the substrate of underlying metal connecting line construction.
Step 1202: on described substrate, form etching stop layer.
Figure 13 is the device profile map behind the formation etching stop layer in the second embodiment of the invention, as shown in figure 13, has formed etching stop layer 1302 on substrate 1301.
In the present embodiment, this etching stop layer 1302 is the nitrogenous silicon carbide layers that utilize PECVD deposition to form, and the etch rate of the dielectric layer of growing thereon in its etch rate and back is compared low, can stop in this layer when guaranteeing via etch.
The consideration of need trading off of the thickness of this etching stop layer 1302 promptly can not thin excessively (to prevent over etching, guaranteeing that etching stopping is in this layer), can not blocked up (easy damaged substrate when remove the back), its thickness can be arranged on 300 to 500 usually
Between, as be 400
Step 1203: on described etching stop layer, form first dielectric layer.
Figure 14 is the device profile map behind formation first dielectric layer in the second embodiment of the invention, as shown in figure 14, has formed first dielectric layer 1303 on etching stop layer 1302.
In the present embodiment, this first dielectric layer 1303 is the BD dielectric layer that utilizes the low k value of chemical gaseous phase depositing process formation, and its thickness is arranged on 3500 to 5000
Between, as be 4000
Though the protection of etching stop layer 1302 is arranged; if but the thickness fluctuation of first dielectric layer 1303 is excessive; still adopt identical etching condition when etching forms through hole in the back, still occur the phenomenon of over etching shown in prior figures 4 and Fig. 5 (dielectric layer 1303 is thinner) or etching deficiency (dielectric layer 1303 is thicker) possibly.
For this reason, present embodiment has added the step that the thickness to first dielectric layer 1303 detects after this step.
Step 1204: the thickness that detects described first dielectric layer.
In the present embodiment, after deposition forms first dielectric layer 1303, utilize the thickness tester that its actual growth thickness is detected.Particularly, can utilize Nano thickness tester, ellipsometer etc.
Step 1205: the process conditions of determining etching technics subsequently according to the thickness of described first dielectric layer.
As shown in Figure 9, owing to be linear relationship between the etching depth of the BD dielectric layer in the present embodiment and the etch period, can utilize the curve 901 among Fig. 9 to adjust etching depth by changing etch period easily.
As, the thickness of setting the BD dielectric layer is 4000
, be 3800 but actual detected obtains its thickness
, then can etch period be shortened about 1.5 seconds, to prevent the phenomenon of over etching by the curve among Fig. 9 901.
For another example, the thickness of setting BD dielectric layer is 4000
, be 4200 but actual detected obtains its thickness
, then can be by the curve among Fig. 9 901 with etch period lengthening about 1 second, to prevent the phenomenon of etching deficiency.
Step 1206: on described first dielectric layer, form via hole image.
Figure 15 is the device profile map behind the formation via hole image in the second embodiment of the invention, as shown in figure 15, utilizes photoresist to define via hole image 1304 on dielectric layer 1303.
Step 1207: according to described process conditions described first dielectric layer is carried out etching, to form through hole.
Figure 16 is the device profile map behind the formation through hole in the second embodiment of the invention, as shown in figure 16, in first dielectric layer 1303, formed through hole 1305 (having removed the photoresist of first dielectric layer, 1303 remained on surface in the device profile map shown in the figure) after this step etching.
In the present embodiment, the thickness of the unsettled dielectric layer 1303 of growth thickness has been carried out prior detection, and etch technological condition has been adjusted, thereby guaranteed that this step etching can stop in the etching stop layer 1302 according to this testing result.
Step 1208: form second dielectric layer on described first dielectric layer and in the through hole.
Figure 17 is the device profile map behind formation second dielectric layer in the second embodiment of the invention, as shown in figure 17, has covered second dielectric layer 1306 on first dielectric layer 1303 and in the through hole 1305.
In the present embodiment, for filling vias 1305 preferably, can obtain comparatively smooth surface simultaneously, this second dielectric layer 1306 has adopted the DUO material layer that utilizes spin coating method to form.
Step 1209: on described second dielectric layer, form groove figure.
Figure 18 is for illustrating the device profile map after the formation groove figure in the second embodiment of the invention, and as shown in figure 18, this step normally utilizes photoetching technique to define the figure 1307 of groove on second dielectric layer 1306.
Step 1210: etching forms the groove that links to each other with at least one through hole.
Figure 19 is for illustrating the device profile map behind the formation groove in the second embodiment of the invention; as shown in figure 19; second dielectric layer 1306 and part first dielectric layer 1303 that utilize the dry etching technology etching not protected by photoresist form the groove 1308 link to each other with at least one through hole 1305 (device profile map shown in the figure removed second dielectric layer, 1306 surfaces residual photoresist).
The concrete formation method of this groove is as follows:
A, second dielectric layer 1306 and part first dielectric layer 1303 that utilize the dry etching technology etching not protected by photoresist;
C, remove second dielectric layer, 1306 surfaces residual photoresist, form the groove 1308 that links to each other with at least one through hole 1305.
Then, can utilize etching stop layer 1302 erosion removals of the method for wet etching or dry etching, again through hole 1305 and groove 1308 be carried out metalized, form dual-damascene structure through hole 1305 bottoms.
The dual-damascene structure formation method of present embodiment, thickness to unsettled first dielectric layer 1303 of growth thickness has carried out prior detection, and comply with this testing result etch technological condition is adjusted, thereby guaranteed when etching through hole, to stop in the etching stop layer 1302, the over etching that occurs among Fig. 4 or Fig. 5 or the phenomenon of etching deficiency can not appear, improve the formation quality of through hole in the dual-damascene structure, also improved the total quality of dual-damascene structure.
Dielectric layer in the present embodiment is the BD material layer, and in other embodiments of the invention, it also can be the Coral material of Novellus company, Dow Corning Corporation Silk dielectric materials etc.
Utilize the change of etch period to adjust the etching depth of through hole in the present embodiment, in other embodiments of the invention, also can adjust etching depth, the air pressure during as etching in the operating room by other parameter that changes etching technics, the flow of etching gas, etching power etc.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (17)
1. the formation method of a through hole is characterized in that, comprises step:
Substrate is provided;
On described substrate, form etching stop layer;
On described etching stop layer, form dielectric layer;
Detect the thickness of described dielectric layer;
Determine the process conditions of etching technics subsequently according to the thickness of described dielectric layer;
On described dielectric layer, form via hole image;
According to described process conditions described dielectric layer is carried out etching, make etching stopping in described etching stop layer, to form through hole, described etch technological condition comprises according to the linear relationship between etching depth and the etch period, adjusts etching depth by changing etch period.
2. formation method as claimed in claim 1 is characterized in that: described dielectric layer is the dielectric layer of low k value.
3. formation method as claimed in claim 1 or 2 is characterized in that: described dielectric layer is the black diamond material layer.
4. formation method as claimed in claim 1 or 2 is characterized in that: the thickness of described dielectric layer is 3500 to 5000
Between.
5. formation method as claimed in claim 1 or 2 is characterized in that: described dielectric layer utilizes chemical gaseous phase depositing process to form.
6. formation method as claimed in claim 1 or 2 is characterized in that: described process conditions comprise etch period.
7. formation method as claimed in claim 1 or 2 is characterized in that: described process conditions comprise operating room's air pressure at least, a kind of in etching gas flow or the etching power.
8. formation method as claimed in claim 1 or 2 is characterized in that: described etching stop layer is nitrogenous silicon carbide layer.
9. the formation method of a dual-damascene structure is characterized in that, comprises step:
Substrate is provided;
On described substrate, form etching stop layer;
On described etching stop layer, form first dielectric layer;
Detect the thickness of described first dielectric layer;
Determine the process conditions of etching technics subsequently according to the thickness of described first dielectric layer;
On described first dielectric layer, form via hole image;
According to described process conditions described first dielectric layer is carried out etching, make etching stopping in described etching stop layer, to form through hole, described etch technological condition comprises according to the linear relationship between etching depth and the etch period, adjusts etching depth by changing etch period;
Form second dielectric layer on described first dielectric layer and in the through hole;
On described second dielectric layer, form groove figure;
Etching forms the groove that links to each other with at least one through hole.
10. formation method as claimed in claim 9 is characterized in that: described first dielectric layer is the dielectric layer of low k value.
11. as claim 9 or 10 described formation methods, it is characterized in that: described first dielectric layer is the black diamond material layer.
12. as claim 9 or 10 described formation methods, it is characterized in that: the thickness of described first dielectric layer is 3500 to 5000
Between.
13. as claim 9 or 10 described formation methods, it is characterized in that: described first dielectric layer utilizes chemical gaseous phase depositing process to form.
14. as claim 9 or 10 described formation methods, it is characterized in that: described etching stop layer is nitrogenous silicon carbide layer.
15. as claim 9 or 10 described formation methods, it is characterized in that: described process conditions comprise etch period.
16. as claim 9 or 10 described formation methods, it is characterized in that: described process conditions comprise operating room's air pressure at least, a kind of in etching gas flow or the etching power.
17. as claim 9 or 10 described formation methods, it is characterized in that: described second dielectric layer utilizes spin coating method to form.
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| CN1258097A (en) * | 1998-12-21 | 2000-06-28 | 日本电气株式会社 | Method for forming double inserted wiring |
| CN1711632A (en) * | 2002-11-12 | 2005-12-21 | 应用材料股份有限公司 | Method and apparatus employing integrated metrology for improved dielectric etch efficiency |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1258097A (en) * | 1998-12-21 | 2000-06-28 | 日本电气株式会社 | Method for forming double inserted wiring |
| CN1711632A (en) * | 2002-11-12 | 2005-12-21 | 应用材料股份有限公司 | Method and apparatus employing integrated metrology for improved dielectric etch efficiency |
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