GB2330963B - Apparatus and method for selectively controlling clocking and resetting of a network interface - Google Patents

Apparatus and method for selectively controlling clocking and resetting of a network interface

Info

Publication number
GB2330963B
GB2330963B GB9810416A GB9810416A GB2330963B GB 2330963 B GB2330963 B GB 2330963B GB 9810416 A GB9810416 A GB 9810416A GB 9810416 A GB9810416 A GB 9810416A GB 2330963 B GB2330963 B GB 2330963B
Authority
GB
United Kingdom
Prior art keywords
clock
network interface
network
power
bypass circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9810416A
Other languages
English (en)
Other versions
GB2330963A (en
GB9810416D0 (en
Inventor
Jeffrey Roy Dwork
Ching Yu
Robert Williams
Rajat Roy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB9810416D0 publication Critical patent/GB9810416D0/en
Publication of GB2330963A publication Critical patent/GB2330963A/en
Application granted granted Critical
Publication of GB2330963B publication Critical patent/GB2330963B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Power Sources (AREA)
GB9810416A 1997-10-30 1998-05-14 Apparatus and method for selectively controlling clocking and resetting of a network interface Expired - Fee Related GB2330963B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/961,190 US5938728A (en) 1997-10-30 1997-10-30 Apparatus and method for selectively controlling clocking and resetting of a network interface

Publications (3)

Publication Number Publication Date
GB9810416D0 GB9810416D0 (en) 1998-07-15
GB2330963A GB2330963A (en) 1999-05-05
GB2330963B true GB2330963B (en) 2001-01-24

Family

ID=25504180

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9810416A Expired - Fee Related GB2330963B (en) 1997-10-30 1998-05-14 Apparatus and method for selectively controlling clocking and resetting of a network interface

Country Status (3)

Country Link
US (1) US5938728A (enExample)
JP (1) JP4129314B2 (enExample)
GB (1) GB2330963B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185630B1 (en) * 1997-02-14 2001-02-06 Advanced Micro Devices, Inc. Device initializing system with programmable array logic configured to cause non-volatile memory to output address and data information to the device in a prescribed sequence
US6662234B2 (en) * 1998-03-26 2003-12-09 National Semiconductor Corporation Transmitting data from a host computer in a reduced power state by an isolation block that disconnects the media access control layer from the physical layer
US6697954B1 (en) * 1999-01-08 2004-02-24 Compaq Computer Corporation Method/apparatus for preserving state of an event during powerup reset sequence based on state of an event signal immediately prior to the reset
US6311284B1 (en) * 1999-03-15 2001-10-30 Advanced Micro Devices, Inc. Using an independent clock to coordinate access to registers by a peripheral device and a host system
US7213061B1 (en) 1999-04-29 2007-05-01 Amx Llc Internet control system and method
US6636912B2 (en) * 1999-10-07 2003-10-21 Intel Corporation Method and apparatus for mode selection in a computer system
US6718417B1 (en) * 1999-12-23 2004-04-06 Intel Corporation Physical layer and data link interface with flexible bus width
US6795881B1 (en) 1999-12-23 2004-09-21 Intel Corporation Physical layer and data link interface with ethernet pre-negotiation
US6782001B1 (en) 1999-12-23 2004-08-24 Intel Corporation Physical layer and data link interface with reset/sync sharing
US7257079B1 (en) 1999-12-23 2007-08-14 Intel Corporation Physical layer and data link interface with adaptive speed
JPWO2001048615A1 (ja) * 1999-12-27 2004-01-08 富士ゼロックス株式会社 プリンタ装置及び制御方法並びにプリンタ制御プログラムを格納したコンピュータ可読の記憶媒体
US20030046457A1 (en) * 2000-10-02 2003-03-06 Shakuntala Anjanaiah Apparatus and method for an interface unit for data transfer between processing units in the asynchronous transfer mode
US6665795B1 (en) * 2000-10-06 2003-12-16 Intel Corporation Resetting a programmable processor
US20040059905A1 (en) * 2002-09-19 2004-03-25 Soulier George R. Method and apparatus for short-power cycle detection
US20040107375A1 (en) * 2002-12-02 2004-06-03 Edward Anglada System and method for switching clock sources
US8881233B2 (en) * 2005-05-23 2014-11-04 Microsoft Corporation Resource management via periodic distributed time
US9063739B2 (en) * 2005-09-07 2015-06-23 Open Invention Network, Llc Method and computer program for device configuration
US7624244B2 (en) * 2007-06-22 2009-11-24 International Business Machines Corporation System for providing a slow command decode over an untrained high-speed interface
US7979616B2 (en) * 2007-06-22 2011-07-12 International Business Machines Corporation System and method for providing a configurable command sequence for a memory interface device
US9547609B2 (en) * 2013-10-25 2017-01-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Data interface for point-to-point communications between devices
CN114201440B (zh) * 2021-12-14 2024-06-07 上海微阱电子科技有限公司 时钟检测方法、电路、串口通信系统、介质和设备
CN119847617B (zh) * 2024-12-31 2025-10-28 研祥智慧物联科技有限公司 网口设备的控制方法、控制装置及网口设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
US5513358A (en) * 1994-02-04 1996-04-30 Motorola, Inc. Method and apparatus for power-up state initialization in a data processing system
WO1996013106A1 (en) * 1994-10-20 1996-05-02 Advanced Micro Devices, Inc. System and method for remote wake-up

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970010634B1 (ko) * 1994-10-25 1997-06-28 삼성전자 주식회사 네트워크 하이버네이션 시스템
KR0156802B1 (ko) * 1995-11-07 1998-11-16 김광호 네트워크 하이버네이션 시스템 및 그 제어 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
US5513358A (en) * 1994-02-04 1996-04-30 Motorola, Inc. Method and apparatus for power-up state initialization in a data processing system
WO1996013106A1 (en) * 1994-10-20 1996-05-02 Advanced Micro Devices, Inc. System and method for remote wake-up

Also Published As

Publication number Publication date
JPH11175198A (ja) 1999-07-02
GB2330963A (en) 1999-05-05
JP4129314B2 (ja) 2008-08-06
US5938728A (en) 1999-08-17
GB9810416D0 (en) 1998-07-15

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20110514