JP4129314B2 - ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法 - Google Patents

ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法 Download PDF

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Publication number
JP4129314B2
JP4129314B2 JP14774398A JP14774398A JP4129314B2 JP 4129314 B2 JP4129314 B2 JP 4129314B2 JP 14774398 A JP14774398 A JP 14774398A JP 14774398 A JP14774398 A JP 14774398A JP 4129314 B2 JP4129314 B2 JP 4129314B2
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Japan
Prior art keywords
clock
network
network interface
power
reset signal
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JP14774398A
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Japanese (ja)
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JPH11175198A (ja
JPH11175198A5 (enExample
Inventor
ジェフリー・ロイ・ドゥウォーク
チン・ユ
ロバート・ウイリアムズ
ラジャット・ロイ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Power Sources (AREA)
JP14774398A 1997-10-30 1998-05-28 ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法 Expired - Fee Related JP4129314B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/961,190 US5938728A (en) 1997-10-30 1997-10-30 Apparatus and method for selectively controlling clocking and resetting of a network interface
US08/961190 1997-10-30

Publications (3)

Publication Number Publication Date
JPH11175198A JPH11175198A (ja) 1999-07-02
JPH11175198A5 JPH11175198A5 (enExample) 2005-09-29
JP4129314B2 true JP4129314B2 (ja) 2008-08-06

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JP14774398A Expired - Fee Related JP4129314B2 (ja) 1997-10-30 1998-05-28 ネットワークインタフェース、ネットワークインタフェースを初期化するための装置およびネットワークインタフェース内に構成情報をロードする方法

Country Status (3)

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US (1) US5938728A (enExample)
JP (1) JP4129314B2 (enExample)
GB (1) GB2330963B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185630B1 (en) * 1997-02-14 2001-02-06 Advanced Micro Devices, Inc. Device initializing system with programmable array logic configured to cause non-volatile memory to output address and data information to the device in a prescribed sequence
US6662234B2 (en) * 1998-03-26 2003-12-09 National Semiconductor Corporation Transmitting data from a host computer in a reduced power state by an isolation block that disconnects the media access control layer from the physical layer
US6697954B1 (en) * 1999-01-08 2004-02-24 Compaq Computer Corporation Method/apparatus for preserving state of an event during powerup reset sequence based on state of an event signal immediately prior to the reset
US6311284B1 (en) * 1999-03-15 2001-10-30 Advanced Micro Devices, Inc. Using an independent clock to coordinate access to registers by a peripheral device and a host system
US7213061B1 (en) 1999-04-29 2007-05-01 Amx Llc Internet control system and method
US6636912B2 (en) * 1999-10-07 2003-10-21 Intel Corporation Method and apparatus for mode selection in a computer system
US6718417B1 (en) * 1999-12-23 2004-04-06 Intel Corporation Physical layer and data link interface with flexible bus width
US6795881B1 (en) 1999-12-23 2004-09-21 Intel Corporation Physical layer and data link interface with ethernet pre-negotiation
US6782001B1 (en) 1999-12-23 2004-08-24 Intel Corporation Physical layer and data link interface with reset/sync sharing
US7257079B1 (en) 1999-12-23 2007-08-14 Intel Corporation Physical layer and data link interface with adaptive speed
JPWO2001048615A1 (ja) * 1999-12-27 2004-01-08 富士ゼロックス株式会社 プリンタ装置及び制御方法並びにプリンタ制御プログラムを格納したコンピュータ可読の記憶媒体
US20030046457A1 (en) * 2000-10-02 2003-03-06 Shakuntala Anjanaiah Apparatus and method for an interface unit for data transfer between processing units in the asynchronous transfer mode
US6665795B1 (en) * 2000-10-06 2003-12-16 Intel Corporation Resetting a programmable processor
US20040059905A1 (en) * 2002-09-19 2004-03-25 Soulier George R. Method and apparatus for short-power cycle detection
US20040107375A1 (en) * 2002-12-02 2004-06-03 Edward Anglada System and method for switching clock sources
US8881233B2 (en) * 2005-05-23 2014-11-04 Microsoft Corporation Resource management via periodic distributed time
US9063739B2 (en) * 2005-09-07 2015-06-23 Open Invention Network, Llc Method and computer program for device configuration
US7624244B2 (en) * 2007-06-22 2009-11-24 International Business Machines Corporation System for providing a slow command decode over an untrained high-speed interface
US7979616B2 (en) * 2007-06-22 2011-07-12 International Business Machines Corporation System and method for providing a configurable command sequence for a memory interface device
US9547609B2 (en) * 2013-10-25 2017-01-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Data interface for point-to-point communications between devices
CN114201440B (zh) * 2021-12-14 2024-06-07 上海微阱电子科技有限公司 时钟检测方法、电路、串口通信系统、介质和设备
CN119847617B (zh) * 2024-12-31 2025-10-28 研祥智慧物联科技有限公司 网口设备的控制方法、控制装置及网口设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513358A (en) * 1994-02-04 1996-04-30 Motorola, Inc. Method and apparatus for power-up state initialization in a data processing system
US5446403A (en) * 1994-02-04 1995-08-29 Zenith Data Systems Corporation Power on reset signal circuit with clock inhibit and delayed reset
KR100378537B1 (ko) * 1994-10-20 2003-07-12 아드밴스트 마이크로 디이바이시스 인코포레이티드 원격웨이크-업시스템및방법
KR970010634B1 (ko) * 1994-10-25 1997-06-28 삼성전자 주식회사 네트워크 하이버네이션 시스템
KR0156802B1 (ko) * 1995-11-07 1998-11-16 김광호 네트워크 하이버네이션 시스템 및 그 제어 방법

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Publication number Publication date
JPH11175198A (ja) 1999-07-02
GB2330963A (en) 1999-05-05
GB2330963B (en) 2001-01-24
US5938728A (en) 1999-08-17
GB9810416D0 (en) 1998-07-15

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