GB2321123A - Circuit for erasing a memory and method thereof - Google Patents

Abstract

A circuit for erasing a RAM 6 where the circuit comprises a microcontroller or processor 2 and a data bus 8 connected to the processor 2 and the memory unit 6. There is also provided a power switch 34 to selectively control a supply voltage to the memory unit 6. The microcontroller 2 is arranged to selectively generate a substantially low voltage at the data bus 8 so as to deprive the memory unit 6 of power.

Description

CIRCUIT FOR ERASING A MEMORY AND A METHOD THEREOF Field of the Invention The present invention relates to a method of erasing a memory, for example, of the type used in modems. The invention also relates to a circuit for erasing a memory.

Background of the Invention In some applications, it is desirable to be able to rapidly erase a Random Access Memory (RAM) of an electronic device, for example, to protect data stored in encryption or secure data storage units.

A known technique to erase the RAM comprises selectively connecting the RAM's power supply line to ground, thereby depriving the RAM of power.

However, current can sometimes feed into the RAM in the form of logical HIGH signals on the address bus, the data bus or the control lines, thereby providing enough internal voltage to maintain the data in the RAM.

The use of buffers has been proposed to isolate the data and address buses as well as the control lines. However, the use of buffers increases the current consumption of the circuit, the size of a circuit board to support the components of the circuit and thus the overall cost of the circuit.

Additionally, the use of buffers increases the access time of data from the RAM and slows the electronic device.

It is therefore an object of the present invention to obviate or mitigate the above disadvantages associated with a circuit to erase a memory.

Summarv of the Invention According to the present invention, there is provided a circuit for erasing a memory unit, the circuit comprising a processor, a first bus connected to the processor and the memory unit, switching means to selectively control a supply voltage to the memory unit, wherein the processor is arranged to selectively generate a substantially low voltage on the first bus so as to deprive the memory unit of power.

Preferably, the circuit further comprises a second bus connected to the processor and the memory unit and a programmable Read Only Memory connected to the second bus and arranged to generate a substantially low voltage on the second bus so as to deprive the memory unit of power.

Preferably, the circuit further comprises means to generate a substantially low voltage at a write terminal of the memory unit.

The circuit may further comprise means to generate a substantially low voltage at a read terminal of the memory unit.

Conveniently, the circuit further comprises means to generate a substantially low voltage at a clock signal terminal of the memory unit.

Preferably, a timer is provided to cause the processor to generate the substantially low voltage for a predetermined period of time sufficient to erase the memory unit. Very preferably, the timer is an R-C circuit. Most preferably, the predetermined period of time is at least one clock cycle.

The processor may be arranged to manually erase the memory unit once the predetermined period has expired.

The processor may be arranged to erase the programmable Read Only Memory once the predetermined period has expired.

Preferably, the first bus is an address bus and the second bus is a data bus.

The circuit may be provided in a modem. Alternatively, the circuit may be provided in a power saving device, for example to allow a bank of memory to be powered down to conserve power.

According to the present invention, there is also provided a method of erasing a memory unit in a circuit including a processor and a first bus connected to the processor and the memory unit, the method comprising the steps of halting a supply of current to the memory unit and generating a substantially low voltage by the processor on the first bus.

Preferably, a second bus is connected to the processor and the memory unit and a programmable Read Only Memory connected to the second bus, the method further comprising the step of generating a substantially low voltage at the second bus by the programmable Read Only Memory so as to deprive the memory unit of power.

Preferably, the method further comprises the step of generating a substantially low voltage at a write terminal of the memory unit.

The method may further comprise the step of generating a substantially low voltage at a read terminal of the memory unit.

Conveniently, the method further comprises the step of generating a substantially low voltage at a clock signal terminal of the memory unit.

Preferably, the method further comprises the step of generating the substantially low voltage for a predetermined period of time. More preferably, the predetermined period of time is at least one clock cycle.

The method may further comprise the step of manually erasing the memory unit once the predetermined period has expired.

The method may further comprise the step of erasing the programmable Read Only Memory once the predetermined period has expired.

Preferably, the first bus is an address bus and the second bus is a data bus.

It is thus possible to provide a circuit for erasing a memory which requires less circuit board space, has reduced current consumption and therefore lower manufacturing costs.

Brief Description of the Drawings The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: FIG. 1 is a schematic diagram of a circuit constituting an embodiment of the present invention; FIG. 2 and FIG. 3 are flow diagrams relating to a method for use with the circuit of FIG. 1, and FIG. 4 is a timing diagram corresponding to the circuit of FIG. 1.

Description of a Preferred Embodiment The circuit of FIG. 1 comprises a battery backup power supply (not shown) for supplying power to tamper detection circuitry (not shown), for example, any circuitry known in the art for detecting tampering with electronic circuits, such as a temperature change detector or a break-in detector. A voltage detector (not shown) is provided to detect changes in output voltages from the tamper detection circuitry. A microcontroller 2 is also provided and has a plurality of data bus terminals 3, a plurality of address bus terminals 5, a WRITE terminal 12, a READ terminal 22, a ROM chip select (ROMCS) terminal 28, a RAM chip select (RAMCS) terminal 38, an external WAIT terminal 56, a RESET terminal 45, an ERASED INDICATOR terminal 50 and a CLEAR ERASED INDICATOR terminal 48. An optional ALARM TRIGGERED terminal 58 can also be provided for diagnostic purposes. The microcontroller 2 is connected to a programmable Read Only Memory (PROM) 4 and a Random Access Memory (RAM) 6 as follows.

The plurality of data bus terminals 3 and the plurality of address bus terminals 5 are respectively connected to a first corresponding plurality of data bus terminals 7 and a first corresponding plurality of address bus terminals 9 of the PROM 4, and a second corresponding plurality of data bus terminals 11 and a second corresponding plurality of address bus terminals 13 of the RAM 6. The above connections form a data bus 8 and an address bus 10.

The WRITE terminal 12, the READ terminal 22 and the ROMCS terminal 28 of the microcontroller 2 are respectively connected to a corresponding WRITE terminal 14, a corresponding READ terminal 24 and a chip select terminal 30 of the PROM 4. The READ terminal 22 is also connected to a corresponding READ terminal 26 of the RAM 6. The WRITE terminal 12 is connected to an inverting input terminal of a first NOR gate 16, the noninverting input terminal of the first NOR gate 16 being connected to a noninverting output terminal of a first flip-flop 18 and an input terminal of a first pulse generator 44. The first pulse generator 44 is triggered by a positive-going edge of an input signal and has an output terminal connected to the RESET terminal 45. The output terminal of the first NOR gate 16 is connected to a corresponding WRITE terminal 20 of the RAM 6.

The ROMCS terminal 28 is also connected to an inverting input terminal of an AND gate 32, the non-inverting input terminal of the AND gate 32 being connected to the non-inverting input terminal of the first NOR gate 16, a non-inverting input terminal of a second NOR gate 40, and an input terminal of a power switch 34. An output terminal of the power switch 34 is connected to a positive voltage supply terminal 36 of the RAM 6. The power switch 34 is also connected to a positive voltage source (not shown). In an alternative embodiment, the power switch 34 can be replaced with a transistor and a current limiting resistor (both not shown) to provide a negative voltage to the RAM 6. The advantage of using a negative voltage is that the RAM 6 will be completely erased in less time than if a substantially low voltage signal, such as a 0 volts signal were used to erase the RAM 6.

Additionally, any other circuit known in the art capable of generating a negative voltage can be used.

The RAMCS terminal 38 is connected to an inverting input terminal of the second NOR gate 40, the output terminal of the second NOR gate 40 being connected to a chip select terminal 27 of the RAM 6.

An output terminal of the AND gate 32 is connected to an input terminal of a second pulse generator 55 which can be an R-C circuit. The second pulse generator 55 is triggered by a positive-going edge and has an output terminal connected to a clocking input terminal of a second flip-flop 46 and the external WAIT terminal 56. The second flipflop 46 has a DATA input terminal connected to a positive voltage supply (not shown), and a RESET terminal connected to the CLEAR ERASED INDICATOR terminal 48. The second flipflop 46 is triggered by a positive-going edge of a clocking signal and has a non-inverting output terminal connected to the ERASED INDICATOR terminal 50 and a RESET terminal of the first flip-flop 18.

The first flip-flop 18 has a DATA input terminal connected to a positive voltage supply (not shown) and a clocking input terminal connected to the voltage detector (not shown). The first flip-flop 18 is triggered by a positivegoing edge of a clocking input signal. If an alternative, level triggered, regime is employed, the first or second flip-flops 18, 46 can be replaced by an AND gate having an inverted input terminal.

If the optional ALARM TRIGGERED terminal 58 is used, the clocking input terminal of the first flipflop 18 can be connected thereto.

In operation (FIG. 2 and FIG. 4), a transition from a logical LOW signal to a logical HIGH signal 402 is awaited at the clocking input terminal of the first flip-flop 18 (step 202). When the transition is detected (step 204), a positive edged logical HIGH signal 404 is output at the non-inverting output terminal of the first flip-flop 18, which triggers the first pulse generator 44 to generate a 0.1 ms positive edged pulse 406 at the RESET terminal 45 (step 206). At the same time as the first pulse generator 44 is triggered, the logical HIGH output signal from the first flip-flop 18 also actuates the power switch 34 (step 206) so as to remove the supply voltage Vcc 408 to the positive voltage supply terminal 36.

In response to the 0.1 ms pulse 406, the microcontroller 2 resets itself and fetches a first op code from the PROM 4, which is 00 in hexadecimal, via the data and address buses 8, 10 by generating a plurality of logical LOW signals 414 on the address bus 10 corresponding to 0000 (step 210). In response, the PROM 4 generates a plurality of logical LOW signal 416 on the data bus 8 corresponding to 0000 (step 212). At the same time, corresponding logical LOW signals 410, 412 are generated at the READ and the ROMCS terminals 22, 28. The AND gate 32 then generates a logical HIGH output signal (not shown) in response to the logical HIGH output signal 404 from the non-inverting output terminal of the first flip-flop 18 and the logical LOW signal 412, the leading edge of the logical HIGH-going output signal from the AND gate 32 triggering the second pulse generator 55 to generate a logical LOW pulse 420 for at least one clock cycle, for example 0.1 s, (step 214) which is sent to the external WAIT terminal 56 to prevent the microcontroller 2 from proceeding beyond the execution of the first op code so as to ensure that the RAM 6 is deprived of power for a sufficiently long period of time in order to erase the RAM 6.

Additionally, the first NOR gate 16 generates a logical LOW output signal 422 (step 216) in response to a logical HIGH signal generated by the WRITE terminal 12 (which is inverted by the inverting input of the first NOR gate 16) and the logical HIGH output signal 404 from the first flip-flop 18, thereby holding the WRITE terminal 20 at logic LOW. The second NOR gate 40 also generates a logical LOW output signal 418 signal (step 218) in response to the logical HIGH output signal 404 from the first flip-flop 18 and a logical HIGH output signal from the RAMCS terminal 38 (which is inverted by the inverting input ofthe second NOR gate 40), thereby holding the chip select terminal 27 at logic LOW. The READ terminal 22 also outputs a logical LOW signal 424.

Thus, the terminals of the RAM 6 corresponding to the data and address buses 8, 10, the READ terminal 26, the WRITE terminal 20 and the chip select terminal 27 are held at logic LOW, thereby depriving the RAM 6 of power and causing any data held by the RAM 6 to be randomised or erased.

Referring to FIG. 3 and FIG. 4, additional fixnctionality (step 220) can also be provided as follows.

The logical LOW pulse 420 from the second pulse generator 55 is also fed to the clocking input terminal of the second flip-flop 46. The returning positive-going edge at the end of the logical LOW pulse 420 triggers the second flip-flop 46 to generate a logical HIGH output signal 426 which is fed to both the ERASED INDICATOR terminal 50 (step 302), to inform the microcontroller 2 that an erase cycle has taken place, and the RESET terminal of the first flip-flop 18, to reset the first flip-flop 18 (step 304).

After the first flip-flop 18 has been reset, a logical LOW signal is generated at the non-inverting output of the first flip-flop 18 once more.

Also, once the 0.1 ms pulse from the first pulse generator 44 has elapsed, a logical LOW signal is present at the RESET terminal 45 and the microcontroller 2 is allowed to function normally once more.

The microcontroller 2 then sends a logical HIGH signal via the CLEAR ERASED INDICATOR terminal 48 to reset the second flip-flop 46 (step 306) which, in response, generates a logical LOW output signal.

The microcontroller 2 can then take whatever subsequent action is appropriate in the circumstances, for example, the RAM 6 or the PROM 4 can be manually erased by the microcontroller 2 if an unauthorised attempt has been made to recover the contents of the RAM 6.

If desirable, the circuit can be arranged to advise an operator that, when applicable, the RAM 6 has been erased.

If it is undesirable for the circuit to continue functioning once the RAM 6 has been erased, the circuit can be arranged so that the circuit takes no further action or 'hangs', for example by remaining in a reset state. This can be achieved by removing the AND gate 32, the second pulse generator 55, the second flip-flop 46 and their respective connections, and connecting the noninverting output terminal of the first flip-flop 18 to the external WAIT terminal 56 via an inverter (not shown) so as to provide a permanent logical LOW signal at the external WAIT terminal 56, thereby ensuring that the microcontroller 2 remains in the reset state indefinitely.

It is also conceivable to fabricate the microcontroller 2 and at least one of the first flip-flop 18, the second flip-flop 46, the first pulse generator 44, the second pulse generator 55, the first NOR gate 16, the second NOR gate 40, the AND gate 32 and the power switch 34 as a single integrated circuit.

In another embodiment of the present invention, the PROM 4 can be removed and the capacity of the RAM 6 increased to store the code stored in the PROM 4. The first flip-flop 18 is then redundant and can be removed along with any respective connections to and from the first flip-flop 18.

Additionally, the output terminal of the second NOR gate 40 can be connected to the ROMCS terminal 28. Clearly, the connections to the PROM 4 are also no longer required. The additional firnctionality described above relating to the microcontroller 2 continuing to function normally after the circuit has been reset does not apply if the code for the circuit is held in the RAM 6 in this embodiment.

Although the invention has been described in the context of an edgetriggered system, it is not intended that the invention be limited to such a system. It is conceivable that other systems can be employed, such as a level triggered system.

Claims (25)

Claims

1. A circuit for erasing a memory unit, the circuit comprising a processor, a first bus connected to the processor and the memory unit, switching means to selectively control a supply voltage to the memory unit, wherein the processor is arranged to selectively generate a substantially low voltage on the first bus so as to deprive the memory unit of power.

2. A circuit as claimed in Claim 1, further comprising a second bus connected to the processor and the memory unit and a programmable Read Only Memory connected to the second bus and arranged to generate a substantially low voltage on the second bus so as to deprive the memory unit of power.

3. A circuit as claimed in any one of the preceding claims, further comprising means to generate a substantially low voltage at a write terminal of the memory unit.

4. A circuit as claimed in any one of the preceding claims, further comprising means to generate a substantially low voltage at a read terminal of the memory unit.

5. A circuit as claimed in any one of the preceding claims, further comprising means to generate a substantially low voltage at a clock signal terminal of the memory unit.

6. A circuit as claimed in any one of the preceding claims, further comprising a timer to cause the processor to generate the substantially low voltage for a predetermined period of time sufficient to erase the memory unit.

7. A circuit as claimed in Claim 6, wherein the timer is an R-C circuit.

8. A circuit as claimed in Claim 6 or Claim 7, wherein the predetermined period of time is at least one clock cycle.

9. A circuit as claimed in any one of the preceding claims when dependent on Claim 5, wherein the processor is arranged to manually erase the memory unit once the predetermined period has expired.

10. A circuit as claimed in any one of the preceding claims when dependent on Claim 5, the processor is arranged to erase the programmable Read Only Memory once the predetermined period has expired.

11. A circuit as claimed in any one of the preceding claims, wherein the first bus is an address bus and the second bus is a data bus.

12. A modem comprising the circuit as claimed in any one of the preceding claims.

13. A power saving device comprising the circuit as claimed in any one of Claims 1 to 12.

14. A method of erasing a memory unit in a circuit including a processor and a first bus connected to the processor and the memory unit, the method comprising the steps of halting a supply of current to the memory unit and generating a substantially low voltage by the processor on the first bus.

15. A method as claimed in Claim 14, wherein a second bus is connected to the processor and the memory unit and a programmable Read Only Memory connected to the second bus, the method further comprising the step of generating a substantially low voltage at the second bus by the programmable Read Only Memory so as to deprive the memory unit of power.

16. A method as claimed in any one of Claim 14 or Claim 15, further comprising the step of generating a substantially low voltage at a write terminal of the memory unit.

17. A method as claimed in any one of Claims 14 to 16, further comprising the step of generating a substantially low voltage at a read terminal of the memory unit.

18. A method as claimed in any one of Claims 14 to 17, further comprising the step of generating a substantially low voltage at a clock signal terminal of the memory unit.

19. A method as claimed in any one of Claims 14 to 18, further comprising the step of generating the substantially low voltage for a predetermined period of time.

20. A method as claimed in Claim 19, wherein the predetermined period of time is at least one clock cycle.

21. A method as claimed in Claim 19 or Claim 20, comprising the step of manually erasing the memory unit once the predetermined period has expired.

22. A method as claimed in any one of Claims 19 to 21, comprising the step of erasing the programmable Read Only Memory once the predetermined period has expired.

23. A method as claimed in any one Claims 14 to 22, wherein the first bus is an address bus and the second bus is a data bus.

24. A circuit substantially as hereinbefore described with reference to Figures 1, 3 and 4.

25. A method of erasing a memory unit in a circuit substantially as hereinbefore described with reference to Figure 2.