JPH07225718A - Microcomputer system - Google Patents

Abstract

PURPOSE:To prevent the over of the number of times of data write into EEPROM caused by the runaway of computer or the like and to surely and easily manage the number of times of data write. CONSTITUTION:In the case of writing data in an EEPROM 102 with a CPU 101 access from the CPU within a fixed time T is monitored by a watchdog timer (WDT) 109 and the area select signal of a selector 105 for the access of the EEPROM is suppressed by a circuit 111 when there is no access, so that unwanted write and the over of the number of times of write into the EEPROM caused by the runaway of the CPU can be prevented. The operation of the selector is suppressed by a one-shot trigger circuit 112 just for a fixed time from the data write into the EEPROM so that required interval time can be secured in the EEPROM and the number of times of unwanted write at the time of runaway can be estimated and managed from timer relation with the WDT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device, and more particularly to a control device for managing the number of times data is written in an EEPROM.

[0002]

2. Description of the Related Art A volatile memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) which is generally used as a data storage means of a microcomputer device is powered down. If you do, the memory information (data) will be lost.

However, in a system that requires time management and information before power-off at the time of restarting, backup by a battery of a volatile memory or electrically writable E
EPROM (Electrically Erasab)
le ・ PROM) etc. are used.

The EEPROM has a characteristic of retaining data even when the power is turned off, but the number of times data can be written in the internal cell is limited. This is usually about 10,000 to 100,000 times per cell depending on the characteristics of the device, but if the number of times is exceeded, there is no guarantee of data reliability.

Therefore, it is necessary to manage the number of writes by the system master (CPU). In addition, once writing is performed, writing cannot be performed until some time has passed. This time is called a write interval time.

The management of the number of times of writing is generally a method of continuously writing the number of times of writing and necessary information to several addresses by a software program. The write interval time is generally managed by an interval timer made of hardware or software.

FIG. 9 shows a computer system in which the EEPROM is mounted. Further, FIG. 10 shows an example of the internal information of the EEPROM. 101 is a CPU and 102 is an EEP
ROM, 103 is a read (RD) signal, 104 is a write (WR) signal, 105 is a selector for selecting a device, 106 is an address group of the CPU 101, 107 is EE
This is a selection signal for the PROM 102. In addition, a is count information and b is necessary information. When writing, writing is performed byte by byte.

[0008]

As mentioned above, the EEP
Since the reliability of the writing information in the ROM is limited by the number of times of writing, the number of times of writing must be managed. This management is generally performed by software, but if the CPU or software runs out of control for some reason, not only the management information of the number of writes becomes erroneous,
One cell may be written tens of thousands of times, and the reliability of the device itself cannot be guaranteed. In addition, since the number of times of writing is uncertain and the confirmation cannot be obtained at the time of restart, it is necessary to replace the device (EEPROM).

It is an object of the present invention to provide a microcomputer device which prevents the number of times data is written to the EEPROM due to a computer runaway or the like.

Another object of the present invention is to provide a microcomputer device which surely and easily manages the number of times data is written in the EEPROM.

[0011]

In order to solve the above-mentioned problems, the present invention provides a microcomputer device having an EEPROM as a data storage means when the CPU does not access within a certain time T.
Watchdog timer that suppresses area selection for access to the memory, and the time from the previous writing of data to the EEPROM to the present writing of data is constant time t
And an interval timer that allows the area selection when the above conditions are met.

Further, the present invention is a microcomputer device having an EEPROM as a data storage means, for writing number counting EEPROM for storing data writing number data for each address of the EEPROM.
M, a counter unit having a count-up function and performing a write-over interrupt to the CPU by counting up to a set value, and the CPU from the EEPRO
When writing data to M, a control circuit for reading the writing frequency data of the counting EEPROM corresponding to the address to the counter means and rewriting the data counted up by the counter means to the counting EEPROM. It is characterized by having.

[0013]

According to the first aspect of the present invention, writing to the EEPROM is suppressed by monitoring the computer runaway by the watch dog timer, and unnecessary writing operation to the EEPROM is eliminated.

Also, the EEP by the interval timer
It limits the write interval time to the ROM and makes it possible to analogize the wrong access count during runaway of the computer from the time T of the watch dog timer and the interval time t.

According to a second aspect of the present invention, there is provided a counting EEPROM for storing the number of times data is written to the EEPROM.
EEP for counting each time data is written to EEPROM
The data in the ROM is counted up by the counter means, and when the count value exceeds the number of times of writing, it is possible to recognize the number of times of writing by interrupting the CPU.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 108 is EEP
Area selection signal of ROM 102, 109 CPU 101
Software that manages the normal operation of
A timer 110 is an inhibit signal that is output when a time-out occurs in the event of software abnormality, and 111 is a circuit that outputs the area selection signal 108 to the EEPROM selection signal 107 when the inhibit signal 110 is not asserted.

Further, 112 is a one-shot trigger circuit which is asserted after writing to the EEPROM 102 and negated after a certain period of time, 113 is a signal by the one-shot trigger circuit 112, and when this signal is not asserted The output of the area selection signal from the selector 105 is suppressed. 114 is a ready circuit,
Wait when the selection signal 107 is not output (standby)
Put in a state. Reference numeral 115 is a ready signal to the CPU 101, 116 is a circuit representing writing to the EEPROM 102, and 117 is a signal for periodically triggering the watch dog timer 109.

The operation of this embodiment will be described below with reference to the normal operation sequence of FIG. 2 and the protection operation sequence of FIG. The following items (1) to (5) are included in the sequence.
Are shown in association with each other.

(1) By the program, the CPU 101
Accesses the watch dog timer 109 every certain time (here, time T). This timer asserts an inhibit signal 110 by the watch dog timer 109 when there is no access from the CPU 101 even after a lapse of 2T (arbitrary). This timer access operation is independent of any other program.

(2) The CPU 101, which needs to write to the EEPROM 102, outputs the area / address group 106 and the write signal 104 of the EEPROM 102. Further, the selector 105 decodes the address group 106 and outputs the area selection signal 108 of the EEPROM.

(3) The software watch dog timer 109 activated as described in (1) above is the CPU 1
While 01 is operating normally, the inhibit signal 110 is not asserted because the timer access is made every time T, and the EEPROM selection signal 107 is set to EEPROM1.
It is input to 02.

The assertion of the selection signal 107 causes the ready circuit 114 to operate, and the ready signal 115 is returned to the CPU 101 to complete the access.

(4) The CPU 101, which needs to write the EEPROM 102 for the second time and thereafter, is
Performs the same operation as. However, the signal output from the circuit 116 by the previous writing operation is a one-shot signal.
Although the signal of the trigger circuit 112 (assuming the time width is t) is asserted, the signal 108 is not output from the circuit 105 unless the signal 113 is asserted until the time t elapses and the one-shot trigger circuit 112 is negated. ,
The CPU 101 is in a wait state. This time t corresponds to the above write interval time. After that, EEP
Writing to the ROM 102 repeats the operation (4).

The above operation is shown in the sequence of FIG.

(5) Here, as shown in FIG. 3, it is assumed that the program has run away due to some abnormality. Watch
The dog timer circuit 109 is the CPU 1 even if the time T elapses.
Since the access from 01 does not occur, the signal 110 is asserted and the circuit 111 is locked after the time 2T.

Therefore, since the writing operation to the EEPROM 102 after that does not occur, an erroneous access due to a runaway can be locked. Further, since the writing circuit is controlled by hardware, erroneous writing of 2T / t times or more does not occur.

Although the counter value may be destroyed by the incorrect writing of 2T / t times, if the time T is less than 10 times t (one digit in order), EE
Based on the overall information of PROM 102, the counter that was illegally written by incorrect access at the time of restarting the power supply.
Since the address and its value can be analogized, EEP
It is possible to confirm the reliability of the ROM 102 (how many times writing has been performed at maximum).

FIG. 4 is a circuit diagram showing another embodiment of the present invention. 1 is a CPU, 2 is a data EEPROM, 3 is a read (RD) signal, 4 is a write (WR) signal, 5 is a selector for selecting a device, 6 is an address group of the CPU 1, and 7 is a selection signal of the data EEPROM 2. is there.

Reference numeral 8 is a CPU data group, 11 and 12 are bidirectional data buffers and data groups for exchanging data with the data EEPROM 2, 13 is a ready circuit for the EEPROM 2, and 14 is a ready signal of the CPU 1.

Further, 15 is an address buffer with a latch, 16 and 17 are addresses 0 and non-address 0 of addresses given to the EEPROM 2, 18 is an EEPROM for counting the number of times of writing, and 19 and 20 are selection conditions of the EEPROM 2, respectively. The incoming RD and WR signals.

Reference numerals 21 and 22 denote read signal / write signal generation circuits (logical product circuits) with a selection condition for the EEPROM 2. 23 is an EEPROM control circuit for counting the number of times of writing. Reference numeral 24 denotes an EEPROM ready generation permission signal (RDY) to be passed to the CPU ready generation circuit at the time of EEPROM access.
ENB).

Reference numerals 25, 26 and 27 are address bit 0 of the EEPROM for counting the number of times of writing, a read (RD) signal and a write (WR) signal. 28 and 29 are 16-bit counters for the number of times of writing, which are divided into lower 8 bits and upper 8 bits, respectively, and are connected by carry data 35.

Reference numeral 30 is an EEPR for counting the number of times of writing.
The data group of the OM 18 is divided into L byte data 33 and H byte data 34 through the buffers 31 and 32 in the upper digit / lower digit of the 16-bit counter.

Reference numerals 36, 37, 38, 39 and 40 denote control signals for the counter and the L / H byte data buffer, which are an H byte / L byte gate enable signal and an H byte / L byte counter, respectively. These are load signal and counter clock signal.

Reference numeral 41 denotes the data bit output of the H byte counter, which is the highest 7 bits of the data bit here.

A flip-flop 42 latches the output 41 with the write signal 27. An output 43 of the flip-flop 42 is a signal for interrupting the CPU 1.

Reference numeral 44 is a circuit for lighting an LED (light emitting diode) as a display means by the interrupt signal 43.
45 and 46 are EEPROM 18 for counting the number of times of writing
Clear setting circuit and setting information. 47 is H / L counter clear information from the CPU 1. Reference numeral 48 is a counter clear signal, and 49 is a circuit which lights up only while the counter clear signal 48 is asserted.

Reference numeral 50 is a CPU accessible register for reading the states of the signals 43 and 46 and passing a clear signal 47 to the EEPROM control circuit 23.

Reference numerals 51 and 52 are a data group and a data buffer for exchanging data between the register 50 and the CPU 1.
Reference numeral 53 is a signal for latching the address of the EEPROM 2.

The operation of this embodiment will be described in detail below with reference to FIGS.

(A) Initialization sequence (FIG. 5)
reference).

EEPROM 18 for writing number counter
Is an operation to set all the contents of 0 to 0. EEPRO for data
This is performed before the write operation is first performed in M2 (for example, at the time of factory shipment). The sequence is as follows.

(A1) By shorting the setting circuit 45, the signal 46 becomes L level. After the power is turned on, the CPU 1 refers to the register 50 to check the level of the signal 46. In that case, signal 48 and signal 3 are asserted and 51
→ Data buffer 52 → Data is read by the route of 8.

(A2) After confirming the L level of the signal 46, C
PU1 performs a write operation on the internal bit of the register 50 and asserts the clear signal 47. In this case, the clear signal 48 and the write signal 4 are asserted, and writing is performed by the route of 8 → data buffer 52 → 51. The contents of the register 50 are shown in FIG.

(A3) Control circuit 23 which has detected the signal 47
Drives the counter clear signal 48 to the L level,
The write counters 28 and 29 are cleared to zero. At the same time, the LED lighting circuit 49 is turned on.

(A4) The CPU 1 uses the data EEPROM
Initialize all areas of M2 (write data is arbitrary).

At the same time, the control circuit 23 controls the write count E
The entire area of the EPROM 18 is read from the counters 28 and 29 and cleared to 0. During that time, since the lighting circuit 49 is lit, it can be visually confirmed. Details of the write sequence will be described later.

(A5) When the all area initialization is completed, the CPU 1 performs a write (WR) operation on the bit inside the register 50 and negates the signal 47. At the same time, since the control circuit 23 negates the signal 48, the clearing of the counters 28 and 29 is released and the lighting circuit 49 is turned off.

(A6) When it is confirmed that the lighting circuit 49 is turned off, the setting (short circuit) of the setting circuit 45 is opened, and the initialization sequence is completed. After that, the setting circuit 45 does not short-circuit until the initialization sequence by replacing the EEPROM.

(B) Normal operation (write operation) (see FIG. 7).

(B1) CPU 1 is a data EEPROM
It is assumed that a write (write) operation is performed on 2. In this case, the selector 5 outputs the selection signal 7 and the write signal 4, and the circuit 22 outputs the write pulse 20. Further, the write address and the data are the address group 6 respectively.
→ The buffers 15 → 16, 17 and the data group 8 → buffer 11 → 12 are passed in this order. Here, EEPROM2
The chip select signal is always selected.

(B2) At the same time as the above (B1), the control circuit 23 receiving the write pulse 20 outputs an address latch pulse 53 to latch the address information in the buffer 15. Of this address information, the upper bits except the least significant bit also serve as the address of the counting EEPROM 18.

Simultaneously with the latching of the address information, the control circuit 23 changes the address bit 0 signal 25 in the order of 0 and 1, and changes the least significant bit digit of the address data to the EEPROM 18 in the order of even and odd bytes. The write count data (2 bytes) of the address written in the write count EEPROM 18 is separately read into the counters 28 and 29.

In that case, the read signal 26, the buffer control signals 36, 37 and the data load signals 38, 39 are used.

(B3) After the count information is loaded into the counter in (B2), the counter clock 40 counts up. The counted up data changes the address 0 signal 25 in the order of 0 and 1, and rewrites to the same address of the counter EEPROM 18 using the buffer control signals 36 and 37 and the write signal 27.

In this case, the byte of the lower digit L / upper digit H of the data is signal 30 → buffer 31 → signal 33 or signal 3
The route of 0 → buffer 32 → signal 34 is used.

(B4) EEPR for data in (B1)
When the write operation of the OM2 is completed, the control circuit 23 asserts the ready generation permission signal 24 and returns the ready signal 14 from the ready circuit 13 to the CPU 1. However, during the operation of (B2) and (B3), the EEPROM2
When the write operation to (1) is performed, the signal 24 is negated and the operation of (B2) and (B3) is waited for.

When the write operation is continuously performed on the EEPROM 2, the CPU 1 always waits. However, in practice, the control circuit 23 asserts the ready generation permission signal 24 during the read operation. This is not a problem because the write cycle interval is very long.

By the above operation, the number of times written in the EEPROM 2 can be stored in the counter EEPROM 18 in units of 2 bytes. Further, when managing in units of 1 byte, one EEPROM 18 is added.

(C) Management of number of times of writing (see FIG. 8).

(C1) Counters 28 and 29 have a total of 16
Since it is a bit counter, it can count up to 65,000 times. Here, when the MSB bit is counted until it becomes “1”, it can be counted about 32,000 times. Since the above circuit manages in units of 2 bytes, the MSB becomes "1" when the write operation is performed about 16000 times or more (less than 32000 times).

(C2) When the MSB of the counter 29 becomes "1", the latch circuit 42 is latched at the timing of writing to the counting EEPROM 18. The latched signal 43 interrupts the CPU 1 and turns on the circuit 44 at the same time, so that the write count of a certain byte is about 160.
Notify that it has been over 00 times.

(C3) After detecting the interrupt, the CPU 1 confirms that the signal 43 is asserted in the register 50 and can detect the overwriting of the EEPROM 2.

As described above, it is possible to prevent the overflow of the number of writing times of the EEPROM 2.

The limit number of times of writing can be set arbitrarily depending on which bit of the signal 41 is used (or combination).

Further, as described above, the counter EEPRO
If M18 is increased by one, an accurate number can be counted for each byte. Further, if a circuit (register) for reading the latched value is added to the address buffer 15,
The number of writes can be confirmed for each address.

[0067]

As described above, according to the present invention, the watchdog timer monitors the runaway of the computer,
Since the writing to the EEPROM is suppressed by the runaway detection, a large number of write operations to the EEPROM are eliminated by the runaway.

EEP by interval timer
By combining with the function that limits the interval time for writing to ROM, in addition to securing a certain interval time, it is possible to infer the number of incorrect accesses during a computer runaway from the time T of the watch dog timer and the interval time t. To facilitate management of the number of writes.

Further, a counting EEPROM for storing the number of times of writing data to the EEPROM is provided, and the EEPROM is
By counting up the data of the counting EEPROM by the counter means every time data is written to the OM, it is possible to prevent the number of times of writing from being exceeded from the count value and to ensure the management and recognition thereof.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a normal operation sequence according to the embodiment.

FIG. 3 is a protection operation sequence according to the embodiment.

FIG. 4 is a circuit diagram of another embodiment.

FIG. 5 is an initialization sequence of another embodiment.

FIG. 6 shows an example of contents of a register 50 according to another embodiment.

FIG. 7 shows a normal operation sequence of another embodiment.

FIG. 8 is a write count management sequence according to another embodiment.

FIG. 9 shows an example of using the EEPROM.

FIG. 10 shows an example of internal information of an EEPROM.

[Explanation of symbols]

 1, 101 ... CPU 2, 102 ... EEPROM 5, 105 ... Selector 13, 114 ... Ready circuit 18 ... Write count count EEPROM 23 ... Write circuit count EEPROM control circuit 28, 29 ... Write count bit counter 31, 32 ... Buffer 42 ... Latch circuit 45 ... Setting circuit 50 ... Register 109 ... Watch dog timer 112 ... One-shot trigger circuit

Claims (2)

[Claims] 1. In a microcomputer device having an EEPROM as a data storage means, the EEPROM is accessed when there is no access from the CPU within a certain time T.
Watchdog timer that suppresses area selection for access to the memory, and the time from the previous writing of data to the EEPROM to the present writing of data is constant time t
A microcomputer device, comprising: an interval timer that permits the area selection when the above is reached. 2. A microcomputer device having an EEPROM as data storage means, wherein the EEPR
An EEPROM for storing the number of times of writing the data for storing the number of times of writing the data for each address of the OM, and a count-up function to count up to a set value.
A counter means for interrupting the writing to the PU and a count means corresponding to the address when writing data from the CPU to the EEPROM is read to the counter means and counted by the counter means. And a control circuit for rewriting the updated data to the counting EEPROM.