GB2320964A - Method for testing electronic devices attached to a leadframe - Google Patents

Method for testing electronic devices attached to a leadframe Download PDF

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Publication number
GB2320964A
GB2320964A GB9804053A GB9804053A GB2320964A GB 2320964 A GB2320964 A GB 2320964A GB 9804053 A GB9804053 A GB 9804053A GB 9804053 A GB9804053 A GB 9804053A GB 2320964 A GB2320964 A GB 2320964A
Authority
GB
United Kingdom
Prior art keywords
leadframe
integrated circuit
circuit packages
testing
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9804053A
Other versions
GB9804053D0 (en
GB2320964B (en
Inventor
Yiu Kam Law
Glenn King Tong Cheung
Pak So Lie
Simon Hong Sing She
Kwok Heung Ho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to GB9804053A priority Critical patent/GB2320964B/en
Publication of GB9804053D0 publication Critical patent/GB9804053D0/en
Publication of GB2320964A publication Critical patent/GB2320964A/en
Application granted granted Critical
Publication of GB2320964B publication Critical patent/GB2320964B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method for testing electronic devices attached to a leadframe includes positioning more than one electronic device 42, 44, 46 attached to a common leadframe underneath a test fixture 50. The test fixture 50 then contacts the devices 42, 44, 46 to perform an electrical test. Testing more than one device at a time while they are attached to a common leadframe greatly improves efficiency of the testing process. Furthermore, positioning the devices 42, 44, 46 below the test fixture 50 reduces the amount of contamination that may settle on the test fixture. The leadframe and associated electronic devices are transported by a walking beam 36 from a heated storage area 30 to the test site 40 then to a further storage area 64. The walking beam 36 may be heated and an inker 62 may mark failed devices.

Description

METHOD FOR TESTING ELECTRONIC DEVICES ATTACHED TO A LEADFRAME Background of the Invention The present invention relates, in general, to testing electronic devices, and more particularly, to testing electronic devices attached to a leadframe.
Part of the standard manufacturing process for electronic devices such as packaged semiconductor devices includes a final electrical test. In the past, the final electrical test has been performed after the packaged electronic devices have been separated from a leadframe which connects several devices during processing.
Accordingly, the devices must each be handled individually. Handling each device individually increases the complexity of the test operation because, for example, the devices must each be picked up separately and aligned to a test fixture or test socket.
An approach which has been taken to provide significant improvement over the conventional testing is to test the packaged electronic devices while they are still connected to a common leadframe. The handling of the devices is significantly simplified because several are connected together. Consequently, only a single leadframe need be handled to accomplish the testing of several devices. Furthermore, the electronic devices attached to a common leadframe are inherently accurately aligned to a particular orientation with reference to the leadframe. Therefore, during testing, the devices attached to a leadframe do not need to be individually aligned to the test fixture. Only the common leadframe need be aligned.
It is convenient to align a leadframe because it may be transported and positioned along a track.
Individual packaged devices are not so easily aligned because they must be moved with a pick-and-place or manual arrangement. One such test-on-leadframe configuration disclosed in the past is found in U.S.
Patent No. 5,008,615, issued to Littlebury on April 16, 1991. One disadvantage of the system disclosed, however, is that the test fixture which is mated with the devices attached to a common leadframe lies below the leadframe.
This configuration allow contaminants such as dust and debris to settle on the contacts where the leads of the electronic devices contact the test fixture. The problem of the test fixture lying below the devices under test is pervasive throughout the prior art. Contaminants which settle on the electrical contacts of the test fixtures of the prior art severely interfere with testing and overall performance.
Another disadvantage of prior art approaches arises from the fact that testing the devices sometimes takes longer than the subsequent trim-and-form and singulation steps. Under these circumstances the trim-and-form equipment waits idle for electrical testing to be completed. This condition results in inefficiency in manufacturing and increased cycle time.
What is needed is an electronic device test arrangement which does not test each electronic device individually. Furthermore, it would be desirable if the testing arrangement did not result in idle trim and form equipment. Moreover, it would be a significant advantage if the test arrangement did not permit contaminants to settle on the electrical contacts of the test fixture.
Summary of the Invention According to the present invention there is provided a method for testing electronic devices attached to a leadframe, comprising the steps of: providing integrated circuit packages connected to a single leadframe, the integrated circuit packages having extending leads separated from one another; heating a first storage area; transporting the leadframe along a walking beam from the first storage area to a test site; raising the leadframe upward to mate with a test fixture disposed perpendicular to gravity, the test fixture having electrical contacts, the extending leads contacting the electrical contacts from below; electrically testing the integrated circuit packages; transporting the leadframe along the walking beam from the test site to a second leadframe storage area; and singulating the integrated circuit packages.
Brief Description of the Drawings FIG.1 is a top view of a plurality of a electronic devices attached to a single leadframe; FIG.2 is a simplified drawing of an apparatus which provides testing in accordance with a preferred embodiment of the present invention; FIG.3 is a side view of the test fixture included in the apparatus of FIG.2; and FIG.4is a bottom view of the test fixture of FIG.3.
Detailed Description of the Drawings The present invention provides significant improvement over the methods for testing electronic devices of the prior art.
The present invention tests devices while they are still attached to a common leadframe. Consequently, the devices do not need to be handled individually, and they are more easily aligned to a test fixture. Furthermore, the preferred method positions the test fixture above the devices to be tested. As used throughout the present specification and the following claims, the terms above, over, below and beneath are relative to the direction of gravity. For example, when the test fixture is said to be above the devices to be tested, this means the test fixture is separated from the devices to be tested in the direction opposite to the direction of gravity. This arrangement is important because when the test fixture is above the devices to be tested, contaminants can not settle on the electrical contacts of the test fixture. In the preferred arrangement, the test fixture is perpendicular to the direction of gravity.
Additionally, an alternate method in accordance with the present invention provides two or more separate test apparatus testing two or more corresponding separate leadframes. After testing, the two or more leadframes are fed to a single trim and form apparatus.
Consequently, any potential idle time of the trim and form apparatus is eliminated.
Turning to the figures, FIG. 1 is a top view of a plurality of electronic devices attached to a single leadframe. Electronic devices 10, 12, and 14 are typical dual in-line package devices comprising plastic (epoxy resin) encapsulation and extending leads represented by leads 16 and 18 of device 10. The devices comprise integrated circuits or other similar solid state semiconductor devices within the encapsulation. The leads provide electrical contact to the solid state device within the package.
Devices 10, 12 and 14 are each attached to single leadframe 20. It should be understood that during the manufacturing process the leads, e.g. 16 and 18, are initially connected to each other by a dambar portion of the leadframe. As shown in FIG. 1, the dambars have been removed in order to electrically separate the individual leads for subsequent electrical testing of the device.
The leads, however, extend straight out and have not yet been trimmed and formed.
Although six lead devices are shown for simplicity and clarity, the preferred method is capable of testing any type of electronic device, including small outline integrated circuit (SOIC) 28 lead packages or quad-flat pack packages, which are well known in the art.
FIG. 2 is a simplified drawing of the apparatus which provides testing of electronic devices in accordance with the preferred method of the present invention. Storage area 30 represents an input storage area which may house a leadframe magazine holding a plurality of leadframes, as is well understood in the art. Heater 32 is preferably a hot air blower which is capable of heating the leadframes and attached electronic devices. Heater 32 is used when the devices must be tested at an elevated temperature. When heater 32 is used to heat the devices, storage area 30 is substantially enclosed and thermally insulated. Cable 34 represents the power cable providing power to heater 32.
Walking beam 36 represents the mechanism which transports the leadframe and attached electronic devices through the apparatus. Many mechanisms may be used for moving leadframe 20 (FIG. 1) along. Often, leadframes are perforated at their edges. In such instances, properly located toothed sprockets may move the leadframes along. In the preferred method, pins (not shown) come up from beneath walking beam 6 and move laterally to slide the leadframe along. Resistive heater 38 is attached to walking beam 36 in a manner to provide heat conduction between resistive heater 38 and walking beam 36. Cable 37 represents the power cable providing power to heater 38.
Positioned at the center of walking beam 36 is test site 40. It should be understood that test site 40 can be heated to the same temperature as walking beam 36 by heat conduction through beam 36 from resistive heater 38 and by hot air blower 61 located between test site 40 and test fixture 50. Consequently, the electrical devices attached to the leadframes can be heated via heater 32 and the temperature can be maintained across the walking beam and at the test site due to heater 38 and hot air blower 61.
Test site 40 is shown holding a leadframe similar to the leadframe shown in FIG. 1. Electronic devices 42, 44 and 46 are attached to a single leadframe, and are the devices to be tested. Test site 40 is capable of moving up and down as indicated by arrow 48. In the preferred embodiment, test site 40 lies directly beneath test fixture 50. Also, in the preferred embodiment test fixture 50 comprises subfixtures 52, 54 and 56.
Subfixtures each provide electrical contacts (represented by contacts 58 and 60) corresponding to the leads extending from the electronic devices below.
According to the preferred method, a leadframe is dispensed from storage area 30, transported along walking beam 36 and positioned at test site 40. Subsequently, test site 40 is raised directly upward toward test fixture 50 such that the leads of the electronic devices contact the electrical contacts of the subfixtures. The electronic devices thus mate with fixture 50. It should be understood that fixture 50 is electrically coupled to a conventional device testing apparatus which can run the appropriate electrical test, typically driven by software, for the particular electronic device under test. It should also be understood that more than one of the electronic devices may be tested simultaneously.
Preferably, all devices attached to a single leadframe are tested simultaneously. Additionally, it should be understood that in alternate methods, the test fixture may be brought down into contact with the devices at test site 40 while test site 40 remains stationary.
Turning briefly to FIGs. 3 and 4 before returning to FIG. 2 for the remainder of the description of the testing apparatus, FIGs. 3 and 4 are enlarged views of test fixture 50. FIG. 3 is a side view showing the pointed electrical contacts, represented by contacts 58 and 60, of the subfixtures. FIG. 4 is a bottom view of fixture 50. FIG. 4 illustrates that the electrical contacts are arranged to correspond to the leads of the electronic devices (shown in FIG. 1). It should be understood that the configuration of test fixture 50 will vary according to the configuration of the electronic device to be tested. An important feature of test fixture 50 is that the electrical contacts point directly downward. This arrangement provides substantial improvement over test systems of the prior art because it prevents contaminants from settling on the electrical contacts.
In the prior art, similar test fixtures might be disposed below or to the side of the devices to be tested. Extended exposure to the testing environment inherently allowed contaminants to collect on the electrical contacts in such configurations. The contaminants give rise to severe disadvantages such as test equipment failure and equipment down time. The arrangement in accordance with the preferred method of the present invention greatly reduces contaminants collecting at the test fixture electrical contacts.
Returning to FIG.2, walking beam 36 extends past test site 40 to inker 62, and finally to a second storage site 64. After the electrical test of a group of electronic devices attached a particular leadframe is completed, the walking beam moves the leadframe to inker 62. Inker 62 includes ink brush 66.
It should be understood that the entire test apparatus is controlled by a computer (not shown) according to methods well known in the art. During the test of a group of a devices, any failing devices are identified by the computer.
The computer directs inker 62 to mark any failing device so that it can be identified later and separated from the good devices.
Finally, the leadframes are collected in storage area 64 which preferably houses a leadframe magazine that may be removed and moved on to other manufacturing equipment, i.e trim and form equipment.
By now it should be appreciated that a method has been provided which is capable of testing more than one electronic device at a time, while the devices are still attached to a common leaciframe. This results in substantial increased efficiency. Additionally, the method significantly limits the amount of contaminants that can settle on the test fixture. Furthermore, a method has been provided which eliminates trim and form apparatus idle time.

Claims (6)

Claims
1. A method for testing electronic devices attached to a leadframe, comprising the steps of: providing integrated circuit packages connected to a single leadframe, the integrated circuit packages having extending leads separated from one another; heating a first storage area; transporting the leadframe along a walking beam from the first storage area to a test site; raising the leadframe upward to mate with a test fixture disposed perpendicular to gravity, the test fixture having electrical contacts, the extending leads contacting the electrical contacts from below; electrically testing the integrated circuit packages; transporting the leadframe along the walking beam from the test site to a second leadframe storage area; and singulating the integrated circuit packages.
2. The method of claim 1, further comprising the steps of identifying failing integrated circuit packages and inking the failing integrated circuit packages.
3. The method of claim 1 or claim 2 wherein the step of electrically testing comprises testing more than one integrated circuit package simultaneously.
4. The method of any preceding claim further comprising the step of heating the walking beam.
5. The method of any preceding claim wherein the step of providing the integrated circuit packages comprises providing small outlined integrated circuits each having 28 of the extending leads.
6. The method of any preceding claim the step of providing the integrated circuit packages comprises providing quad-flat packs.
6. The method of any preceding claim the step of providing the integrated circuit packages comprises providing quad-flat packs.
Amendments to the claims have been filed as follows Claims 1. A method for testing electronic devices attached to a leadframe, comprising the steps of: providing integrated circuit packages connected to a single leadframe, the integrated circuit packages having extending leads separated from one another; heating a first storage area; transporting the leadframe along a walking beam from the first storage area to a test site; raising the leadframe upward to mate with a test fixture disposed perpendicular to gravity, the test fixture having electrical contacts the extending leads contacting the electrical contacts from below; electrically testing the integrated circuit packages; and transporting the leadframe along the walking beam from the test site to a second leadframe storage area.
2. The method of claim 1, further comprising the steps of identifying failing integrated circuit packages and inking the failing integrated circuit packages.
3. The method of claim 1 or claim 2 wherein the step of electrically testing comprises testing more than one integrated circuit package simultaneously.
4. The method of any preceding claim further comprising the step of heating the walking beam.
5. The method of any preceding claim wherein the step of providing the integrated circuit packages comprises providing small outlined integrated circuits, each having 28 of the extending leads.
GB9804053A 1993-11-25 1993-11-25 Method for testing electronic devices attached to a a leadframe Expired - Fee Related GB2320964B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9804053A GB2320964B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a a leadframe

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9324219A GB2285139B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a leadframe
GB9804053A GB2320964B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a a leadframe

Publications (3)

Publication Number Publication Date
GB9804053D0 GB9804053D0 (en) 1998-04-22
GB2320964A true GB2320964A (en) 1998-07-08
GB2320964B GB2320964B (en) 1998-08-26

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GB9804054A Expired - Fee Related GB2320965B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a leadframe
GB9324219A Expired - Fee Related GB2285139B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a leadframe
GB9804053A Expired - Fee Related GB2320964B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a a leadframe

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GB9804054A Expired - Fee Related GB2320965B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a leadframe
GB9324219A Expired - Fee Related GB2285139B (en) 1993-11-25 1993-11-25 Method for testing electronic devices attached to a leadframe

Country Status (4)

Country Link
JP (1) JPH07253450A (en)
CN (1) CN1104647C (en)
GB (3) GB2320965B (en)
MY (1) MY118387A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004395A1 (en) * 1998-07-15 2000-01-27 Siemens Aktiengesellschaft Device for the electric testing of integrated circuits

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG82566A1 (en) * 1996-10-17 2001-08-21 Motorola Inc Method and apparatus for transporting ang testing electronic devices attached to a leadframe
NL1008697C2 (en) * 1998-03-25 1999-09-28 Fico Bv Test device, test assembly, method for testing and method for calibrating a test device.
NL1012420C2 (en) * 1999-06-23 2000-12-28 Johannes Nicolaas Peperkamp Method for measuring electronic components, in particular integrated circuits, and device for that purpose.
JP4111767B2 (en) 2002-07-26 2008-07-02 株式会社ルネサステクノロジ Manufacturing method of semiconductor device and electrical property inspection method of small element
US20080265923A1 (en) * 2007-04-27 2008-10-30 Microchip Technology Incorporated Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like
CN102565652A (en) * 2010-12-30 2012-07-11 展晶科技(深圳)有限公司 Detection device and detection method of encapsulation structure of light-emitting diode

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855672A (en) * 1987-05-18 1989-08-08 Shreeve Robert W Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same
US4985988A (en) * 1989-11-03 1991-01-22 Motorola, Inc. Method for assembling, testing, and packaging integrated circuits
US5008615A (en) * 1989-11-03 1991-04-16 Motorola, Inc. Means and method for testing integrated circuits attached to a leadframe
GB2249868A (en) * 1990-11-15 1992-05-20 Sgs Thompson Microelectronics A testing and finishing system for integrated circuit package units

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855672A (en) * 1987-05-18 1989-08-08 Shreeve Robert W Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same
US4985988A (en) * 1989-11-03 1991-01-22 Motorola, Inc. Method for assembling, testing, and packaging integrated circuits
US5008615A (en) * 1989-11-03 1991-04-16 Motorola, Inc. Means and method for testing integrated circuits attached to a leadframe
GB2249868A (en) * 1990-11-15 1992-05-20 Sgs Thompson Microelectronics A testing and finishing system for integrated circuit package units

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004395A1 (en) * 1998-07-15 2000-01-27 Siemens Aktiengesellschaft Device for the electric testing of integrated circuits

Also Published As

Publication number Publication date
GB9804053D0 (en) 1998-04-22
GB2320964B (en) 1998-08-26
GB2320965A (en) 1998-07-08
CN1106926A (en) 1995-08-16
GB2285139A (en) 1995-06-28
JPH07253450A (en) 1995-10-03
GB9324219D0 (en) 1994-01-12
CN1104647C (en) 2003-04-02
MY118387A (en) 2004-10-30
GB2285139B (en) 1998-06-24
GB2320965B (en) 1998-08-26
GB9804054D0 (en) 1998-04-22

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732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20071125