GB2320612A - Encapsulating a component mounted on a substrate - Google Patents
Encapsulating a component mounted on a substrate Download PDFInfo
- Publication number
- GB2320612A GB2320612A GB9723413A GB9723413A GB2320612A GB 2320612 A GB2320612 A GB 2320612A GB 9723413 A GB9723413 A GB 9723413A GB 9723413 A GB9723413 A GB 9723413A GB 2320612 A GB2320612 A GB 2320612A
- Authority
- GB
- United Kingdom
- Prior art keywords
- vent holes
- substrate
- component package
- epoxy
- attachment site
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 239000004593 Epoxy Substances 0.000 claims abstract description 61
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 22
- 238000005538 encapsulation Methods 0.000 claims description 21
- 239000007788 liquid Substances 0.000 claims description 3
- 230000013011 mating Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000013022 venting Methods 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- MPTQRFCYZCXJFQ-UHFFFAOYSA-L copper(II) chloride dihydrate Chemical compound O.O.[Cl-].[Cl-].[Cu+2] MPTQRFCYZCXJFQ-UHFFFAOYSA-L 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A substrate 110 having vent holes 213, 214 is used to encapsulate an electrical component package 108. The vent holes extend through the substrate 110 and are centrally positioned below the package. The substrate includes a plurality of pads that mate with corresponding contacts carried on the component package 108. Once mated, an application of epoxy 112 completely around the component package 108 is made. Upon heating, the epoxy 112 flows into a gap 604 between the component package 108 and the substrate 110. The vent holes 213, 214 exhaust air from the gap 604 and allow the epoxy 112 to quickly and completely fill the gap 604, thereby encapsulating the component package 108.
Description
SUBSTRATE EMPLOYING A VENT HOLE ARRANGEMENT
SUITABLE FOR ENCAPSULATING AN ELECTRICAL COMPONENT
PACKAGE MOUNTED THEREON AND RELATED METHOD
Field of the Invention
The present invention relates generally to substrates and more particularly to a substrate suitable for encapsulating an electrical component package mounted thereon.
Background of the Invention
Electrical component packages, such as direct chip attach (DCA) packages, have gained wide acceptance throughout the electronics industry. DCA packages indude a plurality of electrical contacts carried on one surface thereof. The contacts are arranged in an array or other pattern and primarily consist of solder bumps. The package is assembled directly to a substrate, such as a printed circuit board. The substrate includes a plurality of pads carried. The pads are arranged on the substrate to mate with the contacts. Assembly is effectuated by soldering the contacts of the package to the pads of the substrate. The bumps and pads create a gap between the package and the substrate.
For reinforcement and reliability, the assembly of the package and substrate is encapsulated. Encapsulation comprises filling the gap between the package and the substrate. Encapsulation is a two-pass process. In a first pass, a bead of epoxy is dispensed along two adjacent
sides of the package, the assembly is heated to melt the epoxy and
induce capillary flow, and the assembly is subjected to a wait period during which the melted epoxy flows into the gap under capillary action. At the end of the wait period, the assembly is subjected to a second pass of dispensing the epoxy along the other two adjacent sides.
Unfortunately, the two-pass process requires increased cycle time, duplicative equipment for in-line manufacturing, and high levels of process quality control. For example, if the wait time between passes is insufficient, an air bubble could become trapped under the package causing incomplete encapsulation and premature catastrophic mechanical failure of the assembly.
Therefore, what is needed is an apparatus, and associated method, for encapsulating an assembly of a component package and substrate via a one-pass process.
Brief Description of the Drawings
FIG. 1 illustrates a communication system including a portable electronic device employing an encapsulated assembly comprised of a substrate with a vent hole arrangement and an electrical component package;
FIG. 2 illustrates an enlarged, exploded perspective view of the assembly of FIG. 1 prior to encapsulation of the assembly;
FIG. 3 illustrates a bottom, perspective view of the electrical component package of FIG. 1;
FIG. 4 illustrates an enlarged top plan view of the vent hole arrangement of FIG. 1;
FIG. 5 illustrates a cross-sectional view of the assembly of FIG. 1 prior to encapsulation of the assembly and prior to attachment of the substrate and the electrical component package, taken along section lines 5 - 5 in FIG. 2;
FIG. 6 illustrates the cross-sectional view of FIG. 5 with the electrical component package attached to the substrate;
FIG. 7 illustrates a top plan view of the assembly of FIG. 1 with encapsulation material applied about the electrical component package;
FIG. 8 illustrates the cross-sectional view of FIG. 5 with the assembly being encapsulated;
FIG. 9 illustrates the cross-sectional view of FIG. 5 with the assembly encapsulated;
FIG. 10 illustrates the cross-sectional view of FIG. 5 with an alternate assembly being encapsulated; and
FIG. 11 illustrates a top plan view of the substrate of FIG. 1 with an alternate vent hole arrangement.
Detailed Description of the Preferred Embodiments
A substrate employing a plurality of vent holes is used to encapsulate an electrical component package in a one-pass process. The vent holes extend through the substrate and are centrally positioned in an attachment site of the substrate. The attachment site includes a plurality of pads that mate with corresponding contacts carried on the electrical component package. The electrical component package is completely surrounded by epoxy. Upon heating, the epoxy flows into a gap between the electrical component package and the substrate dictated by the contacts and pads. The vent holes exhaust air from the gap and allow the epoxy to quickly and completely fill the gap, thereby encapsulating the component package in a one-pass process.
FIG. 1 illustrates a communication system 100 including an electronic device 101 and a base station 102. The electronic device 101 communicates with the base station 102 via radio frequency (RF) signals 103. The electronic device 101, which is shown as a portable cellular telephone, includes an antenna 104 (viewable via cutaway 105) and a substrate assembly 106 (viewable via cutaway 107). When the electronic device 101 is in operation, the substrate assembly 106 processes signals derived from the RF signals 103 received at the antenna 104, and generates signals to be delivered to the antenna 104 and emitted as the RF signals 103. The substrate assembly 106 includes an electrical component package 108 and a substrate 110. The package 108 is attached to a bottom surface 111 of the substrate 110 (viewable via a cutaway 109) and encapsulated by an epoxy 112. A footprint 114 of the package 108 is depicted on a top surface 113 of the substrate 110 in dotted line. The substrate 110 includes a vent hole arrangement 116 centrally positioned within the footprint 114. The vent hole arrangement 116 aids in encapsulation of the package 108 during manufacture of the substrate assembly 106.
The package 108, as shown in FIGs. 2 and 3, comprises a die 200.
In the illustrated embodiment, the package 108 is a direct chip attach (DCA) package (or "flip chip") having approximate dimensions of 7.5 mm x 5 mm x 1 mm and wherein the die 200 consists essentially of silicon. An interface 302 is carried on a bottom surface 300 of the die 200 for connecting the package 108 to the substrate 110. The interface 302 includes a plurality of contacts 304. In the illustrated embodiment, each of the contacts 304 consist of an etched pad 306 and a bump 308, more clearly shown in FIGs. 5 and 6. The pad 306 is carried directly on the die 200 and is preferably deposited with a high lead alloy or other material suitable for bonding to solder. The bump 308 is formed on the pad 306 via a vacuum vapor deposition process or other suitable process. The bump 308 is preferably comprised of a tin-lead solder, such as one consisting of 97% lead and 3% tin, or other suitable solder.
Referring to FIG. 2, the substrate 110 is preferably a printed circuit board (PCB) comprised of polyimide, epoxy-based flame retardant industrial fiberglass (G10-FR4), or other suitable material. The surface 111 of the substrate 110 includes an attachment site 201 for mounting the package 108. The attachment site 201 comprises a plurality of pads 202 carried on the surface 111 of the substrate 110. The plurality of pads 202 are arranged to underlie corresponding ones of the plurality of contacts 304 of FIG. 3 when the interface 302 of the package 108 and the attachment site 201 of FIG. 2 of the substrate 110 are juxtaposed. Outer ones of the plurality of pads 202 are arranged to define a perimeter, which in the illustrated embodiment is rectangular and approximately 7.5 mm x 5 mm. Remaining ones of the plurality of pads 202 are located within the perimeter. Each of the plurality of pads 202 is electrically connected to a metallic trace, such as copper trace 204, disposed within the substrate 110. The metallic traces conduct electrical signals to and from the plurality of pads 202 for processing.
In the illustrated embodiment, the attachment site 201 is compatible with a DCA package, such as package 108. Each of the plurality of pads 202 includes a flattened eutectic bump 500, as shown in
FIG. 5, and a contact 502. The contact 502 is carried in a recess 504, such as a solder mask opening, of the substrate 110. The contact 502 is preferably electroplated with a copper-nickel alloy, aluminum, or other material suitable for bonding to solder. The flattened bump 500 is bonded to the contact 502 and disposed in the recess 504 surrounding the contact 502 via a reflow heating and flattening process. The flattened bump 500 is preferably comprised of a tin-lead solder, such as one comprised of 60% tin and 40% lead, or other suitable solder having a melting point that is lower than the melting point of the bump 308 of the plurality of contacts 304 of the package 108 (see FIG. 3).
Referring to FIG. 2, the vent hole arrangement 116 is located in proximity to a center 206 of the attachment site 201. The center 206 is located at the intersection of transverse and longitudinal axes 208 and 210 of the attachment site 201. In the embodiment shown in FIGs. 2, 4, 5, 6, 8, and 9, the vent hole arrangement 116 includes three cylindrical vent holes 212, 213, and 214 extending between the surfaces 111 and 113 of the substrate 110. The vent holes 212, 213, and 214 must be sized to permit passage of air, but prevent escape of epoxy. In the illustrated embodiment, the vent holes 212, 213, and 214 may be similarly sized and have a diameter D of approximately 0.3 mm to approximately 0.4 mm, as shown in FIG. 4. The vent holes 212, 213, and 214 are arranged such that their respective center axes 415, 416, and 417 are equidistant from the center 206 and define vertexes of an equilateral triangle 418, as shown in dotted line in FIG. 4. Each of the vent holes 212, 213, and 214 must be sufficiently close to the center 206 to ensure complete epoxy encapsulation and prevent voiding in the epoxy. In the illustrated embodiment, a distance, Dco, from the center 206 to the axes 415, 416, and 417 is approximately 0.6 mm and a distance, Doo, between the axes 415, 416, and 417 is approximately 0.9 mm.
The package 108 is mounted to the substrate 110 by, first, placing the package 108 into engagement with the substrate 110 such that each of the plurality of contacts 304 rest on corresponding ones of the plurality of pads 202, as shown in FIG. 5. The package 108 and the substrate 110 are then reflow heated for approximately 60 secs. to 90 secs. to an approximate peak temperature of 220 "C. Such heating melts the flattened bump 500 of each of the plurality of pads 202, without melting the bump 308 of each of the plurality of contacts 304 of the package 108. The melted solder of the flattened bump 500 is drawn onto the bump 308 of each of the plurality of contacts 304 under surface tension. Upon cooling, the flattened bump 500 of each of the plurality of pads 202 is transformed to a concave solder fillet 600, as shown in
FIG. 6. The concave solder fillet 600 of each of the plurality of pads 202 is fused to the bump 308 of each of the plurality of contacts 304 forming a metallurgical interconnection that both mechanically and electrically joins the package 108 and the substrate 110. The resulting assembly 602 comprises the package 108 mounted onto the substrate 110 with the interface 302 facing and parallel to the attachment site 201, but spaced apart therefrom by the plurality of contacts 304 and the plurality of pads 202 to create a gap 604 ranging from approximately 0.07 mm to approximately 0.13 mm. In the illustrated embodiment, the gap 604 is approximately 0.08 mm.
The different materials comprising the package 108 and the substrate 110, respectively, tend to expand when subjected to elevated temperature, but at different rates. This differential in thermal expansion results in stresses in the solder bonds of the plurality of pads 202 and the plurality of contacts 304, which may ultimately result in failure of the interconnection. To reinforce the interconnection, it is known to encapsulate the assembly 602 by filling the gap 604 with an epoxy. For the encapsulation to be reliable and minimize failure of the interconnection, the epoxy must be voidless and completely fill the gap 604.
As discussed in the Background, encapsulation of packages, such as DCA packages, was previously accomplished by a two-pass process, wherein each pass included a step of dispensing, heating, and waiting.
The two-pass process elevated the manufacturing cycle time for a device employing the package. For example, encapsulating a 7.5 mm x 5 mm DCA package via the two-pass process added approximately 90 secs. to the manufacturing cycle time of a device employing the package.
Encapsulation of the assembly 602 is performed via a one-pass process that includes only a single step of dispensing and heating. A dispensing tool 700 of FIG. 7 dispenses a continuous, uniform bead of epoxy 112 to a keep-out area 702 of the substrate 110. The dispensing tool 700, which may be an automated dispensing machine, is calibrated to dispense an amount of the epoxy 112 sufficient to encapsulate the package 108. The amount of the epoxy 112 is dependent on the size of the gap 604. In the illustrated embodiment, the dispensing tool 700 dispenses approximately 15 mg of the epoxy 112, which is a single part epoxy, such as that manufactured and sold by Dexter-Hysol as part number FP4510, or other suitable thermoset polymer. The keep-out area 702 is devoid of electrical components and is adjacent to, and completely circumscribes, the attachment site 201. The keep-out area 702 is sized to accept the amount of the epoxy 112 needed to encapsulate the package 108. In the illustrated embodiment, the keep-out area 702 has a width W of approximately 1.3 mm.
After the epoxy 112 is dispensed, the assembly 602 is heated to about 80 "C. During heating, the viscosity of the epoxy 112 is reduced and the epoxy 112 becomes a free-flowing liquid that is drawn into the gap 604 from all sides of the package 108 by capillary action, as depicted by arrows 800 of FIG. 8. As the epoxy 112 travels inward, air and other gases in the gap 604 are concurrently vented out via the vent hole arrangement 116, as depicted by arrows 802. The venting action of the vent hole arrangement 116 reduces resistance to capillary flow of the epoxy 112 and prevents entrapment of air or other gases in the epoxy 112. As previously stated, the vent holes 212, 213, and 214 are sized to prevent passage of the epoxy 112. Encapsulation is complete when the epoxy completely fills the gap 604, as shown in FIG. 9. In the illustrated embodiment, the one-pass process of dispensing and heating adds only about 30 secs. to the manufacturing cycle time of the device 101 of FIG.
1. As such, encapsulation via the one-pass process is accomplished in one-third of the time required for the two-pass process.
As stated, for encapsulation to be reliable, the gap 604 must be completely filled with the epoxy 112, as shown in FIG. 9. To ensure a complete fill, the vent hole arrangement 116 must employ more than one vent hole. Vent hole arrangements employing a single vent hole are disadvantageous. During encapsulation, extraneous solder mask or other foreign matter present in the gap can be picked up and carried on the front of the epoxy 112 as it flows inward. If such matter reaches the vent hole arrangement prior to the epoxy 112 filling the gap, obstruction of one or more vent holes can occur and venting can be halted. In a vent hole arrangement employing a single vent hole, such obstruction can result in an incomplete fill.
Furthermore, the epoxy 112, itself, can cause an incomplete fill of the gap 604 in a single vent hole arrangement. During encapsulation, the epoxy 112 flows inward from each side of the attachment site at a non-uniform rate and is unlikely to simultaneously converge at the center 206 of the attachment site 201. In an arrangement employing a single vent hole located at an exact center of an attachment site, the single vent hole may become blocked by the epoxy before the epoxy converges and completely fills the gap. Once epoxy fills a vent hole, air or other gases can not escape. When encapsulating a rectangular package whose adjacent sides have different edge-to-center distances, such as the package 108 in the illustrated embodiment, a single vent hole arrangement is disadvantageous because it is susceptible to obstruction by epoxy for this reason.
After encapsulation, the epoxy 112 is cured by heating the assembly 602 to about 150 "C for a period of approximately 1800 secs.
Curing solidifies the epoxy 112 into an epoxy fillet 900, shown in FIG. 9.
The epoxy fillet 900 extends just below a top edge of, and a distance Df outward from, the package 108. In the illustrated embodiment, the distance Df is approximately 1.3 mm. The resulting structure is the substrate assembly 106 of FIG. 1 suitable for use in the device 101.
In an alternate embodiment shown in FIG. 10, "back to back" packages can be encapsulated using the one-pass process. During assembly, the substrate 110 is inverted and a second package 1000 is mounted to the surface 113 directly opposite to the package 108. The second package 1000 is mounted to the substrate 110 in the same manner previously described with respect to the package 108 so as to form assembly 1002. A second gap 1004 resides between the surface 113 and the second component 1000. The epoxy 112 is dispensed around the package 108 on the surface 111 of the substrate 110 in a quantity sufficient to encapsulate the packages 108 and 1000. In the illustrated embodiment, approximately 30 mg to approximately 40 mg of the epoxy 112 is dispensed to encapsulate the assembly 1002. Upon heating, capillary action draws the epoxy 112 into the gap 604, down through the vent hole arrangement 116 in the substrate 110, and into the second gap 1004, as depicted by arrows 1006. Capillary action drives the epoxy 112 outward from the vent hole arrangement 116 along the surface 113, to fill the second gap 1004. Surface tension draws the epoxy 112 upward on the edges of the second package 1000 forming the desired epoxy fillet upon curing. To ensure passage of the epoxy 112, the vent hole arrangement 116 employs vent holes 1012, 1013, and 1014 (of which only vent holes 1013 and 1014 are shown) with diameters that are larger than those of the vent holes 213 - 215 of FIG. 4. In the illustrated embodiment of FIG. 10, each of the vent holes 1012 - 1014 have a diameter of approximately 0.6 mm to approximately 0.8 mm.
As previously stated, the vent hole arrangement 116 must employ more than a single vent hole. An alternate embodiment of a vent hole arrangement 1100 is shown in FIG. 11. The alternate vent hole arrangement 1100 is located in proximity to the center 206 of the attachment site 201. The alternate vent hole arrangement 1100 employs five vent holes 1101, 1102, 1103, 1104, and 1105 extending through the substrate 110. The vent holes 1101 - 1105 must be sized to permit passage of air, but prevent passage of epoxy. In the illustrated embodiment, each of the vent holes 1101 - 1105 has a diameter D' of approximately 0.3 mm to 0.4 mm. The vent holes 1101 - 1105 are arranged such that a center axis 1106 of vent hole 1101 is located at the center 206 of the attachment site 201 and center axes 1107, 1108, 1109, and 1110 of vent holes 1102, 1103, 1104, and 1105, respectively, form corners of a rectangle 1112 shown in dotted line. Each of vent holes 1102 - 1105 must be sufficiently close to the center 206 to ensure complete epoxy encapsulation and prevent voiding. In the illustrated embodiment, a distance, Dco', from the center 206 to the axes 1107 1110 is approximately 0.7 mm to approximately 0.9 mm and a distance,
Doo', between the axes 1102 - 1105 is approximately 1.0 mm to approximately 1.3 mm.
Thus, it can be seen that a package, such as a DCA package, can be encapsulated with epoxy via a one-pass process. Two or more vent holes extending through the substrate beneath the center of the package allows the epoxy to quickly and completely fill the gap between the package and the substrate. Although illustrated for use in the manufacture of a cellular radiotelephone, one skilled in the art will recognize that the one-pass encapsulation process can be used to reduce the manufacturing cycle time of any device employing one or more encapsulated packages. Such devices include, but are not limited to, portable computers, camcorders, cordless telephones, two-way radios, personal digital assistants, and the like.
What is claimed is:
Claims (10)
- Claims 1. An assembly comprising: a substrate having a first surface and a second surface; an attachment site carried on the first surface; a component package having an interface to mate to the attachment site; a predetermined amount of epoxy encapsulating the component package; and a plurality of vent holes extending between the first and second surfaces of the substrate, the plurality of vent holes located about a center of the attachment site beneath the component package, the plurality of vent holes arranged to permit quick and complete encapsulation of the component package by the epoxy.
- 2. An assembly according to claim 1 wherein the interface includes a plurality of contacts having a predetermined length and the attachment site includes a plurality of pads, the plurality of contacts and pads creating a gap between the component package and the substrate, the gap being no greater than approximately 1.3 mm.
- 3. An assembly according to claim 1 wherein each of the plurality of vent holes are equidistant from the center of the attachment site.
- 4. An assembly according to claim 1 wherein the plurality of vent holes are arranged in an equilateral triangle, each of the plurality of vent holes positioned at a vertex of the equilateral triangle.
- 5. An assembly according to claim 4 wherein a center axis to center axis distance between each of the plurality of vent holes is no greater than approximately 0.9 mm.
- 6. An assembly according to claim 1 wherein each of the plurality of vent holes has a diameter no less than approximately 0.3 mm and no greater than approximately 0.4 mm.
- 7. An assembly according to claim 1 wherein the plurality of vent holes comprise five vent holes, one of the five vent holes positioned at the center of the attachment site, the other of the five vent holes arranged in a rectangle thereabout, each of the other of the five vent holes positioned at a corner of the rectangle and substantially equidistant from the one of the five vent holes.
- 8. An assembly according to claim 1 wherein a distance from the center of the attachment site to a center axis of the other of the five vent holes is no greater than approximately 0.9 mm.
- 9. An assembly according to claim 1 further comprising: a second component package attached to the second surface of the substrate directly opposite the component package, a second predetermined amount of epoxy encapsulating the second component package, and wherein the plurality of vent holes are sized to permit passage of epoxy.
- 10. A method of assembly comprising the steps of: providing a substrate having an attachment site and a plurality of vent holes, the plurality of vent holes arranged about a center of the attachment site and extending through the substrate; attaching a component package to the substrate by mating an interface of the component package and the attachment site, the component package and the substrate spaced apart by the interface and the attachment site to create a gap therebetween; completely surrounding the component package with an epoxy placed on the substrate adjacent thereto; and heating the epoxy to form a free-flowing liquid, whereupon the liquid is drawn into the gap, the plurality of vent holes exhausting air from the gap to ensure quick and complete encapsulation of the component package.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US77128696A | 1996-12-20 | 1996-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9723413D0 GB9723413D0 (en) | 1998-01-07 |
GB2320612A true GB2320612A (en) | 1998-06-24 |
Family
ID=25091330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9723413A Withdrawn GB2320612A (en) | 1996-12-20 | 1997-11-06 | Encapsulating a component mounted on a substrate |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPH10190200A (en) |
KR (1) | KR19980064449A (en) |
CN (1) | CN1195962A (en) |
BR (1) | BR9706047A (en) |
FI (1) | FI974564A (en) |
GB (1) | GB2320612A (en) |
SE (1) | SE9704751L (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2504343A (en) * | 2012-07-27 | 2014-01-29 | Ibm | Manufacturing an semiconductor chip underfill using air vent |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5021349B2 (en) * | 2007-03-27 | 2012-09-05 | 小島プレス工業株式会社 | Circuit board for vehicle-mounted antenna |
CN115377021B (en) * | 2022-08-29 | 2024-08-02 | 北京超材信息科技有限公司 | Electronic device module packaging structure and manufacturing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0345760A2 (en) * | 1988-06-08 | 1989-12-13 | STMicroelectronics S.r.l. | Semiconductor device in plastic case with means of anchoring between chip-bearing slice and plastic body |
US4942452A (en) * | 1987-02-25 | 1990-07-17 | Hitachi, Ltd. | Lead frame and semiconductor device |
-
1997
- 1997-11-06 GB GB9723413A patent/GB2320612A/en not_active Withdrawn
- 1997-11-28 BR BR9706047A patent/BR9706047A/en not_active IP Right Cessation
- 1997-12-10 JP JP9361917A patent/JPH10190200A/en active Pending
- 1997-12-18 CN CN97108720A patent/CN1195962A/en active Pending
- 1997-12-18 FI FI974564A patent/FI974564A/en unknown
- 1997-12-19 SE SE9704751A patent/SE9704751L/en not_active Application Discontinuation
- 1997-12-20 KR KR1019970071342A patent/KR19980064449A/en active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4942452A (en) * | 1987-02-25 | 1990-07-17 | Hitachi, Ltd. | Lead frame and semiconductor device |
EP0345760A2 (en) * | 1988-06-08 | 1989-12-13 | STMicroelectronics S.r.l. | Semiconductor device in plastic case with means of anchoring between chip-bearing slice and plastic body |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2504343A (en) * | 2012-07-27 | 2014-01-29 | Ibm | Manufacturing an semiconductor chip underfill using air vent |
US8907503B2 (en) | 2012-07-27 | 2014-12-09 | International Business Machines Corporation | Manufacturing an underfill in a semiconductor chip package |
Also Published As
Publication number | Publication date |
---|---|
FI974564A0 (en) | 1997-12-18 |
MX9709039A (en) | 1998-06-28 |
JPH10190200A (en) | 1998-07-21 |
BR9706047A (en) | 1999-08-03 |
CN1195962A (en) | 1998-10-14 |
KR19980064449A (en) | 1998-10-07 |
SE9704751D0 (en) | 1997-12-19 |
GB9723413D0 (en) | 1998-01-07 |
FI974564A (en) | 1998-06-21 |
SE9704751L (en) | 1998-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0915505B1 (en) | Semiconductor device package, manufacturing method thereof and circuit board therefor | |
US5120678A (en) | Electrical component package comprising polymer-reinforced solder bump interconnection | |
US5872051A (en) | Process for transferring material to semiconductor chip conductive pads using a transfer substrate | |
US5477419A (en) | Method and apparatus for electrically connecting an electronic part to a circuit board | |
US5435732A (en) | Flexible circuit member | |
TWI534915B (en) | Bump-on-lead flip chip interconnection | |
US7125789B2 (en) | Composite metal column for mounting semiconductor device | |
US6060775A (en) | Semiconductor device | |
JPH0410240B2 (en) | ||
US20020089836A1 (en) | Injection molded underfill package and method of assembly | |
GB2320612A (en) | Encapsulating a component mounted on a substrate | |
US20030205799A1 (en) | Method and device for assembly of ball grid array packages | |
AU653945B2 (en) | Attaching integrated circuits to circuit boards | |
EP0263221A1 (en) | Method of forming solder bumps on metal contact pads of a substrate | |
EP4387403A1 (en) | Soldering a surface mount device to an application board | |
JP2000151086A (en) | Printed circuit unit and its manufacture | |
US20240090130A1 (en) | Leadframe mounting with lead insertion for lead wall bonding | |
US20170213785A1 (en) | Method of forming solder bumps on solid state module including printed cirucuit board | |
MXPA97009039A (en) | Substrate that uses an appropriate installation of ventilation holes to encapsulate a package of electrical components mounted on it and met | |
KR100221654B1 (en) | Method for manufacturing metal bump used screen printing | |
KR20030095036A (en) | Solder bump interconnection method of flip chip package | |
KR100481424B1 (en) | Method for manufacturing chip scale package | |
JP2002043466A (en) | Ball grid array package | |
CN117637696A (en) | Micro-system-level packaging base of ceramic device and use mode thereof | |
JPH03209753A (en) | Electronic parts |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |