GB2300778A - Multistandard video tape player for selectively generating clock signals corresponding to video standards - Google Patents
Multistandard video tape player for selectively generating clock signals corresponding to video standards Download PDFInfo
- Publication number
- GB2300778A GB2300778A GB9609556A GB9609556A GB2300778A GB 2300778 A GB2300778 A GB 2300778A GB 9609556 A GB9609556 A GB 9609556A GB 9609556 A GB9609556 A GB 9609556A GB 2300778 A GB2300778 A GB 2300778A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- video
- clock signal
- servo circuit
- standard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/02—Analogue recording or reproducing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/7921—Processing of colour television signals in connection with recording for more than one processing mode
- H04N9/7925—Processing of colour television signals in connection with recording for more than one processing mode for more than one standard
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Television Signal Processing For Recording (AREA)
- Synchronizing For Television (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
A multistandard video tape player includes a first oscillator for generating a first frequency clock signal corresponding to a first video standard, a second oscillator for generating a second frequency clock signal corresponding to a first video standard, a servo circuit 15 for performing a reproduction operation with respect to a video tape based on an input clock signal, and outputting a control pulse signal reproduced from a control track on the video tape, an on-screen-display (OSD) processor 13 for detecting a sync signal from one of an externally input video signal and a reproduced video signal, and generating an OSD signal for a video signal from which a sync signal is detected and an OSD signal from which a sync signal is not detected, based on an input clock signal, a controller 27 for generating a first control signal (CTL1) according to a video standard which is set for a video signal output from the video tape player and generating a second control signal (CTL2) in response to the sync signal detected in the OSD processor 13 and the control pulse signal output from the servo circuit 15, and a selective output portion 29 for selectively supplying one of the first frequency clock signal and the second frequency signal to the servo circuit 15 in response to the first control signal, and selectively supplying the first frequency clock signal and the second frequency signal to the OSD processor 13 and the servo circuit 15 in response to the first and second control signals. Thus, a display unit having no multistandard function can stably operate.
Description
MULTI8TANDARD VIDEO TAPE PLAYER FOR
8ELECTIVELY GENERATING CLOCK 8IGNAL8
CORRESPONDING TO VIDEO STANDARDS The present invention relates to a multistandard video tape player, and more particularly, to a multistandard video tape player for selectively supplying clock signals corresponding to various video standards to corresponding blocks.
The multistandard video tape player can process a video signal received from an external source or a video signal reproduced from a video tape so as to be adapted for a display unit such as a television set having a video standard different from that of the video signal.
Referring to Figure 1, an existing full-colour multistandard video tape player having an on-screendisplay (OSD) function will be described below.
In Figure 1, a video signal processor 10 processes an external video signal input via an input end 5 and a video signal supplied from a servo circuit 15, using reference clock signals CLK1 and CLK2 output from an oscillator 11 having an oscillation frequency of 3.58MHz and an oscillator 12 having an oscillation frequency of 4.43MHz.
The first reference clock signal CLK1 generated by the oscillator 11 is supplied to the OSD processor 13 and the servo circuit 15 via a resistor Ril and a transistor TR1, and the second reference clock signal CLK2 generated by the oscillator 12 is supplied to the OSD processor 13 and the servo circuit 15 via a resistor R12 and a transistor
TR2. Here, the transistors TR1 and TR2 are designed so that the output of the transistor TR2 is not supplied to the OSD processor 13 and the servo circuit 15 when the transistor TR1 operates.
The OSD processor 13 detects a vertical sync signal
V-SYNC from a video signal supplied from the video signal processor 10 and the detected vertical sync signal V-SYNC is supplied to a microprocessor 17. The servo circuit 15 supplies the video signal reproduced from a video tape (not shown) to the video signal processor 10. The servo circuit 15 also down-counts a control pulse signal supplied from a control track on the video tape and outputs the down-counted result CTL C/D to the microprocessor 17. The microprocessor 17 determines a video standard of the reproduced video signal based on the down-counted result CTL CID in case of a play mode. In case of a stop mode, the microprocessor 17 determines a video standard of the video signal based on the vertical sync signal V-SYNC output from the OSD processor 13.When a video signal is determined as an NTSC standard, the microprocessor 17 outputs a high level signal to a transistor TR3, while when a video signal is determined as a PAL standard, the microprocessor 17 outputs a low level signal to a transistor TR3. If the transistor TR1 is turned on by the high level signal of the transistor TR3, the first reference clock signal CLK1 having the frequency of 3.58MHz output from the oscillator 11 is supplied to the OSD processor 13 and the servo circuit 15. Here, the output signal of the transistor TR2 is not supplied to the
OSD processor 13 and the servo circuit 15. Meanwhile, if the transistor TR1 is turned off by the low level signal of the transistor TR3, the second reference clock signal
CLK2 having the frequency of 4.43MHz output from the oscillator 12 is supplied to the OSD processor 13 and the servo circuit 15.The OSD processor 13 generates an OSD signal for a video signal output from the video signal processor 10 based on an input reference clock signal.
These reference clock signals of the Figure 1 apparatus are summarized in the table shown in Figure 3A.
When there is no video signal supplied from the video signal processor 10, the OSD processor 13 generates an OSD signal for displaying a blue scene on a screen based on an input reference clock signal. The video signal into which an OSD signal is inserted by the OSD processor 13 is supplied to a display (not shown) such as a television set. The servo circuit 15 performs a reproduction operation according to the second reference clock signal
CLK2 and supplies a reproduced video signal to the video signal processor 10.
As described above, the Figure 1 video tape player determines a reference clock signal supplied to the OSD processor 13 and the servo circuit 15 according to the down-counted result CTL CID output from the servo circuit 15 and the vertical sync signal V-SYNC. Therefore, when the Figure 1 video tape player supplies the NTSC standard reproduction video signal or the NTSC standard external video signal to a display having the PAL standard, or supplies the PAL standard reproduction video signal or the
PAL standard external video signal to a display having the
NTSC standard, a display which does not have a signal processing function for multistandard cannot display a blue scene according to an OSD signal supplied from the
Figure 1 apparatus since the OSD processor 13 uses a reference clock signal determined by the vertical sync signal V-SYNC of the input video signal. Further, in case of an external video signal and a reproduction video signal respectively having different video standards, the transistor TR3 having a transient characteristic causes a switching delay if the Figure 1 video tape player is changed from an external video signal output mode to a reproduction operation mode or vice versa. In this case, the OSD processor 13 and the servo circuit 15 does not receive a reference clock signal at a time when the reference clock signal is requested for a corresponding video standard.The sync collapse occurs between the OSD processor 13 and the servo circuit 15.
Therefore, with a view to solving or reducing the above problems, it is an aim of preferred embodiments of the present invention to provide a multistandard video tape player for selectively generating respective reference clock signals which are needed in an OSD processor and a servo circuit.
According to a first aspect of the present invention, there is provided a multistandard video tape player comprising:
a first oscillator for generating a first frequency clock signal corresponding to a first video standard;
a second oscillator for generating a second frequency clock signal corresponding to a first video standard;
a servo circuit for performing a reproduction operation with respect to a video tape based on an input clock signal, and outputting a control pulse signal reproduced from a control track on the video tape;
an on-screen-display (OSD) processor for detecting a sync signal from one of an externally input video signal and a reproduced video signal, and generating an OSD signal for a video signal from which a sync signal is detected and an OSD signal from which a sync signal is not detected, based on an input clock signal;;
a controller for generating a first control signal according to a video standard which is set for a video signal output from the video tape player and generating a second control signal in response to the sync signal detected in the OSD processor and the control pulse signal output from the servo circuit; and
selective output means for selectively supplying one of the first frequency clock signal and the second frequency signal to the servo circuit in response to the first control signal, and selectively supplying the first frequency clock signal and the second frequency signal to the OSD processor and the servo circuit in response to the first and second control signals.
Preferably, said first video standard is an NTSC standard and said second video standard is one of PAL,
SECAM and MESECAM standards.
Preferably, said controller generates the second control signal for supplying the second frequency clock signal to said OSD processor when the video tape player is in a stop mode and said set video standard represents the second video standard.
Said controller preferably generates the second control signal for supplying the first frequency clock signal to said OSD processor when the video tape player is in a stop mode and said set video standard represents the first video standard.
Preferably, said controller generates the first control signal for supplying the first frequency clock signal to said OSD processor and the second control signal for supplying the second frequency clock signal to said servo circuit when the video tape player is in a play mode and said set video standard represents the second video standard, and when the control pulse signal output from said servo circuit matches the first video standard.
Said controller preferably generates the first control signal for supplying the second frequency clock signal to said OSD processor and the second control signal for supplying the first frequency clock signal to said servo circuit when the video tape player is in a play mode and said set video standard represents the first video standard, and when the control pulse signal output from said servo circuit matches the second video standard.
For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:
Figure 1 is a block diagram showing part of a conventional video cassette recorder (VCR) for selectively generating reference clock signals;
Figure 2 is a block diagram showing part of a VCR according to a preferred embodiment of the present invention;
Figure 3A shows a table for explaining a supply of reference clock signals in the conventional VCR; and
Figure 3B shows a table for explaining a supply of reference clock signals according to a preferred embodiment of the present invention.
A preferred embodiment of the present invention will be described below in more detail with reference to the accompanying drawings
The Figure 2 apparatus according to a preferred embodiment of the present invention shows a full colour video tape player, in which blocks having the same functions as those of the corresponding blocks of Figure 1 are assigned with the same reference numerals as those of Figure 1. The signal output from the video signal processor 10 is supplied to the OSD processor 13. The OSD processor 13 detects a vertical sync signal V-SYNC from the video signal output from the video signal processor 10 and supplies the detected vertical sync signal V-SYNC to a controller 27.The servo circuit 15 performs a reproduction operation with respect to a video tape based on an input clock signal and down-counts a control pulse signal reproduced from a control track on the video tape.
A controller 27 determines a video standard of the video signal input to the OSD processor 13 based on a frequency of the vertical sync signal V-SYNC of the OSD processor 13 when the Figure 2 apparatus is set into a stop mode. The controller 27 determines a video standard of the reproduced video signal based on a down-counted control pulse signal CTL C/D of the servo circuit 15 when the
Figure 2 apparatus is set into a play mode. The controller 27 generates a first control signal CTL1 according to a video processing mode representing all standards of the external video signal or the reproduced video signal and the externally output video signal in the video tape player and generating a second control signal
CTL2 based on the signal output from the OSD processor 13 or the servo circuit 15.
A selective output portion 29 receives reference clock signals from oscillators 11 and 12, and supplies the received reference clock signals according to the control signals CTL1 and CTL2 of the controller 29 to the OSD processor 13 or the servo circuit 15. The selective output portion 29 includes transistors 22 and 25 whose bases are connected to the oscillator 11 via a resistor
R11 and transistors 21 and 24 whose bases are connected to the oscillator 12 via a resistor R12. The emitters of the transistors 21 and 22 are connected to a clock signal input port of the OSD processor 13 and grounded via a resistor R3. The collector of the transistor 22 is connected to the emitter of the transistor 23. The base of the transistor 23 receives the first control signal
CTL1 of the controller 27. The power supply Vcc is applied to the collectors of the transistors 21 and 23.
The resistors R1 and R2 are for supplying the reference clock signal of the oscillator 11 to the OSD processor 13 when the first control signal CTL1 is high. The resistor
R1 is connected between the power supply Vcc and the base of the transistor 22 and the resistor R2 is connected between the base of the transistor 22 and the ground.
When the first control signal CTL1 is low, the reference clock signal of the oscillator 12 is supplied to the OSD processor 13 via the transistor 21. The emitters of the transistors 24 and 25 are connected to the clock signal input port of the servo circuit 15 and are grounded via a resistor R6. The collector of the transistor 25 is connected to the emitter of the transistor 26. The base of the transistor 26 receives the second control signal
CTL2 of the controller 29. The power supply Vcc is applied to the collectors of the transistors 24 and 26.
The resistors R4 and R5 are for supplying the reference clock signal of the oscillator 11 to the servo circuit 15 when the second control signal CTL2 is high. The resistor
R4 is connected between the power supply Vcc and the base of the transistor 25 and the resistor R5 is connected between the base of the transistor 25 and the ground.
When the second control signal CTL2 is low, the reference clock signal of the oscillator 12 is supplied to the servo circuit 15 via the transistor 24.
The oscillator 11 generates a reference clock signal of the colour subcarrier frequency of 3.58MHz according to the NTSC standard, and the oscillator 12 generates a reference clock signal of the colour subcarrier frequency of 4.43MHz according to the PAL standard. These oscillators 11 and 12 maintain the oscillation states during the operation of the Figure 2 apparatus.
When the Figure 2 apparatus operates at a stop mode or an external input mode, the video signal processor 10 processes a video signal received via a tuner (not shown).
The OSD processor 13 detects a vertical sync signal V-SYNC from the video signal output from the video signal processor 10, and supplies the detected vertical sync signal V-SYNC to the controller 27. When an "output video standard" set for an output video signal is one of PAL,
SECAM and MESECAM standards, and the vertical sync signal
V-SYNC of the OSD processor 13 has a frequency of 60Hz according to the NTSC standard, that is, when the output video standard is a video processing mode set as an NTSC 4.43MHz shown in Figure 3B, the controller 27 generates a first control signal CTL1 having a low state and a second control signal CTL2 having a high state. The transistor 23 of the selective output portion 29 is turned off by the first control signal CTL1 of the low state. The reference clock signal of the oscillator 12 is supplied to the OSD processor 13 via the transistor 21.Since the transistor 26 is turned on by the second control signal CTL2, the reference clock signal of the oscillator 11 is supplied to the servo circuit 15 via the transistor 25. Meanwhile, when a set output video standard is one of PAL, SECAM and
MESECAM standards, and the vertical sync signal V-SYNC of the OSD processor 13 has a frequency of 50Hz according to the PAL standard, the controller 27 generates a first control signal CTL1 having a high state and a second control signal CTL2 having a low state. In this case, the reference clock signal of the oscillator 11 is supplied to the OSD processor 13 via the transistor 22, and the reference clock signal of the oscillator 12 is supplied to the servo circuit 15 via the transistor 24.
When the Figure 2 apparatus operates at a play mode, the servo circuit 15 outputs a video signal recorded on a video tape (not shown) to the video signal processor 10, down-counts a control pulse signal recorded on a control track in the video tape and supplies the down-counted result CTL CID to the controller 27. When a set "output video standard" is one of PAL, SECAM and MESECAM standards, and the down-counted result CTL C/D of the servo circuit 15 represents that the video signal of the
NTSC standard is reproduced, that is, when the output video standard is a video processing mode set as an NTSC
PB ON PAL TV shown in Figure 3B, the controller 27 generates a first control signal CTL1 having a low state and a second control signal CTL2 having a high state.
Therefore, the reference clock signal of the oscillator 11 is supplied to the servo circuit 15, and the reference clock signal of the oscillator 12 is supplied to the OSD processor 13. Meanwhile, when a set output video standard is one of PAL, SECAM and MESECAM standards, and the down counted result CTL C/D of the servo circuit 15 represents that the video signal of the PAL standard is reproduced, the controller 27 generates a first control signal CTL1 having a high state and a second control signal CTL2 having a low state. Therefore, the reference clock signal of the oscillator 11 is supplied to the OSD processor 13 and the reference clock signal of the oscillator 12 is supplied to the servo circuit 15.
Besides, when the Figure 2 apparatus supplies an external video signal or a reproduced video signal of the
NTSC standard to a display unit of the NTSC standard, and supplies an external video signal or a reproduced video signal of the PAL standard to a display unit of the PAL standard, frequencies of the reference clock signals which are supplied to the OSD processor 13 and the servo circuit 15 are shown in Figure 3B. Since all the contents shown in Figure 3B are apparent to a person skilled in the art who understands well the operation of the Figure 2 apparatus, the detailed description thereof will be omitted.
When there is neither external video signal nor reproduced video signal, the controller 27 cannot determine a video standard based on a signal received from the OSD processor 13 and the servo circuit 15. In this case, the controller 27 outputs a first control signal
CTL1 according to a set output video standard. For example, when a set output video standard is the NTSC standard, the controller 27 outputs a first control signal
CTL1 of a high state. When a set output video standard is in one of the PAL, SECAM and MESECAM standards, the controller 27 outputs a first control signal CTL1 of a low state. Therefore, the OSD processor 13 outputs an OSD signal appropriate for a set output video standard, that is, and OSD signal for a blue scene.
As described above, embodiments of the present invention can supply a proper reference clock signal which is determined by video standards of an external video signal and a reproduced video signal and a video standard of a video signal output from a video tape player to an
OSD processor and a servo circuit. Accordingly, a display unit having no function for a multistandard can stably operate.
While only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (7)
1. A multistandard video tape player comprising:
a first oscillator for generating a first frequency clock signal corresponding to a first video standard;
a second oscillator for generating a second frequency clock signal corresponding to a second video standard;
a servo circuit for performing a reproduction operation with respect to a video tape based on an input clock signal, and outputting a control pulse signal reproduced from a control track on the video tape;
an on-screen-display (OSD) processor for detecting a sync signal from one of an externally input video signal and a reproduced video signal, and generating an OSD signal for a video signal from which a sync signal is detected and an OSD signal from which a sync signal is not detected, based on an input clock signal;;
a controller for generating a first control signal according to a video standard which is set for a video signal output from said video tape player and generating a second control signal in response to the sync signal detected in said OSD processor and the control pulse signal output from said servo circuit; and
selective output means for selectively supplying one of the first frequency clock signal and the second frequency signal to said servo circuit in response to the first control signal, and selectively supplying the first frequency clock signal and the second frequency signal to said OSD processor and said servo circuit in response to the first and second control signals.
2. The multistandard video tape player according to claim 1, wherein said first video standard is an NTSC standard and said second video standard is one of PAL,
SECAM and MESECAM standards.
3. The multistandard video tape player according to claim 1 or 2, wherein said controller generates the second control signal for supplying the second frequency clock signal to said OSD processor when the video tape player is in a stop mode and said set video standard represents the second video standard.
4. The multistandard video tape player according to claim 1, 2 or 3, wherein said controller generates the second control signal for supplying the first frequency clock signal to said OSD processor when the video tape player is in a stop mode and said set video standard represents the first video standard.
5. The multistandard video tape player according to any of the preceding claims, wherein said controller generates the first control signal for supplying the first frequency clock signal to said OSD processor and the second control signal for supplying the second frequency clock signal to said servo circuit when the video tape player is in a play mode and said set video standard represents the second video standard, and when the control pulse signal output from said servo circuit matches the first video standard.
6. The multistandard video tape player according to any of the preceding claims, wherein said controller generates the first control signal for supplying the second frequency clock signal to said OSD processor and the second control signal for supplying the first frequency clock signal to said servo circuit when the video tape player is in a play mode and said set video standard represents the first video standard, and when the control pulse signal output from said servo circuit matches the second video standard.
7. A multistandard video tape player substantially as herein described with reference to Figures 2 and 3B.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950011170A KR960042655A (en) | 1995-05-08 | 1995-05-08 | Reference Frequency Switching Circuit of Multi Video Cassette Recorder |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9609556D0 GB9609556D0 (en) | 1996-07-10 |
| GB2300778A true GB2300778A (en) | 1996-11-13 |
| GB2300778B GB2300778B (en) | 1997-05-14 |
Family
ID=19413885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9609556A Expired - Fee Related GB2300778B (en) | 1995-05-08 | 1996-05-08 | Multistandard video tape player for selectively generating clock signals corresponding to video standards |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR960042655A (en) |
| CN (1) | CN1077309C (en) |
| GB (1) | GB2300778B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7627228B2 (en) | 2005-03-04 | 2009-12-01 | Sharp Kabushiki Kaisha | Wireless video transmission system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102013211710C5 (en) * | 2013-06-20 | 2016-11-10 | Siemens Aktiengesellschaft | Wind turbine with a plain bearing |
-
1995
- 1995-05-08 KR KR1019950011170A patent/KR960042655A/en not_active Application Discontinuation
-
1996
- 1996-05-08 GB GB9609556A patent/GB2300778B/en not_active Expired - Fee Related
- 1996-05-08 CN CN96110003A patent/CN1077309C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7627228B2 (en) | 2005-03-04 | 2009-12-01 | Sharp Kabushiki Kaisha | Wireless video transmission system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1147667A (en) | 1997-04-16 |
| GB9609556D0 (en) | 1996-07-10 |
| CN1077309C (en) | 2002-01-02 |
| GB2300778B (en) | 1997-05-14 |
| KR960042655A (en) | 1996-12-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090508 |