GB2290908A

GB2290908A - Semiconductor memory device capacitors

Info

Publication number: GB2290908A
Application number: GB9514098A
Authority: GB
Inventors: Dae-Je Chin; Tae-Young Chung; Young-Woo Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-09-07
Filing date: 1992-09-07
Publication date: 1996-01-10
Anticipated expiration: 2012-09-07
Also published as: GB9514098D0; GB9521898D0; GB2293691A; GB2293691B; GB2290908B

Abstract

A storage capacitor has a storage electrode 36 and a dielectric layer 40 formed on the storage electrode, wherein the storage electrode 36 is of polysilicon and includes a plurality of microtrenches and/or microcylinders formed on its surface. Further, the storage electrode 36 with the plurality of microtrenches and/or microcylinders is formed by forming hemispherical grains on a surface of the storage electrode, forming an etching mask layer on side walls of the respective grains, and performing an anisotropic etching by using the etching mask layer as a mask. <IMAGE>

Description

SEMICONDUCTOR MEMORY DEVICES The present invention relates to semiconductor memory devices, and is concerned particularly with capacitors therefor.

A dynamic random access memory (DRAM) typically has a plurality of memory cells each having one transfer transistor and one storage capacitor.

Accordingly, an area occupicd by the DRAM increases with an increase of the density of the memory cells. Since such an increase of the occupation area causes a decrease of the yield, it is required to increase the storage capacitance in a limited small area occupied by the respective storage capacitors, without increase of the occupation area, according to the increase of the density of the memory cells. To meet this requirement, a number of capacitor cell structures have been proposed, such as stacked capacitor cell and trench capacitor cell structures. The stacked capacitor has been widely proposed for the Megabitclass DRAMs, because of the simplicity of the manufacturing process and the high immunity against soft error in comparison with the trench capacitor.One approach to meet the requirement is to increase the surface area of the storage electrode, or to reduce the effective thickness of the capacitor dielectric layer and use good dielectric substances. However, preferred embodiments of the present invention are not dircctcd to dccreasing the effective thickness of the dielectric layer or increasing the permittivity, but to increasing the surface area of the storage electrode.

A known technique which engraves a storage electrode to increase the surface area of the storage electrode is disclosed in "Extended Abstracts of the 21st Conference on Solid State Devices and Materials (SSDM)", 1989, pp.

137-140. This technique has the following steps of depositing polysilicon on selectively oxidized N-type silicon substrate by low pressure chemical vapor deposition (LPCVD), doping the deposited polysilicon by a phosphorus diffusion using POCL3 source, coating a mixture of spin-on-glass (SOG) and resist on the doped polysilicon, baking the mixed film, selectively etching the SOG in a buffered HF solution leaving only the resist particles on the polysilicon, dry-etching the polysilicon using dispersed resist particles as an etching mask, removing the resist particles, and patterning the polysilicon to form a storage electrode. As a result, the surface area of the storage electrode is increased by using the resist particles left on the polysilicon surface as an etching mask to form an engraved storage electrode.Further, the increase of the surface area of the storage electrode is achieved by controlling the size of the resist particles and the time for etching the polysilicon. The size of the resist particles can be controllcd by the mixing ratio of the resist and SOG, and the thickness of the mixture coated on the polysilicon. However, since this technique requires the use of particles with uniform size and control of the coating thickness of the mixture according to the mixing ratio of the resist and the SOG, thcre may be problems in recurrently engraving storage electrodes and increasing the reliability. Further, another problem is that the engraving process must be complicated to increase the surface area.

Another conventional technique for increasing the surface area of a storage electrode is disclosed in IEDM, 1990, pp. 655-656 (or see SSDM, 1990, pp. 873-876 and SSDM, 1990, pp. 869-872), wherein a memory cell has a hemispherical grain storage electrode. This technique uses the fact that during deposition of the polysilicon by LPCVD, the polysilicon has, under a certain condition, a rugged surface having silicon bumps or hemispherical grains thereon. Further, the paper discloses that such a rugged surface occurs actively at a narrow temperature range (5"C) neighboring with a transition temperature of the polysilicon from non-crystalloid to crystalloid and the surface area of the storage electrode is increased to twice that of a conventional polysilicon.Since this technique can be readily controlled by use of existing equipment within the temperature 5"C, the manufacture process is simple and has a reliable recurrence feature. Actually, the surface area of the storage electrode increases only to twice that of the conventional storage electrode. Therefore, it is difficult to apply the technique to a high density memory device such as tens or hundreds of Megabit-class DRAM, because of the limitation of highly increasing the storage capacitance in a limited small area.

It is accordingly an aim of preferred embodiments of the present invention to provide a storage capacitor with high storage capacitance in a limited area.

It is another aim to provide a storage capacitor having an increased surface area of a storage electrode in a limited area.

It is another aim to provide a storage capacitor having increased storage capacitance in a limited small area made with a simple manufacturing process.

It is another aim to provide a storage capacitor having a high reliability and high storage capacitance formed in a limited small area.

It is still another aim to provide a storage capacitor having high storage capacitance and a reliable recurrcnce feature formed in a limited small area.

According to an aspect of the present invention, a capacitor has a first electrode and a dielectric layer formed on the first electrode, wherein the first electrode is of polysilicon and includes a plurality of microtrenches and/or microcylinders formed on a predetermined area thereof.

Further, a semiconductor memory cell according to another part of the present invention includes a transfer transistor and a storage capacitor, wherein the transfer transistor includes source and drain regions and a gate electrode neighboring with the source and drain regions, wherein the storage capacitor includes a first electrode contacting the source region and spaced apart from the gate electrode, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, and wherein the first electrode is of polysilicon and includes a plurality of microtrenches and/or microcylinders formed on a predetermined area thereof.

According to another aspect of the present invention, a method for forming a storage electrode having a plurality of microtrenches and/or microcylinders includes the steps of forming grains on a surface of the storage electrode, forming an etching mask layer on side walls of the respective grains, and performing an anisotropic etching by using the etching mask layer as a mask.

According to another aspect of the present invention, a capacitor has a first electrode formed in a limited area of a substrate, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer, wherein the first electrode includes a plurality of microtrenches and/or microcylinders of the conduction layer, the conduction layer at the bottom portions of the microtrenches and/or microcylinders being in contact with the insulating layer and a thin conduction layer covering the conduction layer at interior and exterior of the microtrenches and/or microcylinders.

According to another aspect of the present invention, a semiconductor memory cell has a transfer transistor and a storage capacitor, wherein the transfer transistor includes source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer neighboring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions, and a first insulating layer covering the first conduction layer, wherein the storage capacitor includes a second conduction layer contacting the drain region and expanding over the first insulating layer, a second insulating layer covering the second conduction layer, a field oxide layer formed on the substrate neighboring with the source region, a first electrode made of a conduction layer contacting the source region, overlapping a predetermined portion of the first conduction layer and expanding over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, wherein the first electrode includes a plurality of microtrcnches and/or microcylinders of the conduction layer, the conduction layer at the bottom portions of the microtrenches and/or microcylinders being in contact with the insulating layer, and a thin conduction layer covering the conduction layer at interior and exterior of the microtrenches and/or microcylinders.

According to another aspect of the present invention, a semiconductor memory cell includes a transfer transistor and a storage capacitor, wherein the transfer transistor includes source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer neighboring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions, and an insulating layer covering the first conduction layer, wherein the storage capacitor includes a field oxide layer formed on the substrate, the field oxide layer neighboring with the source region, a first electrode made of a conduction layer contacting the source region, the first electrode overlapping a predetermined portion of the first conduction layer and expanding over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, wherein the first electrode includes a plurality of microtrenches and/or microcylinders of the conduction layer, the conduction layer at the bottom portions of the microtrenchcs and/or microcylindcrs being in contact with the insulating layer and a thin conduction layer covering the conduction layer at interior and exterior of the microtrenches and/or microcylinders.

According to another aspect of the present invention, a method for forming a storage electrode having a plurality of microtrenches and/or microcylinders includes the steps of flattening a surface of an insulating layer on which the storage electrode is to be formed, forming grains on a surface of the storage electrode, forming an etching mask layer on side walls of the respective grains, performing an anisotropic etching by using the etching mask layer as a mask so as to form screw-hole-like holes passing through the storage electrode to expose the insulating layer therethrough, and forming a thin conduction layer of polysilicon covering interior and exterior of the screw-hole-like holes.

According to another aspect of the present invention, a method for manufacturing a storage capacitor for use in a semiconductor memory device by using a polysilicon layer having a plurality of hemispherical grains, includes the steps of forming an etching mask layer on top surfaces of the hemispherical grains, patterning the polysilicon layer, performing an anisotropic etching by using the etching mask layer as a mask, and removing the etching mask layer to form a storage electrode.

According to another aspect of the present invention, a method for forming a first electrode of storage electrode in a semiconductor memory device includes the steps of forming a polysilicon layer contacting the source region, the polysilicon layer having a plurality of hemispherical grains on the surface thereof and covering the second insulating layer, forming an etching mask layer on top surfaces of the hemispherical grains, patterning the polysilicon layer, performing an anisotropic etching by using the etching mask layer as a mask, and removing the etching mask layer.

Other optional features and various aspects of the invention are disclosed in the following description and appended claims.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 shows a plan view of one example of a DRAM memory cell according to the present invention; Figure 2 shows a cross-sectional view taken along a line 2-2 of Figure 1; Figures 3A through 3C show an exemplary diagram for showing a process of manufacturing the structure of Figure 2; Figure 4A is an enlarged diagram for illustrating an embodiment of a rounded portion (100) of Figure 3B; Figures 4B and 4C are exemplary diagrams for showing a process of manufacturing a storage capacitor in a case where hemispherical grains are formed continuously as shown in Figure 4A;; Figure SA is an enlarged diagram for illustrating another embodiment of the rounded portion (100) of Figure 3B; Figures SB and SC are exemplary diagrams for showing a process of manufacturing a storage capacitor in case where the hemispherical grains are separated at a distance from each other as shown in Figure 5A; Figure 6 shows a plan view of another embodiment of a DRAM memory cell according to the present invention; Figure 7 shows a cross-sectional view taken along a line 3-3 of Figure 6; Figures sA through 8D show exemplary diagrams for showing a process of manufacturing a structure of Figure 7; Figure 9A is an enlarged diagram for illustrating an embodiment of a rounded portion (500) of Figure 8C; ; Figures 9B and 9C are exemplary diagrams for showing a process of manufacturing a storage capacitor in a case where hemispherical grains are formed continuously as shown in Figure 9A; Figure 10A is an enlarged diagram for illustrating another embodiment of the rounded portion (500) of Figure 8C; Figures 10B and lOC are exemplary diagrams for showing a process of manufacturing a storage capacitor in a case where hemispherical grains are separated at a distance from each other as shown in Figure 10A; Figures 11A through 11D are other exemplary diagrams for showing a process of manufacturing the structure of Figure 7; Figure 12A is an enlarged diagram for illustrating a rounded portion as shown in Figure 11B;; Figures 12B through 121 are exemplary diagrams for showing a process of manufacturing a storage capacitor in a case where the hemispherical grains are separated at a distance from each other as shown in Figure 12A; Figures 13A through 13F are diagrams for showing another example of a process of manufacturing a storage capacitor according to the present invention; Figures 14A through 14H are diagrams for showing another example of a process of manufacturing a storage capacitor according to the present invention; and Figure 15 is a plan view for illustrating etching patterns used in Figure 14C.

In the figurcs, like reference numerals denote like or corresponding parts.

Referring to Figures 1 and 2, a field oxide layer 12 for defining a memory cell region is formed on a P-type semiconductor substrate 10. The semiconductor substrate 10 may be of P-type well region. A transfer transistor which includes an N-type source region 16 adjacent to the field oxide layer 12, an N-type drain region 20 separated from the source region 16 through an N-channel region 18, and a gate electrode 24 disposed on a gate oxide layer 22 over the channel region 18 and adjacent to the source and drain regions 16 and 20, is formed in an active region 14 positioned on a main surface of the semiconductor substrate 10 surrounded with the field oxide layer 12. The gate electrode 24 is connected to a word line 26.A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent active region is formed on the field oxide layer 12. The gate electrode 24 is isolated from the word line 28 by an insulating oxide layer 30. The insulating oxide layer 30 has an opening 32 for exposing a part of the source region 16.

A first electrode of a storage electrode 36 contacts the source region 16 at a source contact region 34 through the opening 32, and defines the storage capacitor region 38, expanding over the adjacent gate electrode 24 and the word line 28. An upper portion of the storage electrode 36 has a number of microtrenches or microcylinders so as to increase the surface area of the storage electrode, as will be described in detail in the following.

A dielectric layer 40 is formed on the surface of the storage electrode 36 and a plate electrode layer 42 is formed over the dielectric layer 40.

Accordingly, the storage capacitor 44 includes the storage electrode 36, the dielectric layer 40 and the plate electrode layer 42. A protection layer 46 is formed on a second electrode of the plate electrode 42 and an exposed portion of the insulating oxide layer 30. The protection layer 46 has an opening 50 which is adjacent to the drain region 20 of the transfer transistor and which is to expose a highly doped N+ region 48 expanding over the surface of the semiconductor substrate 10. A bit line 52 made of a conductive material contacts the N+ region 48 at a bit line contact region 54 through the opening 50 and crosses with the word lines 26, 28, expanding over the protection layer 46 in a band shape. A second protection layer (not depicted) is covered on the bit line 52.

The DRAM memory cell as described above, has one transistor and one capacitor. The capacitor is a stacked capacitor which has a storage electrode having multiple microtrenches in an area 0.4 x 1.2m2 that the storage capacitor region 38 occupics. However, it should be noted that the present invention is not restrictive to expanding the area of the storage electrode.

Referring to Figures 3A-3C, 4A-4C, and SA-SC, a process of manufacturing the inventive DRAM memory cell will be described in detail.

However, since the operation of the DRAM memory cell itself is well known in the art, a detailcd description thereof will not be made.

Referring to Figure 3A, shown is a pair of transfer transistors formed on the semiconductor substrate 10. Though well known, a process of manufacturing the transistors will be described in brief for reference.

The substrate 10 is a P-type well with a concentration 4~5x10'6atom.s/cm3 formed on a P-type silicon wafer having a crystal surface < 1, 0, 0 > and a concentration lxlO'5atoms/cm3. The field oxide layer 12 of 3000A thickness is formed on a part of the substrate 10 to define the active region 14. Then, the gate oxide layer 22 of isoA thickness is formed on the semiconductor substrate in the active region 14 by conventional dry-O2oxidization, and a phosphorus doped polysilicon layer is coated on the semiconductor substrate 10 to form the gate electrode 24. After coating the polysilicon, the gate electrode 24 or the word line 26, and the word line 28 are patterned by a conventional photoetching.By the patterning process, the gate oxide layer other than a lower portion of the gate electrode 24 and the word lines 26, 28 is removed to expose the substrate 10 disposed in the active region 14. Then, phosphorous ions of 1.6x10l3ions/cm' dose are implanted under 60KeV to form the source and drain regions 16, 20. After the phosphorous ion-implantation, an SiO, insulating layer 30 of 2700to thickness is uniformly deposited by LPCVD at about 820"C to insulate the gate electrode 24, the word lines 26, 28 and the ion-implanted source and drain regions 16, 20.

Referring to Figure 3B, after forming the insulating oxide layer 30, the opening 32 for exposing a part of the surface of the source region 16 is formed through the insulating oxide layer 30 by conventional photoetching.

After removing the photoresist used for forming the opening 32, a polysilicon layer 56 of 2500A thickness, having a number of hemispherical grains on its surface, is formed on the substrate in contact with the source contact region 34 through the opening 32. The polysilicon having such a surface structure may be deposited by LPCVD using helium buffered SiH4(20%) at 5500C under atmospheric pressure of 1 bar (see IEEE Trans, on Electron Devices, Vol. ED-36, No.2, pp. 351-353, 1989, or SSDM, pp. 873-876, 1990).

Alternatively, the polysilicon layer 56 may be manufactured by depositing polysilicon of about 1000A thick at a conventional temperature condition (over 600"C) for the polysilicon deposition and then forming, on the polysilicon surface, polysilicon of about l500 thickness having a number of hemispherical grains on its surface. It is preferable that the diameter or the height of the hemispherical grains be about 0.07~0.15,um. After forming the polysilicon layer 56, arsenic ions of 3xlO15ions/cm2 dose are implanted under 100KeV to dope the polysilicon layer 56.Though the polysilicon layer 56 can be doped with phosphorous impuritics, it is, however, preferable to dope the arsenic impurities so as to form a good microtrench structure on the polysilicon layer 56. Then, a mask layer 58 of SiO, of 300A thickness is deposited on the doped polysilicon layer t6 by a conventional chemical vapor deposition (CVD). A dielectric substance with a high permittivity such as Si3N4 or Tea205 can be used for the mask layer 58. However, in consideration of the etching process for forming the microtrenches, it is preferable to use a dielectric substance having a high selectivity of the polysilicon/dielectric substance.After deposition of the mask layer 58, a patterning process is performed to define the storage capacitor area 38 by the conventional photoetching. As a result, the patterned polysilicon layer 56 having microtrenches as shown in Figure 3B and the patterned mask layer 58 of SiO2 are formed.

In the following, an etching process for forming the microtrenches will be described in detail with reference to Figures 4A-4C and SA-SC. Figures 4A and 5A are enlarged diagrams for illustrating different embodiments of a rounded portion 100 described in Figure 3B, respectively.

Figure 5A shows the arrangement of the grains in case where the distance S between the hemispherical grains is more than twice the thickness X of the mask layer 58 of SiOo (i.e., Sr2X), and Figure 4A shows the arrangement of the grains in case where the distance S is zero.

In practice, if the polysilicon layer 56 is deposited by LPCVD at a temperature range in which the polysilicon layer 56 transits from noncrystalloid to crystalloid, the distance S between the grains becomes the mixed states of the case S=O and the case S > 2X. Namely, it should be noted that the arrangements of the grains shown in Figures 4A and 5A can be made at the same time.

Refcrring to Figure 4A, a SiO2 etchback process used for forming a side wall used in the convcntional LDD MOSFET (Lightly Doped Drain MOSFET) manufacture is performed on the polysilicon oxide layer 5s so as to etch-stop at the thickness X (=300A). When the SiO, layer 58 is deposited, since the SiO2 layer is deposited thicker in the valleys between the polysilicon grains, the result of the etchback process is such that the etching mask 62 remains and the upper portions 66 of the grains are exposed as shown in Figure 4B. Then, an anisotropic etching, in which selectivity of the polysilicon/SiO2 is 40, is performed to make O.Srm-thick grooves.Such an etching is performed by using Model No. "Rainbow 4400" by LAM Co. at power 200watt under an atmospheric pressure of 350 millibar with use of a mixed gas of HBR(hydro bromide):Clr = 4OSCCM:i2OSCCM. As a result, 11 -shaped grooves having cylindrical intcr walls are formcd in the polysilicon as shown in Figure 4C and hemispherical portions 64 corresponding to the exposed grains 66 are formed in the bottom surfaces of the grooves, whereby the surface area of the storage electrode 36 is further increased.After forming such microtrenches, a Si3N4 layer of about 70A thickness is formed on the surface of the storage electrode by the conventional CVD, and a dielectric layer 40 of an N-O structure (or an O-N-O structure, if a naturally oxidized SiO, layer is added thereto) of about 20thick SiO, layer obtained by heat-oxidizing the surface of the Si3N4 layer, is coated. Then, a doped polysilicon layer is formed on the dielectric layer 40 by the conventional technique and the doped polysilicon layer is patterned by the conventional photoetching to form the plate electrode 42.

In case of Figures SA through SC, after an etchback of the mask layer 58, an etching mask layer 62 is formed on the side walls of the respective grains 60 as shown in Figure SB, and the upper portions 66 of the grains 60 and the surface portions 68 of the polysilicon layer t6 disposed between the grains 60 are exposed. Thereafter, a submicron-class etching is performed and, as a result, the storage electrode 36 having multiple microcylinders 70 is formed as shown in Figure SC. In this case also, the hemispherical portions 64 corresponding to the shape of the exposed upper portions 66 are formed in the bottom surface of the cylinders 70. However, the bottom surfaces 80 of the exterior of the microcylinders 70 are etched deeper than the hemispherical portions 64.Accordingly, the manufacture of the microtrenches or the microcylinders can be achieved by the sclf-alignment etching process without using the photoresist, thereby simplifying the manufacture process.

In case where the structure of Figure 4A and the structure of Figure 5A are mixed, a number of microcylinders and the poles having a number of microtrenches may be provided, after the anisotropic etching.

Thereafter, the dielectric layer 40 of N-O or O-N-O structure and the plate electrode 42 are formed on the surface of the storage electrode 36 according to a predetermined process.

The process for making the stacked capacitor having the SiO2 etching mask layer 62 disposed on the upper surface of the storage electrode 36 has been described. However, since the etching mask layer 62 can not play the role of the dielectric layer, it is prefcrred to remove the etching mask layer 62.

The SiO2 etching mask layer G2 can be removed in buffered HF solution, after the anisotropic etching process.

Generally, after the anisotropic etching, sharp edges are left at the etched edge portions. The sharp edges can also be made around the portions other than the cdge portions damaged by the anisotropic etching. The existence of those sharp edges prevents the thin dielectric layer 40 covering the storage electrode 36 from being formed rcliably and, further, causes the decrease of the breakdown voltage of the storage capacitor.

A process for rounding the sharp edges can be performed before the dielectric layer 40 is formed and after removing the etching mask layer 62 (in the case of a stacked capacitor without the etching mask layer 62). An SiO2 layer of about ioA thick is formed on the storage electrode 36 by soaking the substrate in a mixed solution of HCL:HrO:HrO = 1:1:6 with a temperature 60 C-80 C. Thereafter, the sharp edges are removed by clearing, with the buffered HF solution, the oxide layer formed during the chemical oxidization process.

The present embodiment of the invention forms a 2500A0-thick polysilicon layer 56 having hemispherical grains and etches the grooves to a depth 2000A. However, it should be noted that the present invention is not limited to such numerical valucs. By increasing the thickness of polysilicon layer 56 and etching more deeply the trenches dependant on the selectivity of the polysilicon/dielectric substance, the surface area of the storage electrode 36 may be further increased.

Referring back to Figure 3C, the above described plate electrode 42 is shown. The next process is a reflow process of covering the protection layer such as BPSG (Boro-Phospho-Silicate Glass) or PSG over the substrate 10 so as to flatten the device. Then, the opening 50 is formed by the conventional technique as shown in Figure 2 and an N+ region 48 is formed through the opening SO. Then, the bit line 52 of aluminum is formed in contact with the N+ region 48.

In the present embodiment of the invention, the bit line 52 overlaps and expands over the transfer transistor and the stacked capacitor 44, and the gate electrode of the transfer transistor is of polysilicon. However, it should be noted that the present invention is not limited to such a structure. Further, the polysilicon forming the first electrode can be replaced with re-crystallized silicon.

Morcovcr, examples of the present invention can be used in forming a groove in a semiconductor substrate and then, forming a stacked capacitor in the groove.

Further, if a storage capacitor having high storage capacitance is required in a limited area on an insulated substrate, the capacitor can be made by forming a storage electrode having multiple microtrenches on the insulated substrate, forming a dielectric layer thereon and forming a plate electrode on the dielectric layer.

The structure of the storage electrode and the process for making same in accordance with the present invention have been described above by way of examples. However, different embodiments can be achieved without departing from the scope of the present invention. For reference, and just by way of further examples, the followings are possible different embodiments according to the present invention.

EXAMPLE 1 Referring to Figures 6 and 7, shown is another embodiment of a DRAM memory cell according to the present invention, wherein a field oxide layer 12 for defining the memory cell region is formed on a P-type semiconductor substrate 10. The semiconductor substrate 10 may be of P-type well region.

A transfer transistor which includes an N-type source region 16 adjacent to the field oxide layer 12, an N-type drain region 20 separated from the source region 16 through an N-channel region 18, a gate oxide layer 22 formed over the channel region 18, and a gate electrode 24 disposed on the gate oxide layer 22 and adjacent to the source and drain regions 16 and 20, is formed in an active region 14 positioned on a main surface of the semiconductor substrate 10 surrounded with the field oxide layer 12. The gate electrode 24 is connected to a word line 26. A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent active region is formed on the field oxide layer 12. The gate electrode 24 is isolated from the word line 28 by a first insulating layer 30.The first insulating layer 30 has an opening 135 through which the drain region 20 of the transfer transistor contacts a bit line 150. An opening 125 is formed in the first insulating layer 30 and a second insulating layer 190 covering the bit line 150. The surface of the second insulating layer 190 is flattened. A storage electrode 200 contacts the source region 16 at a source contact region 18 through the opening 125, and defines the storage capacitor region, expanding over the adjacent gate electrode 24 and the word line 28. An upper portion of the storage electrode 200 has a number of microtrenchcs or microcylinders so as to increase the surface area of the storage electrode, as will be described in detail in the following.

A dielectric layer 40 is formed on the surface of the storage electrode 200 and a plate electrode layer 4(10 is formed over the dielectric layer 40.

Such a DRAM memory cell is an application of a DASH (Diagonal Active Stacked capacitor cell with a Highly-packed storage node) structure in which a bit line is formed under the storage capacitor. The DASH structure is well disclosed in IEDM 1988, pp. 596-599. In a DRAM memory cell having the DASH structure, since an expansion of the storage capacitor in horizontal direction can be designed without limitation of the bit line design rule, it is easy to increase the storage capacitance of the capacitor with a simple process, compared with a DRAM memory cell in which the storage capacitor is formed under the bit line. It is accordingly noted that the storage electrode 200 defining the storage capacitor area can cxpand widely, unless it contacts the storage electrode of a neighboring storage capacitor.

Now, reference will be made to Figures 8A-8D, 9A-9C and 10A-lOC to explain a process of manufacturing the DRAM memory cell of Figure 7.

Referring to Figure sA, described is a process of forming a pair of transfer transistors and the bit line 150. The process prior to forming the bit line 150 is the same as the process described with reference to Figure 3A.

Since the bit line 150 is formed on the first insulating layer 30, it is preferable to flatten the surface of the first insulating layer 30 by using a reflow process such as BPSG. Then, a part of the first insulating layer 30 formed on the drain region -'() is removed by convcntional photoctching to form the opening 135 through which the drain region -'() of the transfer transistor is connected with the bit line 150 of aluminum.

Referring to Figure 8B, after forming the bit line 150, a second insulating layer 190 of BPSG or PSG is coated at a thickness of about 5000 over the substrate and it is reflowed to flatten the surface. The second insulating layer 190 is generally of a silicon oxide, or of a stacked layer of silicon oxide and silicon nitride. In either cases, after the coating of the second insulating layer 190, the surface flattening process should be performed. Alternatively, the flattening process can be achieved by coating a silicon oxide layer on the substrate, coating resist particles thereon and then etching it with a controlled etching ratio of the resist particles and the silicon oxide layer.

Referring to Figure 8C, after completion of forming and flattening the second insulating layer 190, the opening 125 for exposing a part of the surface of the source region 16 is formed through the second insulating layer 190 and the first insulating layer 30 by the conventional photoetching. After the photoresist used for forming the opening 125 is removed, the polysilicon layer 56 of 2500to thickness having hemispherical grains on its surface is formed on the second insulating layer 190, contacting the surface of the source region 16, as described with reference to Figure 3B. After the polysilicon layer 56 is formed, the arsenic ion implantation is performed to dope the polysilicon layer, as described in Figure 3B.Then, a mask layer 250 of SiO, is deposited on the doped polysilicon layer 56 at a thickness of about 300A-500A0 by the conventional CVD. The dielectric substance with a high permittivity such as Si3N4 or Tea,05 can be used for the mask layer 58. However, in consideration of the etching process for forming the microtrenches, it is preferable to use a dielectric substance having a high selectivity of the polysilicon/dielectric substance. After deposition of the mask layer 250, a patterning process is performed to define the storage capacitor area by conventional photoetching.

In the following, an example of a process for forming microtrenches according to the present invention will be described in detail with reference to Figures 9A and lOA, which are enlarged diagrams for illustrating different embodiments of a rounded portion 500 described in Figure 8C, respectively.

Figure 10A shows the arrangement of grains in a case where the distance S between the hemispherical grains is more than twice the thickness X of the mask layer 250 of SiO, (i.e., S22X), and Figure 9A shows the arrangement of the grains in the case where the distance S is zero.

Referring to Figure 9A, an SiO, etchback process used for forming a side wall used in the conventional LDD MOSFET (Lightly Doped Drain MOSFET) manufacture is performed on the polysilicon oxide layer 250 so as to etch-stop at a thickness X (=300An 500 ) of the SiO2 layer 250. This process is the same as the process of Figure 4B. When the SiO2 layer 250 is deposited, since the SiO2 layer is deposited thicker in the valleys between the polysilicon grains 221, the result of the etchback process is such that etching mask 251 remains in the vallcys and the upper portions 222 of the grains 221 are exposed.

Now referring to Figure 9B, an anisotropic etching, in which selectivity of the polysilicon/SiO, is 40, is performed to completely etch out the polysilicon layer 56 of 25nn thickness so as to expose the second insulating layer 190 other than the portion under the etching mask 251. Such an etching is performed by using Model No. "Rainbow 4400" by LAM Co. at power 200watt under an atmospheric pressure of 350 millibar with use of a mixed gas of HBR(hydro-bromidc):C1, = 4()SCCM:120SCCM. As a result, microtrenches 230 having a screw-hole-like structure are formed, passing through the polysilicon layer 56.It should be noted that this embodiment is different from the process of Figure 4C in that the groove's depth of Figure 4C is 0.2m while the holc's depth of this embodiment is 2500 . After the screw-hole-like microtrcnchcs 231) are formed, a doped thin polysilicon layer 240 is deposited uniformly on the interior and exterior of the microtrenches 230 by LPCVD with a deposition rate 202SAimin in the decomposition gas of SiH4 at over 600 C, at which temperature the polysilicon is formed.

Because the cffective thickness of the thin polysilicon layer 240 should be thinner than half the diametcr (0.()7~0.15,um) of the hemispherical grain 221 in order to secure a sufficicnt surface area of the storage capacitor, it is preferable that the thickness of the thin polysilicon layer 240 be 300-700 thick. A patterning process is performed on the thin polysilicon layer 240 formed over the entire surface of the substrate by conventional photoetching so as to define the storage capacitor area and form the storage electrode 200.

As a result, the storage electrode 200 including the polysilicon layer 56 and the thin polysilicon layer 240 has the multiple microtrenches 230.

Now referring to Figure 9C, after the storage electrode 200 is formed, a Si3N4 layer of about 70tri thickness is formed on the surface of the polysilicon layer 240 (or the storage electrode 200) by the conventional CVD, and a dielectric layer 40 of an N-O layer (or an O-N-O layer, if a naturally oxidized SiO, layer is added thereto) of 20thick SiO2 obtained by heatoxidizing the surface of the Si3N4 layer is coated thereon. Then, the polysilicon layer 400 of doped polysilicon is formed on the dielectric layer 40 to complete the manufacture of the storage capacitor shown in Figure 8D.

Figures 10A through lOC show another embodiment of a storage capacitor according to the present invention. In this case, after an etchback of the mask layer 250, an etching mask layer 251 is formed on the side walls 225 of the respective grains 221 as shown in Figure 10A, and the upper portions 222 of the grains 221 and the surface portions 226 of the polysilicon layer 56 disposed between the grains 221 are exposed. Thereafter, a submicron-class etching is performed on the polysilicon layer 56 to expose the second insulating layer 190 and the thin polysilicon layer 240 is deposited over the entire surface of the substrate. Then, the storage electrode 200 is patterned as shown in Figure 10B.Further, the dielectric layer 40 and the plate electrode 400 are consecutively formed on the storage electrode 200.

It may be noted by a person skilled in the art that, even in the case where the distances between the hemispherical grains are not uniform, a storage capacitor can be made by the above process in accordance to the present invention. It should be further noted that an accurate control of the etching depth for forming the microtrenches is not required, because after the polysilicon 56 other than the portions under the etching mask layers 251 is completely removed with a high selectivity of polysilicon/oxide silicon, the thin polysilicon layer 240 for forming the storage electrode 200 is formed.

In the foregoing, it is considered as an example that the storage electrode includes oxide silicon used as an etching mask. However, since the etching mask layer 251 l does not play the role of the dielectric layer, and as it can not increase the surface area of the storage capacitor, it is preferred to remove the etching mask layer 251 by performing anisotropic etching and soaking in a buffered HF solution.

Though the embodiment described with reference to Figure 7 shows a DRAM memory cell having a DASH structure in which the bit line is formed under the storage capacitor, the present invention is not restricted to such a structure. For example, this embodiment can be applied to the DRAM memory cell of Figure 2. In that casc, before the polysilicon layer 56 serving as the storage electrode 36 is deposited, the insulating layer 30 formed under the polysilicon layer 56 should be flattened.

EXAMPLE 2 Another embodiment of the. present invention will now be described hereinbelow with reference to Figures 11A-llD and 12A-121.

First, referring to Figure 11A, the polysilicon layer 56 of 2500A thickness having hemispherical grains on its surface is formed on the second insulating layer 190, contacting the source region 16 through the opening 125 and then, an arsenic ion implantation is performed. Next, with reference to Figure 11B, a SiN layer 330 about 20-500A thick is deposited on the polysilicon layer t6 by the conventional LPCVD, and a SOG (Spin-On-Glass) layer 340 of about 20()0A thick is coated on the SiN layer 330. Since the thickness of the SOG layer 340 is much grcatcr than the height of the hemispherical grain, the rugged surface of the polysilicon layer 56 is fully covered by the SOG layer 340.

Figure 12A shows an enlarged diagram for illustrating the rounded portion of Figure 1 it. In Figure l2B, after the SOG layer 340 is coated and flattened, the SOG layer 340 is etched-back or dry-etched to expose upper portions 331 of the hcmisphcrical grains 221, which surfaces are coated with the SiN layer 330. The exposure of the SiN layer 330 can be accurately controlled by the time and extent of etching. In Figure 12C, the exposed SiN layer 331 is removed by a dry-ctching using the model No. "Rainbow 4400" by LAM Co., or a wet-etching using phosphoric acid (H3PO4).Then, the remaining SOG layer 342 is completely removed, as shown in Figure 12D, by soaking the substrate in BOE (Buffcrcd-Oxide Etchant) solution for about one minute.

Referring to Figure 12E, the upper portions of the hemispherical grains 221 of the exposed polysilicon layer 56 are oxidized to form an oxide layer 231 100-lOOO thick. This oxidization process may be performed by using dry-O2, or soaking the substrate in a mixed solution of HCL:H2O2:H2O=l:l:6 at 60-80 C. At this moment, a thin oxide layer 232 is also formed on the SiN layer 330. However it can be readily removed by soaking the substrate in BOE solution for about 10 seconds. The oxide layer 231 is used as an etching mask in forming the microtrenches. After the oxidation process, the SiN layer 330 remaining on the hemispherical grains 221 and the polysilicon layer 56 is removed by soaking the substrate in H3PO4 solution as shown in Figure 12F.

Referring back to Figure 11C, after forming the etching mask 231 of oxide layer, the polysilicon layer t6 is patterned by conventional photoetching so as to form the storage electrode. It can be therefore appreciated in the above patterning that since the polysilicon layer t6 is formed over the bit line 150, the expansion of the surface area of the storage capacitor can be designed without limitation of the bit line design rule.

Now, referring to Figure 12G, the anisotropic etching, in which selectivity of the polysilicon/SiO2 is 40, is performed on the polysilicon layer 56 in the thickness of 0.2m, by using the etching mask layer 231. Such an etching is performed by using Model No. "Rainbow 4400" by LAM Co. at power 200watt under an atmospheric pressure of 350 millibar with use of a mixed gas of HBR(hydro-bromidc):Cl2 = 40SCCM:120SCCM. As a result, microtrenches 224 having rounded portions corresponding to the shape of the grains in the lower parts are formed as shown in Figure 12G. The bottom areas of the microtrenches 224 have slow slopes.In such a structure, the step coverage characteristics of the dielectric layer formed thereon may be improved, compared with the other structures.

Now, as shown in Figure 12H, the etching mask layer 231 which can not serve as the dielectric layer is removed to complete the manufacture of the storage electrode 201. It is noted that the surface of the storage electrode 201 from which the etching mask layer 231 has been removed is well rounded without sharp portions. Then, a good dielectric layer is coated thereon to prevent an undesirable decrease of the breakdown voltage of the storage capacitor.

Then, a SiN4 layer about 7()A thick is formed on the surface of the storage electrode 2()l by the conventional CVD, and a dielectric layer 40 of an N-O layer (or an O-N-O layer, if a naturally oxidized SiO2 layer is added thereto) of ''O -thick SiO2 obtained by hcat-oxidizing the surface of the Si3N4 layer, is coated thereon. Then, the polysilicon layer 400 of doped polysilicon is formed on the dielectric layer 40 to complete the manufacture of the storage capacitor shown in Figure 121.

Thereafter, a protection layer 46 such as BPSG (Boro-Phospho-Silicate Glass) or PSG is covered over the substrate 10 and a reflow process is performed to flatten the device. As a result, the DRAM memory cell as shown in Figure 11 D is manufactured.

In the above embodiment, the thickness of the polysilicon layer 220 serving as the storage electrode is 2S00A and the depth of the trenches is 2000 . However, it should be noted that the present invention is not restrictive to such numerical values. By increasing the thickness of polysilicon layer 56 and etching more deeply the trenches dependant on the selectivity of the polysilicon/oxide silicon, the surface area of the storage electrode 201 will increase. Of course, all embodiment according to the present invention can be applied for a storage electrode in which the distance between the hemispherical grains is zero.

EXAMPLE 3 Reference will be further made to Figures 13A-13F, 14A-14H and 15 to show another embodiment of the present invention.

First, referring to Figure 13A, a gate electrode 24 and a word line 28 are formed on a semiconductor substrate 10 of a first conduction type, similarly to Figure 3A. Then, a first intcrlaycr insulating layer 600 such as a BPSG or oxide layer is coated on the entire surface of the substrate 10 and the resultant is flattened. A first insulating layer 610 soo-ioooA thick such as a nitride layer and a second insulating layer 620 1000-2000A thick such as an oxide layer are consecutively deposited on the first interlayer insulating layer 600. The first insulating layer 610 of nitride is used as an etch-stop layer in the succeeding process.

Figure 13B shows a process of forming a first contact hole CH1 and a first conduction layer t6 of polysilicon. A photoresist pattern of a desired size is formed on the second insulating layer 620 by the consecutive process of covering the photoresist, and exposing/patterning the photoresist. By using the photoresist pattern, the first and second insulating layer 610 and 620, and the first interlayer insulating layer 60(1 are etched away so as to form the first contact hole CHi which connects the storage electrode used as a first electrode of the storage capacitor with the source region 16 of the transfer transistor.

After the photoresist pattern is removed, a doped polysilicon layer 56 2000-6000A thick having hemispherical grains on its surface is deposited on the entire surface of the substrate 10. In Figure 13B, the grains are connected to adjacent grains, i.c. the distance S between the grains is zero as shown in Figures 4A and 9A. However, the present invention may also be applied to a storage electrode in which the grains are separated at a distance from each other, as shown in the preceding embodiments.

Figure 13C shows a process of forming a pattern of the polysilicon layer and a third insulating layer 630. First, a photoresist pattern of a desired size is formed on the first conduction layer 56 of polysilicon by the consecutive process of covering the photoresist, and cxposing/patterning the photoresist. By using the photoresist pattern, the first conduction layer 56 of polysilicon is etched away so as to form the pattern 56' of the polysilicon layer having hemispherical grains on its surface. Consecutively, the photoresist pattern is removed and the third insulating layer 630 of a 300- 1000t-thick HTO (High Temperature Oxide) layer is deposited over the whole surface of the substrate 1O.

Figure 13D shows a process of etching the third insulating layer 630.

An etchback is performed on the substrate 10 to expose the top portions of the grains of the polysilicon pattern 56'. As a result, the third insulating layer 630 remains between the grains. Further, the remaining third insulating layer 630' exists on the side walls of the polysilicon pattern 56'.

Figure 13E shows a process of forming the storage electrode. By using the remaining third insulating layer 630' as a mask, the polysilicon pattern 56' is etched out to form a storage electrode 202. As a result, the storage electrode 202 is formed which has the microtrenches or microcylinders formed in the areas of the polysilicon pattern 56', on which the remaining third insulating layer 630' is not covered. Further, during the process of etching the storage electrode, the side wall portions of the polysilicon pattern 56' are slope-etched. In this case, the pattern etching of the polysilicon pattern 56' is performed by a mixed gas of Hbr or Cl2 which has a high etchingselectivity of polysilicon/oxi(lc.

Figure 13F shows a process of forming the storage capacitor. After the process of Figure 13E, the remaining third insulating layer 630' used as a mask is removed by wct-ctching, using BOE or buffered HF solution.

Consecutively, the dielectric layer 40 in an O-N-O (oxide-nitride-oxide) or N-O structure is deposited on the entire surface of the exposed storage electrode 202. . Next, a second conduction layer of doped polysilicon is deposited on the dielectric layer 40 and patterned to form the plate electrode 400. As a result, the process of forming a storage capacitor comprised of the storage electrode 202, the dielectric layer 40 and the plate electrode 400 is completed. Then, a bit line is formed by exposing the upper portion of the drain region 2() (not shown). The bit line may be formed prior to forming the first conduction layer for the storage electrode 2()2.

Refercnce will be further made to Figures 14A through 14H to show another embodiment according to the present invention.

The process of Figure 14A is the same as the process of Figure 13A.

In Figure 14B, the first contact hole CH1, the polysilicon layer 56 and the third insulating layer 640 are consecutively formed, as described in Figure 13B. Next, in Figure 14C, a photoresist pattern 700 in a desired size is formed on the third insulating layer 640 by a successive process of covering, exposing and photoctching the photoresist. Then, by using the photoresist pattern as a mask, the third insulating layer 640 and the polysilicon layer 56 are etched out, to form a polysilicon pattern 56a as shown in the drawing.

The third insulating layer 640 is further etched out along the polysilicon pattern 56a by wet-etching using BOE or buffered HF solution, so as to form a third insulating layer pattern 640a. In this case, the etching depth for forming the third insulating layer pattern 640a is about 500-lOOO thick.

Rcfcrcnce will 100W be made to Figure 15 to explain clearly the area A of Figure 14C. The polysilicon layer pattern 56a and the photoresist pattern 700 have the same size. The third insulating layer pattern 640a is smaller in size by a predetermined width than the polysilicon layer pattern 56a along its circumference. In Figure 14D, the photoresist pattern 700 of Figure 14C is removed and the polysilicon layer pattern 56a is etched out by using the third insulating layer pattern 640a as a mask, so as to form hummocks B along the circumference of the polysilicon layer pattern 56a.In Figure 14E, the third insulating layer pattern 640a is removed, and a fourth insulating layer 650 of 500-lOOO -thick HTO film is deposited over the entire surface of the substrate 10. A process of removing the third insulating layer pattern prior to deposition of the fourth insulating layer is negligible. Next, in Figure 14F, an etchback is performed on the substrate 10 on which the fourth insulating layer 650 is formed, so as to have the fourth insulating layer pattern 650a remain between the grains and on the side walls of the polysilicon layer pattern 56a.

It should be noted that a spacer 651 comprised of the remaining fourth insulating layer is formed on the hummocks B. The spacer 651 is used in forming microcylinders along the side walls of the storage electrode in the later process. Now, in Figure 14G, the polysilicon layer pattern 56a is etched out by about 4000W thick, by using the fourth insulating layer pattern 650a as a mask, so as to complete the structure of the storage electrode 204 having the multiple microtrenchcs and/or microcylinders. Thereafter, in Figure 14H, the remaining fourth insulating layer pattern 650a and the spacer 651 are removed.

Then, the dielectric layer 40 is coated over the storage electrode 204 and doped polysilicon is deposited on the dielectric layer 40 to form the plate electrode 400. Thereby, the process of making the storage capacitor is completed.

Though various structures of a storage capacitor according to the present invention have been shown and described in the forgoing, it will be apparent to a person skillcd in the art that various modifications are available without departing from the scope of the present invention. For example, the present invention can be used in forming a groove in a semiconductor substrate and then, forming a stacked capacitor in the groove. Further, in case where a capacitor with high storage capacitance in a limited area of an insulated substrate is required, the requirement can be met by forming a storage electrode having multiple microtrcnches forming a dielectric layer thereon, and forming a plate electrode on the dielectric layer.

As can be appreciated from the foregoing description, examples of a storage capacitor according to the present invention may have a storage electrode having increased surface area in a limited area, so that the storage capacitance increases. Further, since the microtrenches and/or microcylinders with a good uniformity are formed, high reliability of the capacitor may be achieved. It is further noted that processes according to the present invention may be comparatively simple.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papcrs and documents are incorporated herein by reference.

All of the features disclosed in this spccification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combincd in any combination, except combinations where at Icast some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, cquivalcnt or similar purposc, unless cxprcssly stated otherwise.

Thus, unless cxprcssly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar feature.

The invention is not rcstrictcd to the details of the foregoing embodiment(s). The invention cxtcnds to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A method of forming a storage electrode having a plurality of microtrenches and/or microcylinders, comprising the steps of: forming grains on a surface of the storage electrode; forming an etching mask layer on side walls of the respective grains; and performing an anisotropic etching by using the etching mask layer as a mask.

2. A method as claimed in claim 1, further comprising the step of removing sharp edges of said microtrenches and/or microcylinders after said step for performing anisotropic etching.

3. A method of forming a storage electrode having a plurality of microtrenches and/or microcylinders, comprising the steps of: flattening a surface of an insulating layer on which said storage electrode is to be formed; forming grains on a surface of the storage electrode; forming an etching mask layer on side walls of the respective grains; performing an anisotropic etching by using the etching mask layer as a mask so as to form screw-hole-like holes passing through said storage electrode to expose the insulating layer therethrough; and forming a thin conduction layer of polysilicon covering interior and exterior portions of said screw-hole-like holes.

4. A method of manufacturing a storage capacitor for use in a semiconductor memory device by using a polysilicon layer having a plurality of hemispherical grains, comprising the steps of: forming an etching mask layer on top surfaces of said hemispherical grains; patterning said polysilicon layer; performing an anisotropic etching by using the etching mask layer as a mask; and removing said etching mask layer to form a storage electrode.

5. A method as claimed in claim 4, further comprising a step of oxidizing top surfaces of said hemispherical grains to form said etching mask layer thereon.

6. A method as claimed in claim 4 or 5, further comprising a step of subjecting the polysilicon layer between said hemispherical grains to the anisotropic etching.

7. A method as claimed in claim 4, 5 or 6, further comprising the steps of: forming a dielectric layer on said storage electrode; and forming a plate electrode on said dielectric layer.

8. A method of forming a first electrode of a storage electrode in a semiconductor memory device including: a transfer transistor comprising: source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type; a first conduction layer neighboring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions; and a first insulating layer covering said first conduction layer, for insulating said first conduction layer; and a storage capacitor comprising: a second conduction layer contacting said drain region, said second conduction layer expanding over said first insulating layer; a second insulating layer covering said second conduction layer, for insulating said second conduction layer; a field oxide layer formed on the substrate, said field oxide layer neighboring with said source region; said first electrode made of a conduction layer contacting said source region, said first electrode overlapping a predetermined portion of said first conduction layer and expanding over said field oxide layer; a dielectric layer covering said first electrode; and a second electrode covering said dielectric layer, said method comprising the steps of: forming a polysilicon layer contacting said source region, said polysilicon layer having a plurality of hemispherical grains on the surface thereof and covering said second insulating layer; forming an etching mask layer on top surfaces of said hemispherical grains; patterning said polysilicon layer; performing an anisotropic etching by using the etching mask layer as a mask; and removing said etching mask layer.

9. A method as claimed in claim 8, further comprising a step of oxidizing top surfaces of said hemispherical grains to form said etching mask layer thereon.

10. A method as claimed in claim 8 or 9, further comprising a step of subjecting the polysilicon layer between said hemispherical grains to the anisotropic etching.

11. A method of manufacturing a storage electrode of a storage capacitor over a flattened insulating layer formed on a semiconductor substrate having an active region, comprising the steps of: forming on said insulating layer a polysilicon layer contacting said active region, said polysilicon layer having a plurality of hemispherical grains each spaced apart at a predetermined distance from each other; forming a SiN layer on said polysilicon layer; coating a flattened Spin-On-Glass layer on said SiN layer; subjecting said Spin-On-Glass to an etch-back so as to expose said SiN layer formed on top surfaces of the hemispherical grains; removing the exposed SiN layer to expose top surfaces of said hemispherical grains; oxidizing the top surfaces of the hemispherical grains to form an etching mask layer thereon;; subjecting said polysilicon layer to an anisotropic etching by using the etching mask layer as a mask; and removing said etching mask layer.

12. A method as claimed in claim 11, further comprising a step of subjecting the polysilicon layer between said hemispherical grains to anisotropic etching.

13. A method of manufacturing a storage electrode of a storage capacitor over a flattened insulating layer formed on a semiconductor substrate having an active region, comprising the steps of: forming a first interlayer insulating layer, and first and second insulating layers consecutively on the flattened insulating layer; forming a contact hole through said intcrlayer insulating layer and said first and second insulating layers so as to expose said active region therethrough; forming on said second insulating layer a polysilicon layer contacting said active region, said polysilicon layer having a plurality of hemispherical grains; subjecting said polysilicon layer to an etching to form a pattern;; forming on the scmiconductor substrate an insulating layer covering the polysilicon layer and subjecting said insulating layer to an etch-back, so as to form an etching mask pattern with remaining parts of said insulating layer; subjecting the polysilicon layer to an etching by using said etching mask pattern as a mask.

14. A method as claimed in claim 13, wherein said first insulating layer is of nitride.

15. A method as claimed in claim 13 or 14, further comprising a step of forming said etching mask pattern between the hemispherical grains and on side walls of said pattern of the polysilicon layer.

16. A method of manufacturing a storage electrode of a storage capacitor over a flattened insulating layer formed on a semiconductor substrate having an active region, comprising the steps of: forming a first intcrlaycr insulating layer, and first and second insulating layers consecutively on the flattened insulating layer; forming a contact hole through said intcrlaycr insulating layer and said first and second insulating layers so as to expose said active region therethrough; forming on said second insulating layer a polysilicon layer contacting said active region, said polysilicon layer having a plurality of hemispherical grains; forming a third insulating layer on said polysilicon layer; subjecting said polysilicon layer and said third insulating layer to an etching, so as to form a pattcrn; ; subjecting predetermined parts of the pattcnicd third insulating layer to an etching so as to form a first etching mask pattern made of the third insulating layer; subjecting the polysilicon layer to an etching by a predetermined thickness by using said first mask pattern as a mask; depositing a fourth insulating layer on the ovcrall surface of the semiconductor substrate; subjecting said fourth insulating layer to an etch-back, so as to form a second etching mask pattern with remaining parts of said fourth insulating layer; and subjecting the polysilicon layer to an etching by using said second etching mask pattern as a mask.

17. A method as claimed in claim 16, wherein said first etching mask pattern is smaller in size by a predetermined width than the patterned polysilicon layer along its circumference.

18. A method as claimed in claim 16 or 17, wherein said second etching mask pattern is formed bctwccll the hemispherical grains and on side walls of the patterned polysilicon layer.

19. A method as claimed in any preceding claim, substantially as hereinbefore described with reference to the accompanying drawings.