GB2293691A

GB2293691A - Semiconductor memory devices

Info

Publication number: GB2293691A
Application number: GB9521898A
Authority: GB
Inventors: Dae-Je Chin; Tae-Young Chung; Young-Woo Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-09-07
Filing date: 1992-09-07
Publication date: 1996-04-03
Anticipated expiration: 2012-09-07
Also published as: GB9514098D0; GB2290908A; GB9521898D0; GB2290908B; GB2293691B

Description

SEMICONDUCTOR MEMORY DEVICES 2293691 The present invention relates to

semiconductor memory devices, and is concerned particularly with capacitors therefor.

A dynamic random access memory (DRAM) typically has a plurality of memory cells each having one transfer transistor and one storage capacitor.

Accordingly, an area occupied by the DRAM increases with an increase of the density of the memory cells. Since such an increase of the occupation area causes a decrease of the yield, it is required to increase the storage capacitance in a limited small area occupied by the respective storage capacitors, without increase of the occupation area, according to the increase of the density of the memory cells. To meet this requirement, a number of capacitor cell structures have been proposed, such as stacked capacitor cell and trench capacitor cell structures. The stacked capacitor has been widely proposed for the Megabit class DRAMs, because of the simplicity of the manufacturing process and the high immunity against soft error in comparison with the trench capacitor. One approach to meet the requirement is to increase the surface area of the storage electrode, or to reduce the effective thickness of the capacitor dielectric layer and use good dielectric substances. However, preferred embodiments of the present invention are not directed to decreasing the effective thickness of the dielectric layer or increasing the permittivity, but to increasing the surface area of the storage electrode.

2.5 A known technique which engraves a storage electrode to increase the surface area of the storage electrode is disclosed in "Extended Abstracts of the 21st Conference on Solid State Devices and Materials (SSDM)", 1989, pp.

- 1? - 137-140. This technique has the following steps of depositing polysilicon on selectively oxidized N-type silicon substrate by low pressure chemical vapor deposition (LPCVD), doping the deposited polysilicon by a phosphorus diffusion using POCL3 source, coating a mixture of spin-on-glass (SOG) and resist on the doped polysilicon, baking the mixed film, selectively etching the SOG in a buffered HF solution leaving only the resist particles on the polysilicon, dry-etching the polysilicon using dispersed resist particles as an etching mask, removing the resist particles, and patterning the polysilicon to form a storage electrode. As a result, the surface area of the storage electrode is increased by using the resist particles left on the polysilicon surface as an etching mask to form an engraved storage electrode. Further, the increase of the surface area of the storage electrode is achieved by controlling the size of the resist particles and the time for etching the polysilicon. The size of the resist particles can be controlled by the mixing ratio of the resist and SOG, and the thickness of the mixture coated on the polysilicon. However, since this technique requires the use of particles with uniform size and control of the coating thickness of the mixture according to the mixing ratio of the resist and the SOG, there may be problems in recurrently engraving storage electrodes and increasing the reliability. Further, another problem is that the engraving process must be complicated to increase the surface area.

Another conventional technique for increasing the surface area of a storage electrode is disclosed in IEDM, 1990, pp. 655-656 (or see SSDIW, 1990, pp. 873-876 and SSDM, 1990, pp. 869-872), wherein a memory cell has a hemispherical grain storage electrode. This technique uses the fact that during deposition of the polysilicon by LPCVD, the polysilicon has, under a certain condition, a rugged surface having silicon bumps or hemispherical grains thereon. Further, the paper discloses that such a rugged surface occurs actively at a narrow temperature range (5'C) neighboring with a transition temperature of the polysilicon from non-crystalloid to crystalloid and the surface area of the storage electrode is increased to twice that of a conventional polysilicon. Since this technique can be readily controlled by use of existing equipment within the temperature 5C, the manufacture process is simple and has a reliable recurrence feature. Actually, the surface area of the storage electrode increases only to twice that of the conventional storage electrode. Therefore, it is difficult to apply the technique to a high density memory device such as tens or hundreds of Megabit-class DRAM, because of the limitation of highly increasing the storage capacitance in a limited small area.

It is accordingly an aim of preferred embodiments of the present invention to provide a storage capacitor with high storage capacitance in a limited area.

It is another aim to provide a storage capacitor having an increased surface area of a storage electrode in a limited area.

It is another aim to provide a storage capacitor having increased storage capacitance in a limited small area made with a simple manufacturing process.

It is another aim to provide a storage capacitor having a high reliability and high storage capacitance formed in a limited small area.

It is still another aim to provide a storage capacitor having hgh storage capacitance and a reliable recurrence feature formed in a limited small area.

According to one aspect of the present invention, there is provided a capacitor having a first electrode made of a conduction layer formed on a limited area of a substrate, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer wherein said first electrode comprises a plurality of non-concentric microcylinders formed on a predetermined area of said conduction layer.

Preferably, said conduction layer is a polysilicon layer.

According to a second aspect of the present invention, there is provided a semiconductor memory cell comprising: a transfer transistor comprising: source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type; a first conduction layer neighbouring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions; and a first insulating layer covering said first conduction layer, for insulating said first conduction layer: and a storage capacitor comprising: a field oxide layer formed on the substrate, said field oxide layer neighbouring with said source region; a first electrode contacting said source region, said first electrode overlapping a predetermined portion of said first conduction layer and expanding over said field oxide layer; a dielectric layer covering said first electrode; and a second electrode covering said dielectric layer, wherein a plurality of non-concentric microcylinders are formed on said first electrode.

The said microcylinders may be hemispherical at bottom portions.

A third aspect of the present invention provides a capacitor formed in a limited area of a substrate, having a first electrode made of a conduction layer formed on an insulating layer, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer, wherein said first electrode comprises a plurality of non- concentric microcylinders of the conduction layer extending to the surface of said insulating layer, and a thin conduction layer covers said conduction layer at interior and exterior portions of said microcylinders.

The said microcylinders may have a screw-hole-like structure passing through the conduction layer.

Another aspect of the present invention provides a semiconductor memory cell comprising:

a transfer transistor comprising:

source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type; a first conduction layer neighbouring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions; and a first insulating layer covering said first conduction layer, for insulating said first conduction layer: and a storage capacitor comprising:

a second conduction layer contacting said drain region, said second conduction layer expanding over said first insulating layer; a second insulating layer covering said second conduction layer, for insulating said second conduction layer; a field oxide layer formed on the substrate, said field oxide layer neighbouring with said source region; a first electrode made of another conduction layer contacting said source region, said first electrode overlapping a predetermined portion of said first conduction layer and expanding over said field oxide layer; a dielectric layer covering said first electrode; and a second electrode covering said dielectric layer: wherein said first electrode comprises:

a plurality of non-concentric microcylinders of the said other conduction layer extending to the surface of said insulating layer; and a thin conduction layer covering said other conduction layer at interior and exterior portions of said microcylinders.

In an application of the present invention, the said first and second conduction layers may respectively be a word line and a bit line.

The said second insulating layer may have a flattened surface.

The present invention also extends to a semiconductor memory device 1 including a capacitor or a semiconductor memory cell as described above as being in accordance with the present invention.

Other optional features and various aspects of the invention are disclosed in the following description and appended claims.

This application is a divisional of parent application no. 9218898.6, as is application no. 9514098.4. The parent application claims the capacitors described herein which have a thin conduction layer over the first electrode, coating the inside and outside of the microcylinders and/or microtrenches. The related divisional application claims the methods described herein of manufacturing a storage electrode.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

Figure 1 shows a plan view of one example of a DRAM memory cell according to the present invention; Figure 2 shows a cross-sectional view taken along a line 2-2 of Figure 1; Figures 3A through 3C show an exemplary diagram for showing a process of manufacturing the structure of Figure '21; Figure 4A is an enlarged diagram for illustrating an embodiment of a rounded portion (100) of Figure 3B; Figures 4B and 4C are exemplary diagrams for showing a process of manufacturing a storage capacitor which does not fall within the claims of this application, but in respect of which protection is sought by the parent and associated divisional application, in a case where hemispherical grains are formed continuously as shown in Figure 4A; Figure 5A is an enlarged diagram for illustrating an embodiment according to the invention of the rounded portion (100) of Figure 313; Figures 513 and 5C are exemplary diagrams for showing a process of manufacturing a storage capacitor according to the present invention in case where the hemispherical grains are separated at a distance from each other as shown in Figure 5A; Figure 6 shows a plan view of another embodiment of a DRAM memory cell according to the present invention; Figure 7 shows a cross-sectional view taken along a line 3-3 of Figure 6; Figures 8A through 81) show exemplary diagrams for showing a process of manufacturing a structure of Figure 7; Figure 9A is an enlarged diagram for illustrating an embodiment of a rounded portion (500) of Figure 8C which does not fall within the claims of this application, but in respect of which protection is sought by the parent and associated divisional application; Figures 913 and 9C are exemplary diagrams for showing a process of manufacturing a storage capacitor which again does not fall within the claims of this application, but in respect of which protection is sought by the parent and associated divisional application, in a case where hemispherical grains are formed continuously as shown in Figure 9A; Figure 10A is an enlarged diagram for illustrating an embodiment of the rounded portion (500) of Figure 8C according to the present invention; and parts.

Figures 10B and 1OC are exemplary diagrams for showing ayrocess of manufacturing a storage capacitor according to the present invention in a case where hemispherical grains are separated at a distance from each other as shown in Figure 10A.

In the figures, like reference numerals denote like or corresponding Referring to Figures I and 2, a field oxide layer 12 for defining a memory cell region is formed on a P-type semiconductor substrate 10. The semiconductor substrate 10 may be of P-type well region. A transfer transistor which includes an N-type source region 16 adjacent to the field oxide layer 12, an N-type drain region 20 separated from the source region 16 through an N-channel region 18, and a gate electrode 24 disposed on a gate oxide layer 22 over the channel region 18 and adjacent to the source and drain regions 16 and -70, is formed in an active region 14 positioned on a main surface of the semiconductor substrate 10 surrounded with the field oxide layer 12. The gate electrode 24 is connected to a word line 26. A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent 20 active region is formed on the field oxide layer 12. The gate electrode 24 is isolated from the word line 28 by an insulating oxide layer 30. The insulating oxide layer 30 has an opening 32 for exposing a part of the source region 16. A first electrode of a storage electrode 36 contacts the source region 16 at a source contact region 34 through the opening 32, and defines the storage 4.5 capacitor region 38, expanding over the adjacent gate electrode 2-4 and the word line 28. An upper portion of the storage electrode 36 has a number of microtrenches or microcylinders so as to increase the surface area of the storage electrode, as will be described in detail in the following.

A dielectric layer 40 is formed on the surface of the storage electrode 36 and a plate electrode layer 42 is formed over the dielectric layer 40.

Accordingly, the storage capacitor 44 includes the storage electrode 36, the dielectric layer 40 and the plate electrode layer 42. A protection layer 46 is formed on a second electrode of the plate electrode 42 and an exposed portion of the insulating oxide layer 30. The protection layer 46 has an opening 50 which is adjacent to the drain region 20 of the transfer transistor and which is to expose a highly doped N' region 48 expanding over the surface of the semiconductor substrate 10. A bit line 52 made of a conductive material contacts the N' region 48 at a bit line contact region 54 through the opening and crosses with the word lines 26, 28, expanding over the protection layer 46 in a band shape. A second protection layer (not depicted) is covered on the bit line 52.

The DRAM memory cell as described above, has one transistor and one capacitor. The capacitor is a stacked capacitor which has a storage electrode having multiple microtrenches in an area 0.4 x 1.2,uM2 that the storage capacitor region 38 occupies. However, it should be noted that the present invention is not restricted to expanding the area of the storage electrode.

Referring to Figures 3A-3C, 4A-4C, and 5A-5C, a process of manufacturing the DRAM memory cell will be described in detail. However, since the operation of the DRAM memory cell itself is well known in the art, a detailed description thereof will not be made.

Referring to Figure 3A, shown is a pair of transfer transistors formed on the semiconductor substrate 10. Though well known, a process of manufacturing the transistors will be described in brief for reference.

The substrate 10 is a P-type well with a concentration 4-5x 1016 atoMS/CM3 formed on a P-type silicon wafer having a crystal surface <1, 0, O> and a concentration lxlO"atoms/cm'. The field oxide layer 12 of

0 3000A thickness is formed on a part of the substrate 10 to define the active 0 region 14. Then, the gate oxide layer 22 of 150A thickness is formed on the semiconductor substrate in the active region 14 by conventional dry-02 oxidization, and a phosphorus doped polysilicon layer is coated on the semiconductor substrate 10 to form the gate electrode 24. After coating the polysilicon, the gate electrode -14 or the word line 26, and the word line 28 are patterned by a conventional photoetching. By the patterning process, the gate oxide layer other than a lower portion of the gate electrode 24 and the word lines 26, 28 is removed to expose the substrate 10 disposed in the active region 14. Then, phosphorous ions of 1.6x 1013 ionS/CM2 dose are implanted under 60KeV to form the source and drain regions 16, 20. After the phosphorous ion-implantation, an S'02 insulating layer 30 of 2700A thickness is uniformly deposited by LPCVD at about 820'C to insulate the gate electrode 24, the word lines 26, 28 and the ion-implanted source and drain regions 16, 20.

Referring to Figure 3B, after forming the insulating oxide layer 30, the opening 32 for exposing a part of the surface of the source region 16 is formed through the insulating oxide layer 30 by conventional photoetching.

After removing the photoresist used for forming the opening 32, a polysilicon 12 layer 56 of 2500A thickness, having a number of hemispherical grains on its surface, is formed on the substrate in contact with the source contact region 34 through the opening 32. The polysilicon having such a surface structure may be deposited by LPCVD using helium buffered SiH4(20%) at 5500C under atmospheric pressure of I bar (see IEEE Trans, on Electron Devices, Vol. ED-36, No.2, pp. 351-353, 1989, or SSDM, pp. 873-876, 1990).

Alternatively, the polysilicon layer 56 may be manufactured by depositing polysilicon of about 1000A thick at a conventional temperature condition (over 600C) for the polysilicon deposition and then forming, on the polysilicon surface, polysilicon of about 1500A thickness having a number of hemispherical grains on its surface. It is preferable that the diameter or the height of the hemispherical grains be about 0.07-0.15,um. After forming the polysilicon layer 56, arsenic ions of 3x 1015ionS/CM2 dose are implanted under 10OKeV to dope the polysilicon layer 56. Though the polysilicon layer 56 can be doped with phosphorous impurities, it is, however, preferable to dope the arsenic impurities so as to form a good microtrench structure on the 0 polysilicon layer 56. Then, a mask layer 58 of S'02 of 300A thickness is deposited on the doped polysilicon layer 56 by a conventional chemical vapor deposition (CVD). A dielectric substance with a high permittivity such as -)0 S'3N, or Ta-,05 can be used for the mask layer 58. However, in consideration of the etching process for forming the microtrenches, it is preferable to use a dielectric substance having a high selectivity of the polysilicon/di electric substance. After deposition of the mask layer 58, a patterning process is performed to define the storage capacitor area 38 by the conventional photoetching. As a result, the patterned polysilicon layer 56 having microtrenches as shown in Figure 3B and the patterned mask layer 58 of SiO, are formed.

In the following, an etching process for forming microtrenches will be described in detail with reference to Figures 4A-4C and 5A-5C. Figures 4A and 5A are enlarged diagrams for illustrating one way (outside the scope of the present invention) of forming a rounded portion 100 described in Figure 5 3B.

Figure 5A shows the arrangement of the grains in case where the distance S between the hemispherical grains is more than twice the thickness X of the mask layer 58 of S'02 (i.e., Sz_.2X), and Figure 4A shows the arrangement of the grains in case where the distance S is zero.

In practice, if the polysilicon layer 56 is deposited by LPCVD at a temperature range in which the polysilicon layer 56 transits from noncrystalloid to crystalloid, the distance S between the grains becomes the mixed states of the case S=0 and the case S>2X. Namely, it should be noted that the arrangements of the grains shown in Figures 4A and 5A can be made at the same time.

Referring to Figure 4A, a SiO2etchback process used for forming a side -)o wall used in the conventional I-DD MOSFET (Lightly Doped Drain MOSFET) manufacture is performed on the polysilicon oxide layer 58 so as to etchstop 0 at the thickness X (=300A). When the SiO, layer 58 is deposited, since the S'02 layer is deposited thicker in the valleys between the polysilicon grains, the result of the etchback process is such that the etching mask 62 remains and the upper portions 66 of the grains are exposed as shown in Figure 4B. Then, an anisotropic etching, in which selectivity of the polysilicon/SiO, is 40, is performed to make 0.2pm-thick grooves. Such an etching is performed h using Model No. "Rainbow 440W by LAM Co. at power 200walt under an atmospheric pressure of 350 millibar with use of a mixed gas of HBR(hydro bromide):C12 = 40SCCM:120SCCM. As a result, U -shaped grooves having cylindrical inter walls are formed in the polysilicon as shown in Figure 4C and hemispherical portions 64 corresponding to the exposed grains 66 are formed in the bottom surfaces of the grooves, whereby the surface area of the storage electrode 36 is further increased. After forming such microtrenches, a SO, layer of about 70A thickness is formed on the surface of the storage electrode by the conventional CVD, and a dielectric layer 40 of an N-O structure (or an 0-N-O structure, if a naturally oxidized S'02 layer is added thereto) of about 20Athick SiO, layer obtained by heat-oxidizing the surface of the S'3N, layer, is coated. Then, a doped polysilicon layer is formed on the dielectric layer 40 by the conventional technique and the doped polysilicon layer is patterned by the conventional photoetching to form the plate electrode 42.

In case of Figures 5A through 5C, according to the present invention, after an etchback of the mask layer 58, an etching mask layer 62 is formed on the side walls of the respective grains 60 as shown in Figure 5B, and the upper portions 66 of the grains 60 and the surface portions 68 of the polysilicon -)o layer 56 disposed between the grains 60 are exposed. Thereafter, a submicron-class etching is performed and, as a result, the storage electrode 36 having multiple microcylinders 70 is formed as shown in Figure 5C. In this case also, the hemispherical portions 64 corresponding to the shape of the exposed upper portions 66 are formed in the bottom surface of the cylinders 70. However, the bottom surfaces 80 of the exterior of the microcylinders 70 are etched deeper than the hemispherical portions 64. Accordingly, the manufacture of the microtrenches or the microcylinders can be achieved by the self-alignment etching process without using the photoresist, thereby simplifying the manufacture process.

In case where the structure of Figure 4A and the structure of Figure 5A are mixed, a number of microcylinders and the poles having a number of microtrenches may be provided, after the anisotropic etching.

Thereafter, the dielectric layer 40 of N-O or 0-N-O siructure and the plate electrode 42 are formed on the surface of the storage electrode 36 according to a predetermined process.

The process for making the stacked capacitor having the S'02 etching mask layer 62 disposed on the upper surface of the storage electrode 36 has been described. However, since the etching mask layer 62 can not play the role of the dielectric layer, it is preferred to remove the etching mask layer 6-1.

TheS'02etching mask layer 62 can be removed in buffered HF solution, after the anisotropic etching process.

Generally, after the anisotropic etching, sharp edges are left at the etched edge portions. The sharp edges can also be made around the portions other than the edge portions damaged by the anisotropic etching. The existence of those sharp edges prevents the thin dielectric layer 40 covering the storage electrode 36 from being formed reliably and, further, causes the decrease of the breakdown voltage of the storage capacitor.

A process for rounding the sharp edges can be performed before the dielectric laver 40 is formed and after removing the etching mask laver 62 (in the case of a stacked capacitor without the etching mask layer 62). An Si02 layer of about 10A thick is formed on the storage electrode 36 by soaking the substrate in a mixed solution of HCLI-1202:1-120 = L1:6 with a temperature WC80C Thereafter, the sharp edges are removed by clearing, with the buffered HF solution, the oxide layer formed during the chemical oxidization process.

C5 The present embodiment of the invention forms a 2500A-thick polysilicon layer 56 having hemispherical grains and etches the grooves to a 0 depth 2000A. However, it should be noted that the present invention is not limited to such numerical values. By increasing the thickness of polysilicon layer 56 and etching more deeply the trenches dependant on the selectivity of the polysilicon/dielectric substance, the surface area of the storage electrode 36 may be further increased.

Referring back to Figure 3C, the above described plate electrode 42 is shown. The next process is a reflow process of covering the protection layer such as BPSG (Boro-Phospho- Silicate Glass) or PSG over the substrate 10 so as to flatten the device. Then, the opening 50 is formed by the conventional technique as shown in Figure 2 and an N' region 48 is formed through the opening 50. Then, the bit line 52 of aluminum is formed in contact with the N' region 48.

In the present embodiment of the invention, the bit line 52 overlaps and expands over the transfer transistor and the stacked capacitor 44, and the gate electrode of the transfer transistor is of polysilicon. However, it should be noted that the present invention is not limited to such a structure. Further, the 17- polysilicon forming the first electrode can be replaced with re- cystallized silicon.

Moreover, examples of the present invention can be used in forming a groove in a semiconductor substrate and then, forming a stacked capacitor in the groove.

Further, if a storage capacitor having high storage capacitance is required in a limited area on an insulated substrate, the capacitor can be made by forming a storage electrode having multiple microtrenches on the insulated substrate, forming a dielectric layer thereon and forming a plate electrode on the dielectric layer.

The structure of the storage electrode and the process for making same in accordance with the present invention have been described above by way of examples. However, different embodiments can be achieved without departing from the scope of the present invention. For reference, and just by way of further example, the following is a possible embodiment according to the present invention.

EXAMPLE 1

Referring to Figures 6 and 7, shown is another embodiment of a DRAM memory cell according to the present invention, wherein a field oxide layer 1" for defining the memory cell region is formed on a P-type semiconductor substrate 10. The semiconductor substrate 10 may be of P-type well region.

A transfer transistor vhich includes an N-type source region 16 adjacent to the field oxide layer 12, an N-type drain region 20 separated from, the source region 16 through an N-channel region 18, a gate oxide layer 22 formed over the channel region 18, and a gate electrode 24 disposed on the gate oxide layer 22 and adjacent to the source and drain regions 16 and 20, is formed in an active region 14 positioned on a main surface of the semiconductor substrate surrounded with the field oxide layer 12. The gate electrode 24 is connected to a word line 26. A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent active region is formed on the field oxide layer 121. The gate electrode 24 isisolated from the word line 28 by a first insulating layer 30. The first insulating layer 30 has an opening 135 through which the drain region 20 of the transfer transistor contacts a bit line 150. An opening 125 is formed in the first insulating layer 30 and a second insulating layer 190 covering the bit line 150. The surface of the second insulating layer 190 is flattened. A storage electrode 200 contacts the source region 16 at a source contact region 18 through the opening 125, and defines the storage capacitor region, expanding over the adjacent gate electrode 24 and the word line 28. An upper portion of the storage electrode 200 has a number of microtrenches or microcylinders so as to increase the surface area of the storage electrode, as will be described in detail in the following.

A dielectric layer 40 is formed on the surface of the storage electrode and a plate electrode layer 400 is formed over the dielectric layer 40.

Such a DR-AM memory cell is an application of a DASH (Diagonal Active Stacked capacitor cell with a Highly-packed storage node) structure in which a bit line is formed under the storage capacitor. The DASH structure is well disclosed in IEDM 1988, pp. 596-599. In a DRAM memory cell having the DASH structure, since an expansion of the storage capacitor in horizontal - 19 direction can be designed without limitation of the bit line design rule, it is easy to increase the storage capacitance of the capacitor with a simple process, compared with a DRAM memory cell in which the storage capacitor is formed under the bit line. It is accordingly noted that the storage electrode 200 defining the storage capacitor area can expand widely, unless it contacts the storage electrode of a neighboring storage capacitor.

Now, reference will be made to Figures SA-81), 9A-9C and lOA-10C to explain a process of manufacturing the DRAM memory cell of Figure 7.

Referring to Figure 8A, described is a process of forming a pair of transfer transistors and the bit line 150. The process prior to forming the bit line 150 is the same as the process described with reference to Figure 3A.

Since the bit line 150 is formed on the first insulating layer 30, it is preferable to flatten the surface of the first insulating layer 30 by using a reflow process such as BPSG. Then, a part of the first insulating layer 30 formed on the drain region 20 is removed by conventional photoetching to form the opening through which the drain region 20 of the transfer transistor is connected with the bit line 150 of aluminum.

Referring to Figure 813, after forming the bit line 150, a second insulating layer 190 of BPSG or PSG is coated at a thickness of about 5000A over the substrate and it is reflowed to flatten the surface. The second insulating layer 190 is generally of a silicon oxide, or of a stacked layer of silicon oxide and silicon nitride. In either cases, after the coating of the second insulating layer 190, the surface flattening process should be performed. Alter-natively, the flattening process can be achieved by coating a silicon oxide layer on the substrate, coating resist particles thereop and then etching it with a controlled etching ratio of the resist particles and the silicon oxide layer.

Referring to Figure 8C, after completion of forming and flattening the second insulating layer 190, the opening 125 for exposing a part of the surface of the source region 16 is formed through the second insulating layer 190 and the first insulating layer 30 by the conventional photoetching. After the photoresist used for forming the opening 125 is removed, the polysilicon layer 56 of 2500A thickness having hemispherical grains on its surface is formed on the second insulating layer 190, contacting the surface of the source region 16, as described with reference to Figure 3B. After the polysilicon layer 56 is formed, the arsenic ion implantation is performed to dope the polysilicon layer, as described in Figure 3B. Then, a mask layer 250of S'02 is deposited on the doped polysilicon layer 56 at a thickness of about 300k500A by the conventional CVD. The dielectric substance with a high permittivity such as S'3N, or Ta.,0, can be used for the mask layer 58. However, in consideration of the etching process for forming the microtrenches, it is preferable to use a dielectric substance having a high selectivity of the pol ysi 1 icon/di electric substance. After deposition of the mask layer 250, a patterning process is performed to define the storage capacitor area by conventional photoetching.

In the following, an example of a process for forming microtrenches or microcylinders will be described in detail with reference to Figures 9A and IOA, which are enlarged diagrams for illustrating different embodiments of a rounded portion 500 described in Figure 8C, respectively. Figure IOA (according to the present invention) shows the arrangement of grains in a case - -)l - where the distance S between the hemispherical grains is more thap twice the thickness X of the mask layer 250of S'02 (i.e., S2:2X), and Figure 9A (not according to the present invention) shows the arrangement of the grains in the case where the distance S is zero.

Referring to Figure 9A, anS'02 etchback process used for forming a side wall used in the conventional I-DD MOSFET (Lightly Doped Drain MOSFET) manufacture is performed on the polysilicon oxide layer 250 so as to etchstop at a thickness X (=300A 50O.A) of the S'02 layer 250. This process is the same as the process of Figure 4B. When the SiO, layer 250 is deposited, since the SiO, layer is deposited thicker in the valleys between the polysilicon grains 221, the result of the etchback process is such that etching mask 251 remains in the valleys and the upper portions 222 of the grains 221 are exposed.

Now referring to Figure 9B, an anisotropic etching, in which selectivity of the polysilicon/SiO, is 40, is performed to completely etch out the polysilicon layer 56 of 2500A thickness so as to expose the second insulating layer 190 other than the portion under the etching mask 251. Such an etching is performed by using Model No. "Rainbow 4400" by LAM Co. at power 200watt under an atmospheric pressure of 350 millibar with use of a mixed gas of HBR(hydro-bromide):C1, = 40SCCM:120SCCM. As a result, microtrenches 230 having a screw-hole-like structure are formed, passing through the polysilicon layer 56. It should be noted that this embodiment is different from the process of Figure 4C in that the groove's depth of Figure 4C is 0.2,um while the hole's depth of this embodiment is 2500A. After the screw-hole-like microtrenches 230 are formed, a doped thin polysilicon layer - 1) 1) - 240 is deposited uniformly on the interior and exterior of the micTotrenches 230 by LPCVD with a deposition rate 20-25A/min in the decomposition gas of SiH4 at over 600"C, at which temperature the polysilicon is formed.

Because the effective thickness of the thin polysilicon layer 240 should be thinner than half the diameter (0.07-0.15,um) of the hemispherical grain 211 in order to secure a sufficient surface area of the storage capacitor, it is preferable that the thickness of the thin polysilicon layer 240 be 300- 700A thick. A patterning process is performed on the thin polysilicon layer 240 formed over the entire surface of the substrate by conventional photoetching so as to define the storage capacitor area and form the storage electrode 200.

As a result, the storage electrode 200 including the polysilicon layer 56 and the thin polysilicon layer 2140 has the multiple microtrenches 230.

Now referring to Figure 9C, after the storage electrode 200 is formed, a S'3N, layer of about 70A thickness is formed on the surface of the polysilicon layer 240 (or the storage electrode '100) by the conventional CVD, and a dielectric layer 40 of an N-0 layer (or an O-N-0 layer, if a naturally oxidized S'02 layer is added thereto) of 20A-thick SiO, obtained by heat oxidizing the surface of the S'3N4 layer is coated thereon. Then, the polysilicon layer 400 of doped polysilicon is formed on the dielectric layer 40 to complete the manufacture of the storage capacitor shown in Figure 8D.

Figures 10A through 10C show an embodiment of a storage capacitor according to the present invention. In this case, after an etchback of the mask layer 250, an etching mask layer 251 is formed on the side walls 225 of the respective grains 221 as shown in Figure lOA, and the upper portions 222 of the grains 221 and the surface portions 226 of the polysilicon layer 56 disposed between the grains 221 are exposed. Thereafter, a submicron- class etching is performed on the polysilicon layer 56 to expose the second insulating layer 190 and the thin polysilicon layer 240 is deposited over the entire surface of the substrate. Then, the storage electrode 200 is patterned as shown in Figure 1013. Further, the dielectric layer 40 and the plate electrode 400 are consecutively formed on the storage electrode 200.

It may be noted by a person skilled in the art that, even in the case where the distances between the hemispherical grains are not uniform, a storage capacitor can be made by the above process in accordance to the present invention. It should be further noted that an accurate control of the etching depth for forming the microtrenches is not required, because after the polysilicon 56 other than the portions under the etching mask layers 251 is completely removed with a high selectivity of polysilicon/oxide silicon, the thin polysilicon layer 240 for forming the storage electrode 200 is formed.

In the foregoing, it is considered as an example that the storage electrode includes oxide silicon used as an etching mask. However, since the etching mask layer 251 does not play the role of the dielectric layer, and as it )o can not increase the surface area of the storage capacitor, it is preferred to remove the etching mask layer 251 by performing anisotropic etching and soaking in a buffered HF solution.

Though the embodiment described with reference to Figure 7 shows a DRAM memory cell having a DASH structure in which the bit line is formed under the storage capacitor, the present invention is not restricted to such a structure. For example, this embodiment can be applied to the. DRAM memory cell of Figure 2. In that case, before the polysilicon layer 6 serving as the storage electrode 36 is deposited, the insulating layer 30 formed under the polysilicon layer 56 should be flattened.

Though various structures of a storage capacitor according to the present invention have been shown and described in the forgoing, it will be apparent to a person skilled in the art that various modifications are available without departing from the scope of the present invention. For example, the present invention can be used in forming a groove in a semiconductor substrate and then, forming a stacked capacitor in the groove.

As can be appreciated from the foregoing description, examples of a storage capacitor according to the present invention may have a storage electrode having increased surface area in a limited area, so that the storage capacitance increases. Further, since the microcylinders with a good uniformity are formed, high reliability of the capacitor may be achieved.

Claims

1. A capacitor having a first electrode made of a conduction layer formed on a limited area of a substrate, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer wherein said first electrode comprises a plurality of non-concentric microcylinders formed on a predetermined area of said conduction layer.

2. A capacitor as claimed in claim 1, wherein said conduction layer is a 10 polysilicon layer.

3. A semiconductor memory cell comprising:

a transfer transistor comprising: source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type; a first conduction layer neighbouring with the source and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions; and a first insulating layer covering said first conduction layer, for insulating said first conduction layer: and a storage capacitor comprising: a field oxide layer formed on the substrate, said field oxide layer neighbouring with said source region; a first electrode contacting said source region, said first electrode overlapping a predetermined portion of said first conduction layer and expanding over said field oxide layer., a dielectric layer covering said first electrode; and 26 a second electrode covering said dielectric layer, wherein a plurality of non-concentric microcylinders are formed on said first electrode.

4. A semiconductor memory cell as claimed in claim 3, wherein said microcylinders are hemispherical at bottom portions.

5. A capacitor formed in a limited area of a substrate, having a first electrode made of a conduction layer formed on an insulating layer, a 10 dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer, wherein said first electrode comprises a plurality of non-concentric microcylinders of the conduction layer extending to the surface of said insulating layer, and a thin conduction layer covers said conduction layer at interior and exterior portions of said microcylinders.

6. A capacitor as claimed in claim 5, wherein said thin conduction layer is of polysilicon.

7. A semiconductor memory cell as claimed in claim 5 or 6, wherein said 20 microcylinders have a screw-hole-like structure passing through the conduction layer.

8. A semiconductor memory cell comprising:

a transfer transistor comprising: source and drain regions of a second conduction type formed on a semiconductor substrate of a first conduction type; -27 a first conduction layer neighbouring with the source. and drain regions and insulated through a gate oxide layer from a channel region formed between the source and drain regions; and a first insulating layer covering said first conduction layer, for insulating said first conduction layer: and a storage capacitor comprising:

9. A semiconductor memory cell as claimed in claim 8, wherein said first 25 and second conduction layers are respectively a word line and a bit line.

- 2810. A semiconductor memory cell as claimed in claim 8 or 9, wherein said microcylinders have a screwhole-like structure passing through the said other conduction layer.

11. A semiconductor memory cell as claimed in claim 8, 9 or 10, wherein said thin conduction layer is of polysilicon.

12. A semiconductor memory cell as claimed in claim 8, 9, 10 or 11, wherein said second insulating layer has a flattened surface.

13. A capacitor or a semiconductor memory cell substantially as hereinbefore described with reference to the accompanying drawings.

14. A semiconductor memory device including a capacitor or a semiconductor memory cell according to any preceding claim.