GB2276762A - Mounting arrangement for semiconductor devices - Google Patents

Mounting arrangement for semiconductor devices Download PDF

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Publication number
GB2276762A
GB2276762A GB9306823A GB9306823A GB2276762A GB 2276762 A GB2276762 A GB 2276762A GB 9306823 A GB9306823 A GB 9306823A GB 9306823 A GB9306823 A GB 9306823A GB 2276762 A GB2276762 A GB 2276762A
Authority
GB
United Kingdom
Prior art keywords
substrate
semiconductor devices
connector member
electrical connection
mounting arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9306823A
Other versions
GB2276762B (en
GB9306823D0 (en
Inventor
Robert James Dickenson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Semiconductors Ltd
Original Assignee
Plessey Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Semiconductors Ltd filed Critical Plessey Semiconductors Ltd
Priority to GB9306823A priority Critical patent/GB2276762B/en
Publication of GB9306823D0 publication Critical patent/GB9306823D0/en
Priority to EP94301643A priority patent/EP0618613A1/en
Priority to JP6078155A priority patent/JPH077103A/en
Priority to US08/217,505 priority patent/US5508476A/en
Publication of GB2276762A publication Critical patent/GB2276762A/en
Application granted granted Critical
Publication of GB2276762B publication Critical patent/GB2276762B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Abstract

An arrangement for making fatigue-free external connections to a device (4,5) mounted on a direct copper bonded substrate, in which one or more connector tubes (6) are brazed to respective copper areas (2) on the substrate before the device (4,5) is mounted on the substrate, and external connections are made by soldering leads (8) or bus bars (9) into the tubes (6). <IMAGE>

Description

2276762 1M Mounting Arrangement for Semiconductor Devices The present
invention relates to mounting arrangements for semiconductor devices. In particular although not exclusively the invention is concerned with a mounting arrangement, or package, for an insulated gate bipolar transistor (IGBT).
Present mounting arrangements for IGBTs utilise a direct copper bonded (DCB) alumina substrate, which forms the base of the package as well as providing internal isolation. Other semiconductor devices and/or passive components may be mounted on the substrate, and the component-bearing, or populated, side of the substrate may be enclosed in a case and encapsulated with any of a variety of potting compounds.
Several methods are used for attaching connecting wires or bus-bars to copper areas on the substrate, which then make terminals on the outside of the package or module for the end user, one of which methods is to solder the wires or bus-bars directly to the copper area on the populated side of the substrate. With this method components can be mounted on the substrate and the sub-assembly completed before space-restricting external connections are made, which can be essential if space is limited, as is often the case with this kind of structure.
A problem which arises with such soldered joints is that 7 the thermal expansion rate of the copper layer which forms part of the DCB "sandwich" is modified by the bond to the alumina, and is lower than that of free copper. A copper conductor soldered to the copper layer tends to expand and contract at its normal rate, and this results in fatigue and eventual failure of the solder joint, It is an object of the present invention to provide an improved electrical connection to a conductive area on a substrate.
According to one aspect of the present invention a mounting arrangement for one or more semiconductor devices comprises a substrate of electrically insulating material having directly bonded thereon at least one area of electrically conducting material to which a semiconductor device is to be connected, said area of electrically conductive material having brazed thereon an electrically conductive connector member to which an external electrical connection may be soldered.
According to another aspect of the present invention a method of making an electrical connection to a generally laminar conductor formed on a substrate of electrically insulating material, on which substrate one or more semiconductor devices are to be mounted, includes the steps of brazing onto said laminar conductor an electrically conductive connector member, mounting said one or more semiconductor devices on said substrate, and securing an electrical connection to said conductive connector member.
Preferably said connector member takes the form of a short length of tube one end of which is brazed to said laminar conductor. The electrical connection may comprise a wire or strip conductor which is secured to said connector member by soldering.
A mounting arrangement for semiconductor devices providing for electrical connection to the devices by way of conductive areas or layers on an insulating substrate on which the devices are mounted, will now be described by way of example with reference to the accompanying drawing, of which:- Figure 1 shows schematically an isometric view of the mounting arrangement, and Figure 2 shows a sectional view of part of the mounting arrangement shown in Figure 1.
Referring to the drawing a direct copper bonded substrate comprises a thin sheet 1 of alumina having layers of copper 2 and 3 bonded to its upper and lower faces respectively, the layer 2 at least being patterned to suit the connections required to semiconductor devides 4, 5 mounted on the substrate. To prepare for external connections to the devices 4 and 5, short lengths of copper tube 6 are brazed to the copper layer 2 at locations which will not obstruct assembly, the tubes 6 having, say, one end face brazed to the copper layer 2 such that the axis of the tube is perpendicular to the layer 2 as shown or at any convenient angle for making the required external connection.
All assembly operations, such as soldering in place the devices 4 and 5 and making wire bond interconnections 7, are then completed before the assembly space envelope is restricted by the soldering of the wire connections 8 or bus bars 9 into the tubes 6.
The brazed joints between the copper tubes 6 and the copper layers 2 do not fatigue, although it is still expected that the solder will fatigue at its point of contact with the layer 2, the integrity of the connection being maintained through the soldered joint between the walls of the tubes 6 and the connections 8 or bus bars 9.
Because of the temperatures involved, of the order of, say, 780C for a silver/copper eutectic, brazed connections can only be made prior to the mounting on the substrate of components such as the semiconductor devices 4 and 5, and this prevents the use of directly brazed connections except where assembly space is not a consideration. The present method combines the strength and freedom from fatigue of brazed joints with the advantage of making the external connections by soldering at a late stage of manufacture, when space over the substrate is no longer required for 71 positioning and mounting the components on the substrate.
It will be appreciated that the method may find uses with different semiconductor devices and substrate materials.
W 1

Claims (5)

  1. A mounting arrangement for one or more semiconductor devices comprising a substrate of electrically insulating material having directly bonded thereon at least one area of electrically conducting material to which a semiconductor device is to be connected, said area of electrically conductive material having brazed thereon an electrically conductive connector member to which an external electrical connection may be soldered.
  2. 2. A method of making an electrical connection to a generally laminar conductor formed on a substrate of electrically insulating material, on which substrate one or more semiconductor devices are to be mounted, including the steps of brazing onto said laminar conductor an electrically conductive connector member, mounting said one or more semiconductor devices on said substrate, and securing an electrical connection to said conductive connector member.
  3. 3. A method according to Claim 2 wherein said connector member takes the form of a short length of tube one end of which is brazed to said laminar conductor.
  4. 4. A method according to Claim 2 or Claim 3 wherein the electrical connection comprises a wire or strip conductor which is secured to said connector member by soldering.
  5. 5. A mounting arrangement for semiconductor devices substantially as hereinbefore described with reference to the drawings.
GB9306823A 1993-04-01 1993-04-01 Mounting arrangement for semiconductor devices Expired - Fee Related GB2276762B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB9306823A GB2276762B (en) 1993-04-01 1993-04-01 Mounting arrangement for semiconductor devices
EP94301643A EP0618613A1 (en) 1993-04-01 1994-03-08 Connections arrangement for semiconductor devices
JP6078155A JPH077103A (en) 1993-04-01 1994-03-24 Apparatus and method for mounting one or more semiconductor device
US08/217,505 US5508476A (en) 1993-04-01 1994-03-24 Mounting arrangement for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9306823A GB2276762B (en) 1993-04-01 1993-04-01 Mounting arrangement for semiconductor devices

Publications (3)

Publication Number Publication Date
GB9306823D0 GB9306823D0 (en) 1993-05-26
GB2276762A true GB2276762A (en) 1994-10-05
GB2276762B GB2276762B (en) 1996-10-30

Family

ID=10733162

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9306823A Expired - Fee Related GB2276762B (en) 1993-04-01 1993-04-01 Mounting arrangement for semiconductor devices

Country Status (4)

Country Link
US (1) US5508476A (en)
EP (1) EP0618613A1 (en)
JP (1) JPH077103A (en)
GB (1) GB2276762B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777849A (en) * 1996-02-06 1998-07-07 Asea Brown Boveri Ag Power semiconductor module having elongate plug contacts
US6423907B1 (en) * 1998-02-09 2002-07-23 Tessera, Inc. Components with releasable leads
JP2002186137A (en) * 2000-12-14 2002-06-28 Yazaki Corp Connection structure for connecting electrical component to electrical junction box
US6712772B2 (en) * 2001-11-29 2004-03-30 Biocontrol Medical Ltd. Low power consumption implantable pressure sensor
US8380312B2 (en) 2009-12-31 2013-02-19 Ams Research Corporation Multi-zone stimulation implant system and method
WO2013036399A2 (en) 2011-09-08 2013-03-14 Ams Research Corporation Implantable electrode assembly

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778530A (en) * 1971-04-01 1973-12-11 W Reimann Flatpack lead positioning device
US4634638A (en) * 1981-12-17 1987-01-06 International Business Machines Corporation High melting point copper-gold-tin brazing alloy for chip carriers
US4970570A (en) * 1986-10-28 1990-11-13 International Business Machines Corporation Use of tapered head pin design to improve the stress distribution in the braze joint
JPS62282456A (en) * 1987-05-19 1987-12-08 Toshiba Corp Manufacture of hybrid ic
FR2673040B1 (en) * 1991-02-19 1997-01-31 Thomson Csf METHOD FOR ASSEMBLING AND INTERCONNECTING MODULAR ELECTRONIC CARDS, CARDS AND ELECTRONIC CARD ASSEMBLY ACCORDING TO THIS METHOD.
JP2927010B2 (en) * 1991-03-01 1999-07-28 株式会社日立製作所 Semiconductor package
US5196251A (en) * 1991-04-30 1993-03-23 International Business Machines Corporation Ceramic substrate having a protective coating thereon and a method for protecting a ceramic substrate
US5198885A (en) * 1991-05-16 1993-03-30 Cts Corporation Ceramic base power package
EP0544934B1 (en) * 1991-11-30 1996-10-02 Endress U. Hauser Gmbh U. Co. Method of stabilizing the surface properties of objects to be thermally treated in a vacuum

Also Published As

Publication number Publication date
JPH077103A (en) 1995-01-10
GB2276762B (en) 1996-10-30
EP0618613A1 (en) 1994-10-05
GB9306823D0 (en) 1993-05-26
US5508476A (en) 1996-04-16

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Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20050401