GB2260644A - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
GB2260644A
GB2260644A GB9208891A GB9208891A GB2260644A GB 2260644 A GB2260644 A GB 2260644A GB 9208891 A GB9208891 A GB 9208891A GB 9208891 A GB9208891 A GB 9208891A GB 2260644 A GB2260644 A GB 2260644A
Authority
GB
United Kingdom
Prior art keywords
resin
chip
package
tsop
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9208891A
Other versions
GB9208891D0 (en
Inventor
Chung Woo Lee
Young Jae Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9208891D0 publication Critical patent/GB9208891D0/en
Publication of GB2260644A publication Critical patent/GB2260644A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor package in which one side of a resin encapsulated chip (21), or the lead frame pad (23) which supports it, is free from the body of resin. Both TSOP and FCP embodiments of the invention are disclosed. <IMAGE>

Description

2 3 6 4 4 -l- SEMICONDUCTOR PACKAGE The present invention relates to a
semiconductor package comprising a body of resin, a semiconductor device and a plurality of leads.
Recent developments in semiconductor packages have been concerned with c miniaturisation, multi-function, and large capacity. This has resulted from developments in the multi-function, multi-pin, and high speed aspects of the semiconductor devices themselves. In order to meet these requirements, recent developments have included the TQFP (Thin Quad Flat Package), TSOP (Thin Small Outline Package), FCP (Flip Chip Package), and TABP (Tape Automated 1 Bonding Package). The TQFP and TSOP use conventional wires for bonding, 1 while the FCP and TABP utilise the thermal compression of metal bumps method of bonding. A common aim is to reduce the thickness of the packages.
Figure 1 illustrates a cross-sectional view of a conventional TSOP. In the TSOP, a lead frame pad 13 which supports a chip 11 is located below the internal leads 15. Internal leads 15 are connected to chip 11 by wiring lines 17. The TSOP is molded within a body of resin, which covers the internal leads 15 and fixes chip 11 at the center of the lead frame pad 13. External leads 19 remain outside the resin and are bent to the required shape. By reducing the loop shape of wiring lines 17 the thickness of the TSOP can be reduced to about l mm. In the TSOP, however, water particles can be absorbed under the lead frame pad 13 during the molding process. Such water particles tend to condense, generating stresses which can crack the package.
Figure 2 illustrates a cross-sectional view of a conventional FCP. In the FCP, the chip 11 is bonded with the internal leads 15 by metal bumps 18, in such a manner that the chip is upside down as compared with the figure 1 arrangement.
1 -- -1) I- The FCP is molded within a body of resin which encompasses the internal leads 15 and fixes chip 11 at the center of the FCP. External leads 19 mree bent to the required shape. The FCP needs no additional lead frame pad because the chip 11 is supported by the internal leads 15. Therefore, in the FCP cracking of the package due to water particle condensation is avoided and a relatively thin and compact form is achieved.
In both the TSOP and the FCP, however, it is difficult to fabricate a thin body of resin. Additionally, even though a thin package is achieved, the chip is often tilted by the force applied by the resin during the molding process. This can result in various difficulties.
It is an object of the present invention to mitigate the above mentioned disadvantages and to provide a semiconductor package of improved reliability and ZP simple construction.
According to the present invention, there is provided a semiconductor package comprising a body of resin, a semiconductor device and a plurality of leads with one side of the semiconductor device, or of a lead frame pad to which it is attached, being free of the resin.
Embodiments of the present invention will now be described, by way of example only and with reference to the accompanying drawings, in which:- C Figure 1 illustrates a cross-sectional view of a conventional TSOP, Figure 2 illustrates a cross-sectional view of a conventional FCP, Figure 3 illustrates a cross-sectional view of a TSOP according to one embodiment of the present invention, and Figure 4 illustrates a cross-sectional view of a FCP according to another embodiment of the present invention.
i -I- Figure 3 is a cross-sectional view of a TSOP according to one embodiment of the present invention. A chip 21 is located on a front side of a lead frame pad 23 by a bonding agent. The chip is connected to internal leads 25 by wiring lines 27.
ZP:' ZD The TSOP is molded within a body of resin, encompassing the internal leads 25 but exposing the back side of lead frame pad 23. External leads 29 are free of the resin and are bent to the required shape. In particular, the leads may be bent such that the free surface of the lead frame pad is either at the top or bottom of the final package. In the molding process, pad 23 is held in a molding machine which prevents chip 21 from being moved by the resin.
Fiaure 4 illustrates a cross-sectional view of a FCP according to another embodiment of the present invention. Chip 21 is bonded with internal leads 25 by metal bumps 28 with the chip being upside down, as in the arrangement shown in figure 2. The FCP of figure 4 is molded within a body of resin so as to encompass but to expose the back side of the chip 21. Again, external leads internal leads. 29 are free of the resin and are bent to shape as required. In the molding process, I the back side of the chip 21 is held in a molding machine, so as to keep the back ZD side of the chip 21 free of resin and to prevent the chip 21 from being moved by the resin.
In the TSOP and FCP according to the present invention, the back side of the lead frame pad or of the chip itself is kept free from the resin. Therefore, the packages can be as thin as the resin which surrounds the internal leads 25.
1 Furthermore, in the TSOP, tension can be reduced by increasing the size of the loops of the wiring lines without increasing the thickness of package. Additionally, C> the arrangements illustrated in figures 3 and 4 improve dissipation of heat generated during operation of the chip. Cracking of the package due to differences in thermal 0 0 1 expansion between the resin and the pad is prevented. Also, movement of the chip within the package during moulding is prevented, by the lead frame pad and/or the chip itself being held by the molding machine in the molding process.
The present invention results in thin packages and can reduce the tension of the wiring lines in a TSOP. Also, the present invention mitigates the problem of cracking of the package and improves the heat emitting ability, thereby improving the overall reliability of the package.
The invention is not limited to the embodiments described hereinabove. Various modifications of the disclosed embodiments as well as other embodiments of the invention will be apparent to persons skilled in the art from the description given above.
CLAAAS A semiconductor package comprising a body of resin, a semiconductor device and a plurality of leads. with one side of the semiconductor device, or of a lead frame pad to which it is attached, being free of the resin.
2. A semiconductor package as claimed in claim 1 and having a semiconductor device supported on one side of a lead frame pad and the body of resin holding the lead frame pad relative to internal portions of the leads, wherein the side of said lead frame pad opposite that supporting the semiconductor device is free of the resin.
A semiconductor package as claimed in claim 2, wherein the internal leads extend beyond the resin to form external leads which can be bent so that the side of the lead frame pad which is free of the resin is selectively at the top side of the package or at the bottom side thereof.
4. A semiconductor device as claimed in claim 1, wherein the semiconductor device is bonded directly to the leads.
5. A semiconductor device substantially as hereinbefore described with reference to and as illustrated in figure 3 of the accompanying drawings.
1:1 In 6. A semiconductor device substantially as hereinbefore described with reference to and as illustrated in figure 4 of the accompanying drawings.
GB9208891A 1991-10-18 1992-04-24 Semiconductor package Withdrawn GB2260644A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018423A KR930009031A (en) 1991-10-18 1991-10-18 Semiconductor package

Publications (2)

Publication Number Publication Date
GB9208891D0 GB9208891D0 (en) 1992-06-10
GB2260644A true GB2260644A (en) 1993-04-21

Family

ID=19321489

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9208891A Withdrawn GB2260644A (en) 1991-10-18 1992-04-24 Semiconductor package

Country Status (4)

Country Link
JP (1) JPH05206321A (en)
KR (1) KR930009031A (en)
DE (1) DE4234993A1 (en)
GB (1) GB2260644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0711104A1 (en) * 1994-11-01 1996-05-08 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor, semiconductor device made therewith and method for making same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2556294B2 (en) * 1994-05-19 1996-11-20 日本電気株式会社 Resin-sealed semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1186890A (en) * 1966-07-13 1970-04-08 Motorola Inc Semiconductor Device
GB2043343A (en) * 1979-02-23 1980-10-01 Hitachi Ltd Semiconductor device
WO1988006348A1 (en) * 1987-02-20 1988-08-25 Lsi Logic Corporation Integrated circuit package assembly
GB2218570A (en) * 1988-05-09 1989-11-15 Nat Semiconductor Corp Plastics moulded pin-grid-array power package
US4926239A (en) * 1983-06-07 1990-05-15 Sharp Kabushiki Kaisha Plastic encapsulant for semiconductor
US4981776A (en) * 1983-01-25 1991-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a plastic encapsulated semiconductor device with insulated heat sink

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3570115A (en) * 1968-05-06 1971-03-16 Honeywell Inc Method for mounting electronic chips
JPS54128278A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Resin-sealed semiconductor device and its packaging method
FR2429494A1 (en) * 1978-06-21 1980-01-18 Materiel Telephonique Encapsulation semiconductor chip connector - has continuous metal strip with contact points bearing on chip
JPS55134940A (en) * 1979-04-06 1980-10-21 Citizen Watch Co Ltd Resin sealing method for ic
FR2488445A1 (en) * 1980-08-06 1982-02-12 Efcis PLASTIC CASE FOR INTEGRATED CIRCUITS

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1186890A (en) * 1966-07-13 1970-04-08 Motorola Inc Semiconductor Device
GB2043343A (en) * 1979-02-23 1980-10-01 Hitachi Ltd Semiconductor device
US4981776A (en) * 1983-01-25 1991-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a plastic encapsulated semiconductor device with insulated heat sink
US4926239A (en) * 1983-06-07 1990-05-15 Sharp Kabushiki Kaisha Plastic encapsulant for semiconductor
WO1988006348A1 (en) * 1987-02-20 1988-08-25 Lsi Logic Corporation Integrated circuit package assembly
GB2218570A (en) * 1988-05-09 1989-11-15 Nat Semiconductor Corp Plastics moulded pin-grid-array power package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0711104A1 (en) * 1994-11-01 1996-05-08 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor, semiconductor device made therewith and method for making same

Also Published As

Publication number Publication date
GB9208891D0 (en) 1992-06-10
JPH05206321A (en) 1993-08-13
KR930009031A (en) 1993-05-22
DE4234993A1 (en) 1993-04-22

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