KR0152555B1 - Chip scale package for lead frame - Google Patents
Chip scale package for lead frameInfo
- Publication number
- KR0152555B1 KR0152555B1 KR1019950037832A KR19950037832A KR0152555B1 KR 0152555 B1 KR0152555 B1 KR 0152555B1 KR 1019950037832 A KR1019950037832 A KR 1019950037832A KR 19950037832 A KR19950037832 A KR 19950037832A KR 0152555 B1 KR0152555 B1 KR 0152555B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- scale package
- lead frame
- chip scale
- bonding pads
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 칩 스케일 패키지에 관한 것으로, 리드프레임을 적용하여 칩 스케일 패키지를 실현하여 종래 패키지 제조 장치를 사용할 수 있기 때문에 제조 단가 측면에서 저렴한 패키지를 실현할 수 있으며, TSOP 수준의 신뢰도를 보장하는 동시에 상대적으로 고 난이도의 제조 기술이 요구되지않는 특징을 갖는다.The present invention relates to a chip scale package. Since the lead frame is applied to realize a chip scale package, a conventional package manufacturing apparatus can be used, so that a cheap package can be realized in terms of manufacturing cost, and the TSOP level of reliability can be assured. As a result, the manufacturing technology of the high difficulty is not required.
Description
제1도는 종래 기술의 일 실시예에 의한 테세라(Tessera)사(社)의 칩 스케일 패키지를 나타내는 단면도.1 is a cross-sectional view showing a chip scale package of Tessera Corporation according to an embodiment of the prior art.
제2도는 종래 기술의 다른 실시예에 의한 미찌비시(Mitsubishi) 사의 칩 스케일 패키지의 일 부분을 절개하여 내부를 나타내는 사시도.Figure 2 is a perspective view showing the inside by cutting a portion of the chip scale package of Mitsubishi, according to another embodiment of the prior art.
제3도는 종래 기술의 또 다른 실시예에 의한 도시바(Toshiba) 사의 칩 스케일 패키지를 나타내는 단면도.3 is a cross-sectional view showing a chip scale package of Toshiba Corporation according to another embodiment of the prior art.
제4도는 본 발명의 일 실시예에 의한 리드프레임을 적용한 센터 패드(center pad)를 갖는 칩 스케일 패키지를 나타내는 단면도.4 is a cross-sectional view illustrating a chip scale package having a center pad to which a lead frame according to an embodiment of the present invention is applied.
제5도는 본 발명의 다른 실시예에 의한 리드프레임을 적용한 센터 패드를 갖는 칩 스케일 패키지를 나타내는 단면도.5 is a cross-sectional view illustrating a chip scale package having a center pad to which a lead frame according to another embodiment of the present invention is applied.
제6도는 본 발명의 또 다른 실시예에 의한 리드프레임을 적용한 에지 패드(edge pad)를 갖는 칩 스케일 패키지를 나타내는 단면도.6 is a cross-sectional view illustrating a chip scale package having an edge pad to which a lead frame is applied according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
310, 510 : 칩 312, 512 : 본딩 패드310, 510: chip 312, 512: bonding pad
320, 520 : 폴리이미드 테이프 330, 530 : 본딩 와이어320, 520: polyimide tape 330, 530: bonding wire
340, 540 : 내부리드 350, 550 : 외부리드340, 540: Internal lead 350, 550: External lead
360, 560 : 액상수지360, 560: liquid resin
400, 500, 600 : 칩 스케일 패키지(CSP)400, 500, 600: Chip Scale Package (CSP)
본 발명은 칩 스케일 패키지에 관한 것으로, 더욱 상세하게는 리드프레임을 적용하여 칩과의 전기적 연결을 하여 통상적인 패키지 제조 장치를 이용할 수 있기 때문에 저 단가의 칩 스케일 패키지를 제조할 수 있는 리드프레임을 적용한 칩 스케일 패키지(chip scale package)에 관한 것이다.The present invention relates to a chip scale package, and more particularly, a lead frame capable of manufacturing a low cost chip scale package can be manufactured since a conventional package manufacturing apparatus can be used by applying a lead frame to electrically connect with a chip. The present invention relates to an applied chip scale package.
시스템의 경박 단소의 추세에 맞추어 그에 실장되는 패키지의 크기 또한 경박 단소가 추구되어졌다. 그러나, 통상적인 패키지에 있어서는 상기의 목적을 달성하기에는 역부족인 면이 있었다.In accordance with the trend of light and small short of the system, the size of the package to be mounted is also pursued. However, in the conventional package, there existed a side which is inadequate to achieve the said objective.
결국, 칩 크기에 대응되는 패키지의 개발이 요구되어졌다. 최근 몇몇 제조 회사에서 추진되고 있는 소위, 칩 스케일 패키지(chip scale package, CSP)는 멀티 칩 모듈용으로 개발되어 노운 굿 다이(known good die)의 대용으로 활용되어지고 있다.As a result, development of a package corresponding to the chip size has been required. Recently, a so-called chip scale package (CSP), which is being promoted by several manufacturing companies, has been developed for a multi-chip module and used as a substitute for a known good die.
그러나, 제조 단가 면에서 볼 그리드 어레이(ball grid array) 패키지보다 불리하기 때문에 제조 설비를 갖는 몇몇 회사에서만 추진 중에 있다.However, only a few companies with manufacturing facilities are pushing forward because they are disadvantageous over ball grid array packages in terms of manufacturing cost.
제1도는 종래 기술의 일 실시예에 의한 테세라(Tessera)사(社)의 칩 스케일 패키지를 나타내는 단면도이다.1 is a cross-sectional view showing a chip scale package of Tessera Corporation according to an embodiment of the prior art.
제1도를 참조하면, 종래 기술의 CSP(100)는 칩(10)의 하부면 상에 형성된 본딩 패드들(12)이 그들(12)에 대응되는 플렉시블(flexible) 패턴(20)과 각기 대응되어 전기적 연결되어 있으며, 그 플랙시블 패턴(20)의 하부 상에 관통 구멍들이 형성된 폴리이미드 필름(40)이 부착되어 있으며, 상기 플랙시블 패턴(20)과 그 각기 솔더 범프들(60)은 표면에 전도성 물질이 코팅된 관통 구멍들에 의해 각기 전기적 연결되는 구조를 갖는다.Referring to FIG. 1, the CSP 100 of the related art corresponds to a flexible pattern 20 in which bonding pads 12 formed on the bottom surface of the chip 10 correspond to them 12, respectively. And a polyimide film 40 having through holes formed on the lower portion of the flexible pattern 20, and the flexible pattern 20 and the respective solder bumps 60 are formed on a surface of the flexible pattern 20. Has a structure that is electrically connected to each other by through holes coated with a conductive material.
여기서, 상기 칩(10)의 하부 면상의 본딩 패드들(12)이 형성되지 않는 부분과 상기 플랙시블 패턴(20)의 사이에 엘라스토머(elastomer)(30)가 개재되어 있다.Here, an elastomer 30 is interposed between the portion where the bonding pads 12 on the lower surface of the chip 10 are not formed and the flexible pattern 20.
그리고, 상기 칩(10)은 핸들링 링(50)에 의해 고정되어 있으며, 칩(10)의 상부면은 상기 핸들링 링(50)에 대하여 노출되어 있는 구조를 갖는다.The chip 10 is fixed by the handling ring 50, and an upper surface of the chip 10 is exposed to the handling ring 50.
이와같은 구조를 갖는 패키지는, 일종의 μGA 패키지로써 번인 검사가 가능하며 고밀도 실장이 가능한 플립칩의 상호 접속 기술이다.A package having such a structure is a flip chip interconnect technology that enables burn-in inspection as a kind of μGA package and enables high density mounting.
또한, 고 열방출성과 다양한 검사에 대응되기 용이한 장점을 가지나 단위 공정별로 제조 단가가 높으며 표준화가 어려운 단점을 가지고 있다.In addition, it has the advantages of high heat dissipation and easy to cope with various inspections, but has a high manufacturing cost per unit process and difficult to standardize.
제2도는 종래 기술의 다른 실시예에 의한 미찌비시(Mitsubishi) 사의 칩 스케일 패키지의 일부분을 절개하여 내부를 나타내는 사시도이다.2 is a perspective view showing the inside by cutting a portion of a chip scale package of Mitsubishi Corporation according to another embodiment of the prior art.
제2도를 참조하면, 종래 기술의 CSP(200)는 칩(110)의 상부면 상의 중심 부분에 형성된 본딩 패드들(이하 센터 패드 라 한다.)(112)이 그들(112)에 각기 대응되는 솔더 범프들(160)과 칩 상면에 형성되어 있는 회로 패턴들(120)에 의해 각기 전기적으로 연결되어 있으며, 상기 전기적 연결 부분을 외부의 환경으로부터 보호하기위해서 성형수지(150)에 의해 봉지되어 있으며, 상기 솔더 범프들(160)의 상기 성형수지(150)의 대하여 노출되게 형성된 구조를 갖는다.Referring to FIG. 2, the CSP 200 of the prior art has bonding pads (hereinafter referred to as center pads) 112 formed at the center portion on the top surface of the chip 110 corresponding to them 112, respectively. The solder bumps 160 are electrically connected to each other by circuit patterns 120 formed on an upper surface of the chip, and are encapsulated by a molding resin 150 to protect the electrical connection parts from an external environment. In addition, the solder bumps 160 may be formed to be exposed to the molding resin 150.
이와같은 구조를 갖는 패키지는, 제1도에서 언급된 장점 이외에 회로 패턴이 형성되어 있기 때문에 본딩 패드의 위치에 제한을 받지 않는 동시에 TSOP(thin small outline package)와 같은 신뢰성이 보장되는 장점을 갖으나, 상기 솔더 범프의 크기가 크기 때문에 초 다핀 대응이 곤란하며 웨이퍼 제조 공정에서 회로 패턴들을 제조하기 때문에 조립 공정이 복잡하며 공정별 제조 단가가 높다.Packages having such a structure have advantages such as thin small outline packages (TSOPs), which are not limited to the position of the bonding pads because the circuit pattern is formed in addition to the advantages mentioned in FIG. In addition, since the solder bumps are large, it is difficult to cope with ultra-multi pins, and because the circuit patterns are manufactured in the wafer manufacturing process, the assembly process is complicated and the manufacturing cost per process is high.
제3도는 종래 기술의 또 다른 실시예에 의한 도시바(Toshiba) 사의 칩 스케일 패키지를 나타내는 단면도이다.3 is a cross-sectional view showing a chip scale package of Toshiba Corporation according to another embodiment of the prior art.
제3도를 참조하면, 종래의 CSP(300)는 칩(210)의 하부면 상에 형성된 본딩 패드들(212)은 그들(212)에 각기 대응되는 기판(250) 상의 회로 패턴들(252)과 각기 금(Au) 재질의 범프(220)에 의해 각기 전기적 연결되어 있으며, 상기 회로 패턴들(252)을 상기 기판(250) 상에 형성된 관통 구멍들(254)에 의해 각기 그 기판(250)의 하부면 상에 형성된 전극 단자들(256)과 각기 전기적 연결되어 있으며, 상기 전기적 연결된 부분을 보호하기 위하여 열 경화성 수지(260)에 의해 상기 칩(210)의 하부부터 상기 기관(250)의 상부면까지 성형된 구조를 갖는다.Referring to FIG. 3, the conventional CSP 300 includes bonding pads 212 formed on the bottom surface of the chip 210, and circuit patterns 252 on the substrate 250 corresponding to them 212, respectively. And each of the substrates 250 is electrically connected to each other by bumps 220 made of Au, and the circuit patterns 252 are formed through through holes 254 formed on the substrate 250, respectively. Each of the terminals 250 is electrically connected to the electrode terminals 256 formed on the lower surface of the upper part of the engine 250 from the bottom of the chip 210 by a thermosetting resin 260 to protect the electrically connected parts. It has a molded structure up to face.
여기서, 상기 관통 구멍들(254)의 내표면은 전도성 물질로 코팅되어 있으며, 결과적으로 본딩 패드들(212)과 전극 단자들(256)이 각기 관통 구멍들(254)에 의해전기적 연결되어 있다.Here, the inner surfaces of the through holes 254 are coated with a conductive material, and as a result, the bonding pads 212 and the electrode terminals 256 are electrically connected to each other by the through holes 254.
이와 같은 구조를 갖는 패키지는, 0.5mm 정도로 두께가 얇은 패키지를 실현할 수 있는 플립 칩 기술을 이용하고 있으나 고가의 기판(알루미나)을 사용하기 때문에 패키지의 제조 단가가 높은 단점을 내포하고 있다.The package having such a structure uses flip chip technology that can realize a package that is as thin as 0.5 mm, but has a disadvantage in that the manufacturing cost of the package is high because an expensive substrate (alumina) is used.
따라서 본 발명의 목적은 리드프레임을 적용하여 종래 패키지 제조 장치를 사용할 수 있기 때문에 제조 단가 측면에서 저렴한 패키지를 실현할 수 있으며, TSOP 수준의 신뢰도를 보장하는 동시에 상대적으로 고 난이도의 제조 기술이 요구되지 않는 리드 프레임을 적용한 칩 스케일 패키지(chip scale package)를 제공하는데 있다.Accordingly, an object of the present invention is to realize a cheap package in terms of manufacturing cost because it can use a conventional package manufacturing apparatus by applying a lead frame, while ensuring the reliability of the TSOP level does not require a relatively high difficulty manufacturing technology The present invention provides a chip scale package using a lead frame.
상기 목적을 달성하기 위하여, 칩의 크기에 대응되는 크기를 갖는 칩 스케일 패키지(chip scale package)에 있어서, 복수개의 본딩 패드들을 갖는 칩과; 그 본딩 패드들에 각기 대응되어 전기적 연결된 내부 리드들과, 그 내부리드들과 각기 일체형으로 대응된 외부리드들을 포함하는 리드프레임과; 상기 칩과 리드프레임의 내부리드들이 내재·봉지된 성형수지를 포함하며, 그 리드프레임의 외부 리드들과 상기 칩의 본딩 패드들이 형성된 반대 면이 상기 성형수지에 대하여 노출된 것을 특징으로 하는 리드프레임을 적용한 칩 스케일 패키지를 제공한다.In order to achieve the above object, a chip scale package having a size corresponding to the size of a chip, comprising: a chip having a plurality of bonding pads; A lead frame including inner leads electrically connected to the bonding pads and electrically connected to the bonding pads, and outer leads respectively integrally associated with the inner leads; And a molding resin in which the inner leads of the chip and the lead frame are embedded and encapsulated, and an opposite surface on which the outer leads of the lead frame and the bonding pads of the chip are formed is exposed to the molding resin. Provides a chip scale package to which is applied.
이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제4도는 본 발명의 일 실시예에 의한 리드프레임을 적용한 센터 패드(center pad)를 갖는 칩 스케일 패키지를 나타내는 단면도이다.4 is a cross-sectional view illustrating a chip scale package having a center pad to which a lead frame according to an embodiment of the present invention is applied.
제5도는 본 발명의 다른 실시예에 의한 리드프레임을 적용한 센터 패드를 갖는 칩 스케일 패키지를 나타내는 단면도이다.5 is a cross-sectional view illustrating a chip scale package having a center pad to which a lead frame according to another embodiment of the present invention is applied.
제6도는 본 발명의 또 다른 실시예에 의한 리드프레임을 적용한 에지 패드 (edge pad)를 갖는 칩 스케일 패키지를 나타내는 단면도이다.6 is a cross-sectional view illustrating a chip scale package having an edge pad to which a lead frame according to another embodiment of the present invention is applied.
제4도 내지 제6도를 참조하면, 본 발명에 의한 CSP(400)는 칩(310)의 하부면 상의 형성된 센터 패드들(312)이 그들(312)에 대응되는 리드프레임의 내부리드들(340)이 각기 본딩 와이어(330)에 의해 전기적 연결되어 있으며, 그 칩(310)의 가장자리 부분과 내부 리드들(340)의 전기적 연결 부분을 제외한 소정 영역과 폴리이미드 테이프(320)에 의해 접착되어 고정되어 있으며, 상기 전기적 연결 부분과 내부리드들(340)이 액상 수지(360)에 의해 봉지되어 있으며, 상기 내부리드들(340)과 일체형인 외부리드들(350)이 상기 액상 수지(360)에 노출되어 있는 구조를 갖는다.4 to 6, the CSP 400 according to the present invention includes the inner leads of the lead frame in which the center pads 312 formed on the bottom surface of the chip 310 correspond to them 312. Each of the 340 is electrically connected by the bonding wires 330, and a predetermined region except for the edge portion of the chip 310 and the electrical connection portion of the inner leads 340 is bonded by the polyimide tape 320. The electrical connection part and the inner leads 340 are fixed by the liquid resin 360, and the outer leads 350 integral with the inner leads 340 are the liquid resin 360. It has a structure exposed to.
또한, 상기 칩(310)에 전원이 인가되어 작동될 때에 발생되는 열을 대기 중으로 신속하게 방출하기 위해 상기 액상 수지(360)에 대하여 칩(310)의 본딩 패드들(312)이 형성된 엑티브 영역의 다른 면이 노출되어 있다.In addition, the active area of the active region in which bonding pads 312 of the chip 310 are formed with respect to the liquid resin 360 in order to quickly release heat generated when the chip 310 is powered and operated to the atmosphere. The other side is exposed.
제5도의 CSP(500)는 제4도의 CSP(400) 구조의 폴리이미드 테이프(320)에 의해 리드프레임이 지지되지 않고 직접 본딩 와이어들(330)에 의해 지지되는 구조를 갖는 것 외에는 제4도의 CSP(400)와 동일한 구조를 갖는다.The CSP 500 of FIG. 5 has a structure in which the lead frame is not supported by the polyimide tape 320 of the CSP 400 structure of FIG. 4 but is directly supported by the bonding wires 330. It has the same structure as the CSP 400.
또한, 제6도의 CSP(600)는 칩(510)의 본딩 패드들(512)이 칩(510)의 가장자리 부분에 형성된 것 외에는 제4도의 CSP(400) 구조와 동일한 구조를 갖는다.In addition, the CSP 600 of FIG. 6 has the same structure as that of the CSP 400 of FIG. 4 except that the bonding pads 512 of the chip 510 are formed at an edge of the chip 510.
따라서, 본 발명에 따른 구조에 따르면, 통상적인 종래 기술에 의한 CSP의 장점을 갖는 동시에 리드프레임을 적용하여 종래 패키지 제조 장치를 사용할 수 있기 때문에 제조 단가 측면에서 저렴한 패키지를 실현할 수 있으며, TSOP 수준의 신뢰도를 보장하는 동시에 상대적으로 고 난이도의 제조 기술이 요구되지 않는 이점(利點)이 있다.Therefore, according to the structure according to the present invention, it is possible to use a conventional package manufacturing apparatus by applying a lead frame while having the advantages of the conventional CSP according to the prior art, it is possible to realize a cheap package in terms of manufacturing cost, TSOP level While ensuring reliability, there is an advantage that relatively difficult manufacturing techniques are not required.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037832A KR0152555B1 (en) | 1995-10-28 | 1995-10-28 | Chip scale package for lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950037832A KR0152555B1 (en) | 1995-10-28 | 1995-10-28 | Chip scale package for lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970024081A KR970024081A (en) | 1997-05-30 |
| KR0152555B1 true KR0152555B1 (en) | 1998-10-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950037832A KR0152555B1 (en) | 1995-10-28 | 1995-10-28 | Chip scale package for lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0152555B1 (en) |
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1995
- 1995-10-28 KR KR1019950037832A patent/KR0152555B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970024081A (en) | 1997-05-30 |
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