GB2252448A - method for forming metal wirings of a semiconductor device - Google Patents
method for forming metal wirings of a semiconductor device Download PDFInfo
- Publication number
- GB2252448A GB2252448A GB9112054A GB9112054A GB2252448A GB 2252448 A GB2252448 A GB 2252448A GB 9112054 A GB9112054 A GB 9112054A GB 9112054 A GB9112054 A GB 9112054A GB 2252448 A GB2252448 A GB 2252448A
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- United Kingdom
- Prior art keywords
- metal wirings
- forming
- metal
- semiconductor device
- sidewall spacers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 125
- 239000002184 metal Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 239000011810 insulating material Substances 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims 2
- 229910016006 MoSi Inorganic materials 0.000 claims 1
- 229910004304 SiNy Inorganic materials 0.000 claims 1
- 229910008484 TiSi Inorganic materials 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 239000011295 pitch Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- -1 silicide nitride Chemical class 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for forming metal wirings of a semiconductor device includes the steps of, forming metal wirings (15) arranged at regular intervals, forming sidewall spacers (18) made of an insulating material on the metal wirings (15) by means of an etchback method, and forming other metal wirings (21) in spaces between the first metal wirings (15) by means of an etchback method. The distance between the metal wirings is determined by the thickness of the sidewall spacers (18). Therefore, the distance between the metal wirings can be reduced to about 0.1 mu m. Also, the sidewall spacers (18) formed between the metal wirings improve the coverage of an insulating layer 22. Accordingly, this method can be utilized in manufacturing 64M and 256M DRAMs. <IMAGE>
Description
2 -2 5 2 4 4 8 1 METHOD FOR FORMING METAL WIRINGS OF A SEMICONDUCTOR
DEVICE The present invention relates to a method for forming metal wirings of a semiconductor device, and particularly to a method for forming metal wirings of VLSI (very-large-scale integrated) semiconductor devices having a metal wiring pitch at sub-micron dimensions.
Recently, the development in miniaturizing techniques at sub-micron dimensions has brought about rapid and remarkable increases in the integration density of semiconductor memory devices. In DRAM devices, for example, 4M DRAMs on a 0.8pm design rule are now produced in volume, 16M DRAMs are being shifted from the trial stage to mass production, and 64M and 256M DRAMs on a 0.!':im design rule are now under active study. Along with these advances in VLSI (very-large-scale integration) of semiconductor memory devices, it is essential to perform multiple layer metallization, and the spacing between metal wirings is narrowed.
Generally, the conventional method for forming metal wirings is carried out by sequential processes to form contact holes, then form metal wirings, and to cover the surface of the obtained structure with a passivation film. Therefore, a problem is pointed out that the coverage of the passivation film covering the metal wirings is non-conformal due to the stepped structure of the metal wirings. Also, the narrow gaps between metal wirings produce voids in the passivation film. Furthermore, the inferior flatness of the passivation film leads not only to difficulties in subsequent second metal wirings processing, but also, in 2 severe cases, further deterioration such as disconnections of the metal wiring. In addition, the void causes shorts between metal wirings. These inferior metal wirings decrease the reliability and the yield of the device. Therefore, a new metal wirings technique is required to realize the 64M and 256M DRAMs.
It is an object of the present invention to provide a method for forming metal wirings of a semiconductor device having a wiring pitch at halfmicron dimensions, to solve the above described problems of the conventional technique.
It is another object of the present invention to provide a method for forming metal wirings of a semiconductor device capable of improving the planarization thereof in subsequent processing.
According to one aspect of the present invention, there is provided a method for forming metal wirings of the semiconductor device according to the present invention comprising the steps of:
forming contact holes in a first insulating layer formed on a semiconductor substrate; forming a first smooth metal layer on the entire surface of the resultant structure after the contact hole formation process so as to completely fill up the contact holes; forming first metal wirings arranged at regular intervals by means of a photolithography process, of the first smooth metal layer in order to form a half of the metal wirings; forming sidewall spacers of a second insulating layer on the respective side surfaces of the first metal wirings and simultaneously etching the first insulating layer between the 3 sidewall spacers to an even depth; forming a second smooth metal layer on the entire surface of the resultant structure after the etching process so as to completely fill up the spaces between the sidewall spacers; and forming second metal wirings arranged in the spaces by means of an anisotropic etching process of the smooth second metal layer in order to f orm, the other half of said metal wirings, the second metal wirings being insulated from the f irst metal wirings by the sidewall spacers.
In the present invention as described above, the remaining half of the metal wirings are arranged adjacent to one another and are formed between the previously formed first half of the metal wirings. The method for forming metal wirings of the semiconductor device according to the present invention is performed by forming the first metal layer into a pattern of half of all the metal wirings in advance via photolithography, forming insulating spacers on both side walls of the metal wirings via an etchback process, and etching the second metal layer successively deposited thereon by an etchback process, thereby forming the remaining half of the metal wirings. Therefore, the spacing between each metal wiring can be adjusted by the size of the side wall spacers via a single masking process similar to the conventional method. As a result, it is possible to obtain metal wiring spaces down to approximately 0.34im.
Embodiments of the present invention will be described, by way of example, with reference to the accompanying drawings, in which:
Figures 1A to ID are sectional views showing a process 4 for forming metal wirings according to a conventional method; and Figures 2A to 21 are sectional views showing a process for forming metal wirings according to an embodiment of the present invention.
In order to further the understanding of the present invention, a conventional method for forming metal wirings of a semiconductor device will be described with reference to Figures 1A to 1D.
Referring to Figure 1A, an inter- insulating layer 2 covers a semiconductor substrate 1. A contact hole 3 is formed into the interinsulating layer 2. Successively, a barrier layer 4 made of a refractory metal is covered over the entire surface of the structure. Referring to Figure 1B, a metal layer 5 is formed over the barrier layer 4 by depositing an aluminum or an aluminum alloy via sputtering or CVD (Chemical Vapor Deposition), filling the contact hole 3. Then, a photoresist covers the metal layer 5, then photoresist pattern 6 is formed via photolithography. Referring to Figure 1C, metal wirings 7 are formed by etching the metal layer 5 and the barrier layer 4 using the photoresist pattern 6 as a mask. Thereafter, as illustrated in Figure 1D, a passivation film 8, made of a PSG (PhosphorSilicate Glass) layer or a BPSG (Boro-Phosphorous-Silicate Glass) layer is coated over the entire surface of the structure, thereby completing the process for forming metal wirings.
In the conventional process for forming metal wirings as described above, the metal layer is etched by lithography to form the metal wirings, prior to coating the passivation f ilm over the entire structure. Accordingly, the narrower the distance between the metal wirings is, the larger the aspect ratio of the groove between each metal wiring becomes. A larger aspect ratio leads to the creation of voids in the grooves, during the coating of the passivation film. Further, the surface of the passivation film becomes rough because of the stepped structure of the metal wirings. The occurrence of voids and the deterioration in planarization decreases the reliability of the metal wirings, and makes the succeeding process difficult.
The forming process of metal wirings according to an embodiment of the present invention will now be described with reference to Figures 2A to 21.
Referring to Figure 2A, a first insulating layer 11 which is an oxide layer, is formed over a silicon semiconductor substrate 10. Then, contact holes 12 are formed in the first insulating layer 11.
Referring to Figure 2B, an aluminum alloyed in conjunction with Si, Cu, Ti, Pd, Hf or B, is deposited by sputtering or CVD method, to completely fill up the contact holes 12. Thus, a first metal layer 13 is formed on the entire surface of the resultant structure. Here, a barrier layer which is made of a refractory metal or a silicide of a refractory metal such as titanium/titanium nitride (Ti/TiN), molybdenum silicide (MoSix), titanium tungsten (TiW), titanium silicide (TiSix) and tungsten (W), can be formed before depositing the aluminum alloy.
Referring to Figure 2C, a photoresist covers the metal layer 13. Then, photoresist pattern 14 is formed by photolithography. Here, the photoresist pattern 14 is provided l, 6 to form alternately first half of the metal wirings among whole metal wirings. If metal wirings with wider linewidths are previously formed during this process, they are thus less affected by any succeeding etch process than metal wirings with narrower linewidths.
Referring to Figure 2D, the first metal layer 13, is etched using the photoresist pattern 14 as a mask. Then, the pnotoresist pattern 14 is removed, forming half of the metal wirings 15 and leaving metal layqr 16 filling the contact holes.
Referring to Figure 2E, a second insulating layer 17 of a compound such as silicide nitride (SixNy), silicide oxide nitride (SixOyNz), undoped silicate glass (USG), PSG or BPSG is evenly applied over the entire surface of the structure obtained by the above.
Referring to Figure 2F, the second insulating layer 17 is wholly etched over the entire area thereof via an etchback process, and leaving side wall spacers 18, made of the second insulating layer material formed on the side walls of the first half of the metal wirings 15. During this etching process, it is preferable that the second insulating layer 17 is adequately overetched, so that the grooves 19 between the metal wirings 15 are cut deeper than the bottom of the metal wirings, and so that the varying depth of adjacent metal wirings decreases parasitic capacitance between each metal wiring.
Referring to Figure 2G, an aluminum alloy layer is deposited via a CVD or sputtering method to completely fill the grooves 19, thereby forming a second metal layer 20.
Referring to Figure 2H, the deposited second metal 7 layer 20 is wholly etched over the entire area thereof by an etchback process, so that remaining half of the metal wirings 21 are formed within the grooves 19 between the previously formed first half of the metal wirings 15.
Referring to Figure 21, a third insulating layer 22 made of the same material as the side wall spacers covers over the entire surface of the structure to have a generally planarized surface, thereby completing the process for forming metal wirings.
In the aforesaid metal wirings forming process according to the present invention, since side wall spacers are formed between metal wirings, it is possible to improve the planarization of the third insulating layer, and to prevent any void occurrence therein.
Further, since the photolithography process is performed once as in the conventional metallization process, the remaining half of the metal wirings can be self-aligned with the first half of the metal wirings. Also, the spacing between each metal wiring can be narrowed to O.lpm, by merely adjusting the width of the side wall spacers. Therefore, a method for forming metal wirings of the semiconductor device according to the present invention can be utilized in making 64M and 256M DRAMs.
1 8
Claims (13)
1. A method for forming metal wirings of a semiconductor device comprising the steps of: forming contact holes in a f irst insulating layer formed on a semiconductor substrate; forming a f irst smooth metal layer on the entire surface of the resultant structure after said contact hole formation process so as to fill up completely said contact holes; forming first metal wirings arranged at regular intervals by means of a photolithography process of said first smooth metal layer in order to form a half of said metal wirings; forming sidewall spacers of a second insulating layer on the respective side surfaces of said first metal wirings and simultaneously etching said first insulating layer between said sidewall spacers to an even depth; forming a second smooth metal layer on the entire surf ace of the resultant structure after said etching process so as to fill up completely the spaces between said sidewall spacers; and f orming second metal wirings arranged in said spaces by anisotropic etching said smooth second metal layer in order to form the other half of said metal wirings, said second metal wirings being insulated from said first metal wirings by said sidewall spacers.
2.
A method for forming metal wirings of a semiconductor 9 device as claimed in claim 1, wherein said metal layers are deposited by any one of a high temperature sputtering method and a chemical vapour deposition method.
3. A method for forming metal wirings of a semiconductor device as claimed in claim 1 or 2. wherein said metal layers comprise any one of an aluminium and an aluminium alloy.
4. A method for forming metal wirings of a semiconductor device as claimed in any preceding claim, wherein said metal layers comprise an aluminium, alloyed in conjunction with any one among Si, Cu, Ti, Pd, Hf and B.
5. A method for forming metal wirings of a semiconductor device as claimed in any preceding claim, wherein said metal layers consist of a barrier layer and an aluminium alloy which are stacked.
6. A method for forming metal wirings of a semiconductor device as claimed in claim 5, wherein said barrier layer comprises any one among Ti/TiN, MoSi,, TiW, TiSi, and W.
7. A method for forming metal wirings of semiconductor device as claimed in any preceding claim, wherein said sidewall spacers are made of any one among SiNy, Si,OYN,, USG, PSG, and BPSG.
8.
A method for forming metal wirings of a semiconductor device as claimed in any preceding claim, wherein said process for forming said sidewall spacers comprises the steps of: depositing said second insulating layer on the entire surface of the resultant structure after said first metal wiring formation process by any one of a plasma low temperature deposition method and an atmosphere pressure chemical vapour deposition method; and etching said second insulating layer by means of an etchback method.
9. A method for forming metal wirings of a semiconductor device as claimed in any preceding claim, wherein the thickness of said sidewall spacers is above 0.34im.
10. A method for forming metal wirings of a semiconductor device comprising the steps of: forming a half of said metal wirings arranged at intervals of two pitches of said metal wirings; forming sidewall spacers made of an insulating material on the side surface of the half of said metal wirings by means of an etchback method; and f orming the other half of said metal wirings in spaces between the half of said metal wirings by means of an etchback method, the other half of said metal wirings being self-aligned to the half of said metal wirings and being separated from the half of said metal wirings by said sidewall spacers.
A method for f orming metal wirings of a semiconductor 1 device substantially as hereinbef ore described with reference to any of Figures 2A to 21 of the accompanying drawings.
12. A semiconductor device comprising metal wirings formed by the method claimed in any preceding claim.
13. A semiconductor device substantially as herein described with reference to Figure 21 of the accompanying drawings. %
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910001861A KR930006128B1 (en) | 1991-01-31 | 1991-01-31 | Metal wiring method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9112054D0 GB9112054D0 (en) | 1991-07-24 |
| GB2252448A true GB2252448A (en) | 1992-08-05 |
| GB2252448B GB2252448B (en) | 1995-03-22 |
Family
ID=19310706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9112054A Expired - Lifetime GB2252448B (en) | 1991-01-31 | 1991-06-05 | Method for forming metal wirings of a semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0789566B2 (en) |
| KR (1) | KR930006128B1 (en) |
| DE (1) | DE4118380C2 (en) |
| FR (1) | FR2672429B1 (en) |
| GB (1) | GB2252448B (en) |
| IT (1) | IT1247972B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0580290A1 (en) * | 1992-06-24 | 1994-01-26 | AT&T Corp. | Self-aligned method of fabricating closely spaced apart metallization lines |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100352909B1 (en) * | 2000-03-17 | 2002-09-16 | 삼성전자 주식회사 | Method of forming self-aligned contact structure in semiconductor device and self-aligned contact structure fabricated thereby |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0026953A1 (en) * | 1979-10-08 | 1981-04-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
| US4400865A (en) * | 1980-07-08 | 1983-08-30 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
| EP0162774A2 (en) * | 1984-05-15 | 1985-11-27 | Digital Equipment Corporation | Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby |
| US4826781A (en) * | 1986-03-04 | 1989-05-02 | Seiko Epson Corporation | Semiconductor device and method of preparation |
| EP0334761A1 (en) * | 1988-03-23 | 1989-09-27 | STMicroelectronics, Inc. | Method for forming a self-aligned source/drain contact for a MOS transistor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4424621A (en) * | 1981-12-30 | 1984-01-10 | International Business Machines Corporation | Method to fabricate stud structure for self-aligned metallization |
| JPS61270870A (en) * | 1985-05-25 | 1986-12-01 | Mitsubishi Electric Corp | Semiconductor device |
| US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
| IT1225624B (en) * | 1988-10-20 | 1990-11-22 | Sgs Thomson Microelectronics | SELF-ALIGNED METAL-SEMICONDUCTOR CONTACT PROCEDURE IN INTEGRATED DEVICES CONTAINING MISFET STRUCTURES |
-
1991
- 1991-01-31 KR KR1019910001861A patent/KR930006128B1/en not_active IP Right Cessation
- 1991-06-03 FR FR9106646A patent/FR2672429B1/en not_active Expired - Lifetime
- 1991-06-04 IT ITMI911517A patent/IT1247972B/en active IP Right Grant
- 1991-06-05 DE DE4118380A patent/DE4118380C2/en not_active Expired - Lifetime
- 1991-06-05 GB GB9112054A patent/GB2252448B/en not_active Expired - Lifetime
- 1991-06-14 JP JP3170608A patent/JPH0789566B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0026953A1 (en) * | 1979-10-08 | 1981-04-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
| US4400865A (en) * | 1980-07-08 | 1983-08-30 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
| EP0162774A2 (en) * | 1984-05-15 | 1985-11-27 | Digital Equipment Corporation | Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby |
| US4826781A (en) * | 1986-03-04 | 1989-05-02 | Seiko Epson Corporation | Semiconductor device and method of preparation |
| EP0334761A1 (en) * | 1988-03-23 | 1989-09-27 | STMicroelectronics, Inc. | Method for forming a self-aligned source/drain contact for a MOS transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0580290A1 (en) * | 1992-06-24 | 1994-01-26 | AT&T Corp. | Self-aligned method of fabricating closely spaced apart metallization lines |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1247972B (en) | 1995-01-05 |
| FR2672429A1 (en) | 1992-08-07 |
| GB2252448B (en) | 1995-03-22 |
| ITMI911517A1 (en) | 1992-12-04 |
| FR2672429B1 (en) | 1997-03-14 |
| KR920015491A (en) | 1992-08-27 |
| JPH0789566B2 (en) | 1995-09-27 |
| KR930006128B1 (en) | 1993-07-07 |
| JPH04249346A (en) | 1992-09-04 |
| DE4118380C2 (en) | 1994-01-20 |
| GB9112054D0 (en) | 1991-07-24 |
| ITMI911517A0 (en) | 1991-06-04 |
| DE4118380A1 (en) | 1992-08-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Expiry date: 20110604 |